1 /** 2 * @file spi17y_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module. 4 */ 5 6 /* **************************************************************************** 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included 17 * in all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Except as contained in this notice, the name of Maxim Integrated 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated 29 * Products, Inc. Branding Policy. 30 * 31 * The mere transfer of this software does not imply any licenses 32 * of trade secrets, proprietary technology, copyrights, patents, 33 * trademarks, maskwork rights, or any other form of intellectual 34 * property whatsoever. Maxim Integrated Products, Inc. retains all 35 * ownership rights. 36 * 37 * 38 *************************************************************************** */ 39 40 #ifndef _SPI17Y_REGS_H_ 41 #define _SPI17Y_REGS_H_ 42 43 /* **** Includes **** */ 44 #include <stdint.h> 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 #if defined (__ICCARM__) 51 #pragma system_include 52 #endif 53 54 #if defined (__CC_ARM) 55 #pragma anon_unions 56 #endif 57 /// @cond 58 /* 59 If types are not defined elsewhere (CMSIS) define them here 60 */ 61 #ifndef __IO 62 #define __IO volatile 63 #endif 64 #ifndef __I 65 #define __I volatile const 66 #endif 67 #ifndef __O 68 #define __O volatile 69 #endif 70 #ifndef __R 71 #define __R volatile const 72 #endif 73 /// @endcond 74 75 /* **** Definitions **** */ 76 77 /** 78 * @ingroup spi17y 79 * @defgroup spi17y_registers SPI17Y_Registers 80 * @brief Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module. 81 * @details SPI peripheral. 82 */ 83 84 /** 85 * @ingroup spi17y_registers 86 * Structure type to access the SPI17Y Registers. 87 */ 88 typedef struct { 89 union{ 90 __IO uint32_t data32; /**< <tt>\b 0x00:</tt> SPI17Y DATA32 Register */ 91 __IO uint16_t data16[2]; /**< <tt>\b 0x00:</tt> SPI17Y DATA16 Register */ 92 __IO uint8_t data8[4]; /**< <tt>\b 0x00:</tt> SPI17Y DATA8 Register */ 93 }; 94 __IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPI17Y CTRL0 Register */ 95 __IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPI17Y CTRL1 Register */ 96 __IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI17Y CTRL2 Register */ 97 __IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPI17Y SS_TIME Register */ 98 __IO uint32_t clk_cfg; /**< <tt>\b 0x14:</tt> SPI17Y CLK_CFG Register */ 99 __R uint32_t rsv_0x18; 100 __IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI17Y DMA Register */ 101 __IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPI17Y INT_FL Register */ 102 __IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPI17Y INT_EN Register */ 103 __IO uint32_t wake_fl; /**< <tt>\b 0x28:</tt> SPI17Y WAKE_FL Register */ 104 __IO uint32_t wake_en; /**< <tt>\b 0x2C:</tt> SPI17Y WAKE_EN Register */ 105 __I uint32_t stat; /**< <tt>\b 0x30:</tt> SPI17Y STAT Register */ 106 } mxc_spi17y_regs_t; 107 108 /* Register offsets for module SPI17Y */ 109 /** 110 * @ingroup spi17y_registers 111 * @defgroup SPI17Y_Register_Offsets Register Offsets 112 * @brief SPI17Y Peripheral Register Offsets from the SPI17Y Base Peripheral Address. 113 * @{ 114 */ 115 #define MXC_R_SPI17Y_DATA32 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: <tt> 0x0000</tt> */ 116 #define MXC_R_SPI17Y_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: <tt> 0x0000</tt> */ 117 #define MXC_R_SPI17Y_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: <tt> 0x0000</tt> */ 118 #define MXC_R_SPI17Y_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI17Y Base Address: <tt> 0x0004</tt> */ 119 #define MXC_R_SPI17Y_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI17Y Base Address: <tt> 0x0008</tt> */ 120 #define MXC_R_SPI17Y_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI17Y Base Address: <tt> 0x000C</tt> */ 121 #define MXC_R_SPI17Y_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI17Y Base Address: <tt> 0x0010</tt> */ 122 #define MXC_R_SPI17Y_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI17Y Base Address: <tt> 0x0014</tt> */ 123 #define MXC_R_SPI17Y_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI17Y Base Address: <tt> 0x001C</tt> */ 124 #define MXC_R_SPI17Y_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI17Y Base Address: <tt> 0x0020</tt> */ 125 #define MXC_R_SPI17Y_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI17Y Base Address: <tt> 0x0024</tt> */ 126 #define MXC_R_SPI17Y_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI17Y Base Address: <tt> 0x0028</tt> */ 127 #define MXC_R_SPI17Y_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI17Y Base Address: <tt> 0x002C</tt> */ 128 #define MXC_R_SPI17Y_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI17Y Base Address: <tt> 0x0030</tt> */ 129 /**@} end of group spi17y_registers */ 130 131 /** 132 * @ingroup spi17y_registers 133 * @defgroup SPI17Y_DATA32 SPI17Y_DATA32 134 * @brief Register for reading and writing the FIFO. 135 * @{ 136 */ 137 #define MXC_F_SPI17Y_DATA32_DATA_POS 0 /**< DATA32_DATA Position */ 138 #define MXC_F_SPI17Y_DATA32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI17Y_DATA32_DATA_POS)) /**< DATA32_DATA Mask */ 139 140 /**@} end of group SPI17Y_DATA32_Register */ 141 142 /** 143 * @ingroup spi17y_registers 144 * @defgroup SPI17Y_DATA16 SPI17Y_DATA16 145 * @brief Register for reading and writing the FIFO. 146 * @{ 147 */ 148 #define MXC_F_SPI17Y_DATA16_DATA_POS 0 /**< DATA16_DATA Position */ 149 #define MXC_F_SPI17Y_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI17Y_DATA16_DATA_POS)) /**< DATA16_DATA Mask */ 150 151 /**@} end of group SPI17Y_DATA16_Register */ 152 153 /** 154 * @ingroup spi17y_registers 155 * @defgroup SPI17Y_DATA8 SPI17Y_DATA8 156 * @brief Register for reading and writing the FIFO. 157 * @{ 158 */ 159 #define MXC_F_SPI17Y_DATA8_DATA_POS 0 /**< DATA8_DATA Position */ 160 #define MXC_F_SPI17Y_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI17Y_DATA8_DATA_POS)) /**< DATA8_DATA Mask */ 161 162 /**@} end of group SPI17Y_DATA8_Register */ 163 164 /** 165 * @ingroup spi17y_registers 166 * @defgroup SPI17Y_CTRL0 SPI17Y_CTRL0 167 * @brief Register for controlling SPI peripheral. 168 * @{ 169 */ 170 #define MXC_F_SPI17Y_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ 171 #define MXC_F_SPI17Y_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ 172 #define MXC_V_SPI17Y_CTRL0_EN_DIS ((uint32_t)0x0UL) /**< CTRL0_EN_DIS Value */ 173 #define MXC_S_SPI17Y_CTRL0_EN_DIS (MXC_V_SPI17Y_CTRL0_EN_DIS << MXC_F_SPI17Y_CTRL0_EN_POS) /**< CTRL0_EN_DIS Setting */ 174 #define MXC_V_SPI17Y_CTRL0_EN_EN ((uint32_t)0x1UL) /**< CTRL0_EN_EN Value */ 175 #define MXC_S_SPI17Y_CTRL0_EN_EN (MXC_V_SPI17Y_CTRL0_EN_EN << MXC_F_SPI17Y_CTRL0_EN_POS) /**< CTRL0_EN_EN Setting */ 176 177 #define MXC_F_SPI17Y_CTRL0_MASTER_POS 1 /**< CTRL0_MASTER Position */ 178 #define MXC_F_SPI17Y_CTRL0_MASTER ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_MASTER_POS)) /**< CTRL0_MASTER Mask */ 179 #define MXC_V_SPI17Y_CTRL0_MASTER_DIS ((uint32_t)0x0UL) /**< CTRL0_MASTER_DIS Value */ 180 #define MXC_S_SPI17Y_CTRL0_MASTER_DIS (MXC_V_SPI17Y_CTRL0_MASTER_DIS << MXC_F_SPI17Y_CTRL0_MASTER_POS) /**< CTRL0_MASTER_DIS Setting */ 181 #define MXC_V_SPI17Y_CTRL0_MASTER_EN ((uint32_t)0x1UL) /**< CTRL0_MASTER_EN Value */ 182 #define MXC_S_SPI17Y_CTRL0_MASTER_EN (MXC_V_SPI17Y_CTRL0_MASTER_EN << MXC_F_SPI17Y_CTRL0_MASTER_POS) /**< CTRL0_MASTER_EN Setting */ 183 184 #define MXC_F_SPI17Y_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ 185 #define MXC_F_SPI17Y_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ 186 #define MXC_V_SPI17Y_CTRL0_SS_IO_OUTPUT ((uint32_t)0x0UL) /**< CTRL0_SS_IO_OUTPUT Value */ 187 #define MXC_S_SPI17Y_CTRL0_SS_IO_OUTPUT (MXC_V_SPI17Y_CTRL0_SS_IO_OUTPUT << MXC_F_SPI17Y_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_OUTPUT Setting */ 188 #define MXC_V_SPI17Y_CTRL0_SS_IO_INPUT ((uint32_t)0x1UL) /**< CTRL0_SS_IO_INPUT Value */ 189 #define MXC_S_SPI17Y_CTRL0_SS_IO_INPUT (MXC_V_SPI17Y_CTRL0_SS_IO_INPUT << MXC_F_SPI17Y_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_INPUT Setting */ 190 191 #define MXC_F_SPI17Y_CTRL0_START_POS 5 /**< CTRL0_START Position */ 192 #define MXC_F_SPI17Y_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_START_POS)) /**< CTRL0_START Mask */ 193 #define MXC_V_SPI17Y_CTRL0_START_START ((uint32_t)0x1UL) /**< CTRL0_START_START Value */ 194 #define MXC_S_SPI17Y_CTRL0_START_START (MXC_V_SPI17Y_CTRL0_START_START << MXC_F_SPI17Y_CTRL0_START_POS) /**< CTRL0_START_START Setting */ 195 196 #define MXC_F_SPI17Y_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ 197 #define MXC_F_SPI17Y_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ 198 #define MXC_V_SPI17Y_CTRL0_SS_CTRL_DEASSERT ((uint32_t)0x0UL) /**< CTRL0_SS_CTRL_DEASSERT Value */ 199 #define MXC_S_SPI17Y_CTRL0_SS_CTRL_DEASSERT (MXC_V_SPI17Y_CTRL0_SS_CTRL_DEASSERT << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_DEASSERT Setting */ 200 #define MXC_V_SPI17Y_CTRL0_SS_CTRL_ASSERT ((uint32_t)0x1UL) /**< CTRL0_SS_CTRL_ASSERT Value */ 201 #define MXC_S_SPI17Y_CTRL0_SS_CTRL_ASSERT (MXC_V_SPI17Y_CTRL0_SS_CTRL_ASSERT << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_ASSERT Setting */ 202 203 #define MXC_F_SPI17Y_CTRL0_SS_POS 16 /**< CTRL0_SS Position */ 204 #define MXC_F_SPI17Y_CTRL0_SS ((uint32_t)(0xFUL << MXC_F_SPI17Y_CTRL0_SS_POS)) /**< CTRL0_SS Mask */ 205 #define MXC_V_SPI17Y_CTRL0_SS_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SS0 Value */ 206 #define MXC_S_SPI17Y_CTRL0_SS_SS0 (MXC_V_SPI17Y_CTRL0_SS_SS0 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS0 Setting */ 207 #define MXC_V_SPI17Y_CTRL0_SS_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SS1 Value */ 208 #define MXC_S_SPI17Y_CTRL0_SS_SS1 (MXC_V_SPI17Y_CTRL0_SS_SS1 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS1 Setting */ 209 #define MXC_V_SPI17Y_CTRL0_SS_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SS2 Value */ 210 #define MXC_S_SPI17Y_CTRL0_SS_SS2 (MXC_V_SPI17Y_CTRL0_SS_SS2 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS2 Setting */ 211 #define MXC_V_SPI17Y_CTRL0_SS_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SS3 Value */ 212 #define MXC_S_SPI17Y_CTRL0_SS_SS3 (MXC_V_SPI17Y_CTRL0_SS_SS3 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS3 Setting */ 213 214 /**@} end of group SPI17Y_CTRL0_Register */ 215 216 /** 217 * @ingroup spi17y_registers 218 * @defgroup SPI17Y_CTRL1 SPI17Y_CTRL1 219 * @brief Register for controlling SPI peripheral. 220 * @{ 221 */ 222 #define MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ 223 #define MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ 224 225 #define MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ 226 #define MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ 227 228 /**@} end of group SPI17Y_CTRL1_Register */ 229 230 /** 231 * @ingroup spi17y_registers 232 * @defgroup SPI17Y_CTRL2 SPI17Y_CTRL2 233 * @brief Register for controlling SPI peripheral. 234 * @{ 235 */ 236 #define MXC_F_SPI17Y_CTRL2_CPHA_POS 0 /**< CTRL2_CPHA Position */ 237 #define MXC_F_SPI17Y_CTRL2_CPHA ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_CPHA_POS)) /**< CTRL2_CPHA Mask */ 238 #define MXC_V_SPI17Y_CTRL2_CPHA_RISING_EDGE ((uint32_t)0x0UL) /**< CTRL2_CPHA_RISING_EDGE Value */ 239 #define MXC_S_SPI17Y_CTRL2_CPHA_RISING_EDGE (MXC_V_SPI17Y_CTRL2_CPHA_RISING_EDGE << MXC_F_SPI17Y_CTRL2_CPHA_POS) /**< CTRL2_CPHA_RISING_EDGE Setting */ 240 #define MXC_V_SPI17Y_CTRL2_CPHA_FALLING_EDGE ((uint32_t)0x1UL) /**< CTRL2_CPHA_FALLING_EDGE Value */ 241 #define MXC_S_SPI17Y_CTRL2_CPHA_FALLING_EDGE (MXC_V_SPI17Y_CTRL2_CPHA_FALLING_EDGE << MXC_F_SPI17Y_CTRL2_CPHA_POS) /**< CTRL2_CPHA_FALLING_EDGE Setting */ 242 243 #define MXC_F_SPI17Y_CTRL2_CPOL_POS 1 /**< CTRL2_CPOL Position */ 244 #define MXC_F_SPI17Y_CTRL2_CPOL ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_CPOL_POS)) /**< CTRL2_CPOL Mask */ 245 #define MXC_V_SPI17Y_CTRL2_CPOL_NORMAL ((uint32_t)0x0UL) /**< CTRL2_CPOL_NORMAL Value */ 246 #define MXC_S_SPI17Y_CTRL2_CPOL_NORMAL (MXC_V_SPI17Y_CTRL2_CPOL_NORMAL << MXC_F_SPI17Y_CTRL2_CPOL_POS) /**< CTRL2_CPOL_NORMAL Setting */ 247 #define MXC_V_SPI17Y_CTRL2_CPOL_INVERTED ((uint32_t)0x1UL) /**< CTRL2_CPOL_INVERTED Value */ 248 #define MXC_S_SPI17Y_CTRL2_CPOL_INVERTED (MXC_V_SPI17Y_CTRL2_CPOL_INVERTED << MXC_F_SPI17Y_CTRL2_CPOL_POS) /**< CTRL2_CPOL_INVERTED Setting */ 249 250 #define MXC_F_SPI17Y_CTRL2_SCLK_INV_POS 4 /**< CTRL2_SCLK_INV Position */ 251 #define MXC_F_SPI17Y_CTRL2_SCLK_INV ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_SCLK_INV_POS)) /**< CTRL2_SCLK_INV Mask */ 252 253 #define MXC_F_SPI17Y_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ 254 #define MXC_F_SPI17Y_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI17Y_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ 255 #define MXC_V_SPI17Y_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */ 256 #define MXC_S_SPI17Y_CTRL2_NUMBITS_0 (MXC_V_SPI17Y_CTRL2_NUMBITS_0 << MXC_F_SPI17Y_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */ 257 258 #define MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ 259 #define MXC_F_SPI17Y_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ 260 #define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ 261 #define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ 262 #define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ 263 #define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ 264 #define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ 265 #define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ 266 267 #define MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ 268 #define MXC_F_SPI17Y_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ 269 #define MXC_V_SPI17Y_CTRL2_THREE_WIRE_DIS ((uint32_t)0x0UL) /**< CTRL2_THREE_WIRE_DIS Value */ 270 #define MXC_S_SPI17Y_CTRL2_THREE_WIRE_DIS (MXC_V_SPI17Y_CTRL2_THREE_WIRE_DIS << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_DIS Setting */ 271 #define MXC_V_SPI17Y_CTRL2_THREE_WIRE_EN ((uint32_t)0x1UL) /**< CTRL2_THREE_WIRE_EN Value */ 272 #define MXC_S_SPI17Y_CTRL2_THREE_WIRE_EN (MXC_V_SPI17Y_CTRL2_THREE_WIRE_EN << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_EN Setting */ 273 274 #define MXC_F_SPI17Y_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ 275 #define MXC_F_SPI17Y_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ 276 #define MXC_V_SPI17Y_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ 277 #define MXC_S_SPI17Y_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ 278 #define MXC_V_SPI17Y_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ 279 #define MXC_S_SPI17Y_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ 280 #define MXC_V_SPI17Y_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ 281 #define MXC_S_SPI17Y_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ 282 #define MXC_V_SPI17Y_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */ 283 #define MXC_S_SPI17Y_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */ 284 285 #define MXC_F_SPI17Y_CTRL2_SRPOL_POS 24 /**< CTRL2_SRPOL Position */ 286 #define MXC_F_SPI17Y_CTRL2_SRPOL ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CTRL2_SRPOL_POS)) /**< CTRL2_SRPOL Mask */ 287 #define MXC_V_SPI17Y_CTRL2_SRPOL_SR0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SRPOL_SR0_HIGH Value */ 288 #define MXC_S_SPI17Y_CTRL2_SRPOL_SR0_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR0_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR0_HIGH Setting */ 289 #define MXC_V_SPI17Y_CTRL2_SRPOL_SR1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SRPOL_SR1_HIGH Value */ 290 #define MXC_S_SPI17Y_CTRL2_SRPOL_SR1_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR1_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR1_HIGH Setting */ 291 #define MXC_V_SPI17Y_CTRL2_SRPOL_SR2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SRPOL_SR2_HIGH Value */ 292 #define MXC_S_SPI17Y_CTRL2_SRPOL_SR2_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR2_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR2_HIGH Setting */ 293 #define MXC_V_SPI17Y_CTRL2_SRPOL_SR3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SRPOL_SR3_HIGH Value */ 294 #define MXC_S_SPI17Y_CTRL2_SRPOL_SR3_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR3_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR3_HIGH Setting */ 295 #define MXC_V_SPI17Y_CTRL2_SRPOL_SR4_HIGH ((uint32_t)0x10UL) /**< CTRL2_SRPOL_SR4_HIGH Value */ 296 #define MXC_S_SPI17Y_CTRL2_SRPOL_SR4_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR4_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR4_HIGH Setting */ 297 #define MXC_V_SPI17Y_CTRL2_SRPOL_SR5_HIGH ((uint32_t)0x20UL) /**< CTRL2_SRPOL_SR5_HIGH Value */ 298 #define MXC_S_SPI17Y_CTRL2_SRPOL_SR5_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR5_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR5_HIGH Setting */ 299 #define MXC_V_SPI17Y_CTRL2_SRPOL_SR6_HIGH ((uint32_t)0x40UL) /**< CTRL2_SRPOL_SR6_HIGH Value */ 300 #define MXC_S_SPI17Y_CTRL2_SRPOL_SR6_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR6_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR6_HIGH Setting */ 301 #define MXC_V_SPI17Y_CTRL2_SRPOL_SR7_HIGH ((uint32_t)0x80UL) /**< CTRL2_SRPOL_SR7_HIGH Value */ 302 #define MXC_S_SPI17Y_CTRL2_SRPOL_SR7_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR7_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR7_HIGH Setting */ 303 304 /**@} end of group SPI17Y_CTRL2_Register */ 305 306 /** 307 * @ingroup spi17y_registers 308 * @defgroup SPI17Y_SS_TIME SPI17Y_SS_TIME 309 * @brief Register for controlling SPI peripheral/Slave Select Timing. 310 * @{ 311 */ 312 #define MXC_F_SPI17Y_SS_TIME_PRE_POS 0 /**< SS_TIME_PRE Position */ 313 #define MXC_F_SPI17Y_SS_TIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_PRE_POS)) /**< SS_TIME_PRE Mask */ 314 #define MXC_V_SPI17Y_SS_TIME_PRE_256 ((uint32_t)0x0UL) /**< SS_TIME_PRE_256 Value */ 315 #define MXC_S_SPI17Y_SS_TIME_PRE_256 (MXC_V_SPI17Y_SS_TIME_PRE_256 << MXC_F_SPI17Y_SS_TIME_PRE_POS) /**< SS_TIME_PRE_256 Setting */ 316 317 #define MXC_F_SPI17Y_SS_TIME_POST_POS 8 /**< SS_TIME_POST Position */ 318 #define MXC_F_SPI17Y_SS_TIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_POST_POS)) /**< SS_TIME_POST Mask */ 319 #define MXC_V_SPI17Y_SS_TIME_POST_256 ((uint32_t)0x0UL) /**< SS_TIME_POST_256 Value */ 320 #define MXC_S_SPI17Y_SS_TIME_POST_256 (MXC_V_SPI17Y_SS_TIME_POST_256 << MXC_F_SPI17Y_SS_TIME_POST_POS) /**< SS_TIME_POST_256 Setting */ 321 322 #define MXC_F_SPI17Y_SS_TIME_INACT_POS 16 /**< SS_TIME_INACT Position */ 323 #define MXC_F_SPI17Y_SS_TIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_INACT_POS)) /**< SS_TIME_INACT Mask */ 324 #define MXC_V_SPI17Y_SS_TIME_INACT_256 ((uint32_t)0x0UL) /**< SS_TIME_INACT_256 Value */ 325 #define MXC_S_SPI17Y_SS_TIME_INACT_256 (MXC_V_SPI17Y_SS_TIME_INACT_256 << MXC_F_SPI17Y_SS_TIME_INACT_POS) /**< SS_TIME_INACT_256 Setting */ 326 327 /**@} end of group SPI17Y_SS_TIME_Register */ 328 329 /** 330 * @ingroup spi17y_registers 331 * @defgroup SPI17Y_CLK_CFG SPI17Y_CLK_CFG 332 * @brief Register for controlling SPI clock rate. 333 * @{ 334 */ 335 #define MXC_F_SPI17Y_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */ 336 #define MXC_F_SPI17Y_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */ 337 #define MXC_V_SPI17Y_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */ 338 #define MXC_S_SPI17Y_CLK_CFG_LO_DIS (MXC_V_SPI17Y_CLK_CFG_LO_DIS << MXC_F_SPI17Y_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */ 339 340 #define MXC_F_SPI17Y_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */ 341 #define MXC_F_SPI17Y_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */ 342 #define MXC_V_SPI17Y_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */ 343 #define MXC_S_SPI17Y_CLK_CFG_HI_DIS (MXC_V_SPI17Y_CLK_CFG_HI_DIS << MXC_F_SPI17Y_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */ 344 345 #define MXC_F_SPI17Y_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */ 346 #define MXC_F_SPI17Y_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI17Y_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */ 347 348 /**@} end of group SPI17Y_CLK_CFG_Register */ 349 350 /** 351 * @ingroup spi17y_registers 352 * @defgroup SPI17Y_DMA SPI17Y_DMA 353 * @brief Register for controlling DMA. 354 * @{ 355 */ 356 #define MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ 357 #define MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ 358 359 #define MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ 360 #define MXC_F_SPI17Y_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ 361 #define MXC_V_SPI17Y_DMA_TX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_FIFO_EN_DIS Value */ 362 #define MXC_S_SPI17Y_DMA_TX_FIFO_EN_DIS (MXC_V_SPI17Y_DMA_TX_FIFO_EN_DIS << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_DIS Setting */ 363 #define MXC_V_SPI17Y_DMA_TX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_FIFO_EN_EN Value */ 364 #define MXC_S_SPI17Y_DMA_TX_FIFO_EN_EN (MXC_V_SPI17Y_DMA_TX_FIFO_EN_EN << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_EN Setting */ 365 366 #define MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ 367 #define MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ 368 #define MXC_V_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_CLEAR Value */ 369 #define MXC_S_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR (MXC_V_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR << MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_CLEAR Setting */ 370 371 #define MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ 372 #define MXC_F_SPI17Y_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ 373 374 #define MXC_F_SPI17Y_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ 375 #define MXC_F_SPI17Y_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ 376 #define MXC_V_SPI17Y_DMA_TX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DIS Value */ 377 #define MXC_S_SPI17Y_DMA_TX_DMA_EN_DIS (MXC_V_SPI17Y_DMA_TX_DMA_EN_DIS << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DIS Setting */ 378 #define MXC_V_SPI17Y_DMA_TX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_EN Value */ 379 #define MXC_S_SPI17Y_DMA_TX_DMA_EN_EN (MXC_V_SPI17Y_DMA_TX_DMA_EN_EN << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_EN Setting */ 380 381 #define MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ 382 #define MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ 383 384 #define MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ 385 #define MXC_F_SPI17Y_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ 386 #define MXC_V_SPI17Y_DMA_RX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_FIFO_EN_DIS Value */ 387 #define MXC_S_SPI17Y_DMA_RX_FIFO_EN_DIS (MXC_V_SPI17Y_DMA_RX_FIFO_EN_DIS << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_DIS Setting */ 388 #define MXC_V_SPI17Y_DMA_RX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_FIFO_EN_EN Value */ 389 #define MXC_S_SPI17Y_DMA_RX_FIFO_EN_EN (MXC_V_SPI17Y_DMA_RX_FIFO_EN_EN << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_EN Setting */ 390 391 #define MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ 392 #define MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ 393 #define MXC_V_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_CLEAR Value */ 394 #define MXC_S_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR (MXC_V_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR << MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_CLEAR Setting */ 395 396 #define MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ 397 #define MXC_F_SPI17Y_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ 398 399 #define MXC_F_SPI17Y_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ 400 #define MXC_F_SPI17Y_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ 401 #define MXC_V_SPI17Y_DMA_RX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DIS Value */ 402 #define MXC_S_SPI17Y_DMA_RX_DMA_EN_DIS (MXC_V_SPI17Y_DMA_RX_DMA_EN_DIS << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DIS Setting */ 403 #define MXC_V_SPI17Y_DMA_RX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_EN Value */ 404 #define MXC_S_SPI17Y_DMA_RX_DMA_EN_EN (MXC_V_SPI17Y_DMA_RX_DMA_EN_EN << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_EN Setting */ 405 406 /**@} end of group SPI17Y_DMA_Register */ 407 408 /** 409 * @ingroup spi17y_registers 410 * @defgroup SPI17Y_INT_FL SPI17Y_INT_FL 411 * @brief Register for reading and clearing interrupt flags. All bits are write 1 to 412 * clear. 413 * @{ 414 */ 415 #define MXC_F_SPI17Y_INT_FL_TX_THRESH_POS 0 /**< INT_FL_TX_THRESH Position */ 416 #define MXC_F_SPI17Y_INT_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS)) /**< INT_FL_TX_THRESH Mask */ 417 #define MXC_V_SPI17Y_INT_FL_TX_THRESH_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_THRESH_CLEAR Value */ 418 #define MXC_S_SPI17Y_INT_FL_TX_THRESH_CLEAR (MXC_V_SPI17Y_INT_FL_TX_THRESH_CLEAR << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS) /**< INT_FL_TX_THRESH_CLEAR Setting */ 419 420 #define MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */ 421 #define MXC_F_SPI17Y_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */ 422 #define MXC_V_SPI17Y_INT_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_EMPTY_CLEAR Value */ 423 #define MXC_S_SPI17Y_INT_FL_TX_EMPTY_CLEAR (MXC_V_SPI17Y_INT_FL_TX_EMPTY_CLEAR << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS) /**< INT_FL_TX_EMPTY_CLEAR Setting */ 424 425 #define MXC_F_SPI17Y_INT_FL_RX_THRESH_POS 2 /**< INT_FL_RX_THRESH Position */ 426 #define MXC_F_SPI17Y_INT_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS)) /**< INT_FL_RX_THRESH Mask */ 427 #define MXC_V_SPI17Y_INT_FL_RX_THRESH_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_THRESH_CLEAR Value */ 428 #define MXC_S_SPI17Y_INT_FL_RX_THRESH_CLEAR (MXC_V_SPI17Y_INT_FL_RX_THRESH_CLEAR << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS) /**< INT_FL_RX_THRESH_CLEAR Setting */ 429 430 #define MXC_F_SPI17Y_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */ 431 #define MXC_F_SPI17Y_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */ 432 #define MXC_V_SPI17Y_INT_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_FULL_CLEAR Value */ 433 #define MXC_S_SPI17Y_INT_FL_RX_FULL_CLEAR (MXC_V_SPI17Y_INT_FL_RX_FULL_CLEAR << MXC_F_SPI17Y_INT_FL_RX_FULL_POS) /**< INT_FL_RX_FULL_CLEAR Setting */ 434 435 #define MXC_F_SPI17Y_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */ 436 #define MXC_F_SPI17Y_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */ 437 #define MXC_V_SPI17Y_INT_FL_SSA_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSA_CLEAR Value */ 438 #define MXC_S_SPI17Y_INT_FL_SSA_CLEAR (MXC_V_SPI17Y_INT_FL_SSA_CLEAR << MXC_F_SPI17Y_INT_FL_SSA_POS) /**< INT_FL_SSA_CLEAR Setting */ 439 440 #define MXC_F_SPI17Y_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */ 441 #define MXC_F_SPI17Y_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */ 442 #define MXC_V_SPI17Y_INT_FL_SSD_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSD_CLEAR Value */ 443 #define MXC_S_SPI17Y_INT_FL_SSD_CLEAR (MXC_V_SPI17Y_INT_FL_SSD_CLEAR << MXC_F_SPI17Y_INT_FL_SSD_POS) /**< INT_FL_SSD_CLEAR Setting */ 444 445 #define MXC_F_SPI17Y_INT_FL_FAULT_POS 8 /**< INT_FL_FAULT Position */ 446 #define MXC_F_SPI17Y_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_FAULT_POS)) /**< INT_FL_FAULT Mask */ 447 #define MXC_V_SPI17Y_INT_FL_FAULT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_FAULT_CLEAR Value */ 448 #define MXC_S_SPI17Y_INT_FL_FAULT_CLEAR (MXC_V_SPI17Y_INT_FL_FAULT_CLEAR << MXC_F_SPI17Y_INT_FL_FAULT_POS) /**< INT_FL_FAULT_CLEAR Setting */ 449 450 #define MXC_F_SPI17Y_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */ 451 #define MXC_F_SPI17Y_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */ 452 #define MXC_V_SPI17Y_INT_FL_ABORT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_ABORT_CLEAR Value */ 453 #define MXC_S_SPI17Y_INT_FL_ABORT_CLEAR (MXC_V_SPI17Y_INT_FL_ABORT_CLEAR << MXC_F_SPI17Y_INT_FL_ABORT_POS) /**< INT_FL_ABORT_CLEAR Setting */ 454 455 #define MXC_F_SPI17Y_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */ 456 #define MXC_F_SPI17Y_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */ 457 #define MXC_V_SPI17Y_INT_FL_M_DONE_CLEAR ((uint32_t)0x1UL) /**< INT_FL_M_DONE_CLEAR Value */ 458 #define MXC_S_SPI17Y_INT_FL_M_DONE_CLEAR (MXC_V_SPI17Y_INT_FL_M_DONE_CLEAR << MXC_F_SPI17Y_INT_FL_M_DONE_POS) /**< INT_FL_M_DONE_CLEAR Setting */ 459 460 #define MXC_F_SPI17Y_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */ 461 #define MXC_F_SPI17Y_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */ 462 #define MXC_V_SPI17Y_INT_FL_TX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_OVR_CLEAR Value */ 463 #define MXC_S_SPI17Y_INT_FL_TX_OVR_CLEAR (MXC_V_SPI17Y_INT_FL_TX_OVR_CLEAR << MXC_F_SPI17Y_INT_FL_TX_OVR_POS) /**< INT_FL_TX_OVR_CLEAR Setting */ 464 465 #define MXC_F_SPI17Y_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */ 466 #define MXC_F_SPI17Y_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */ 467 #define MXC_V_SPI17Y_INT_FL_TX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_UND_CLEAR Value */ 468 #define MXC_S_SPI17Y_INT_FL_TX_UND_CLEAR (MXC_V_SPI17Y_INT_FL_TX_UND_CLEAR << MXC_F_SPI17Y_INT_FL_TX_UND_POS) /**< INT_FL_TX_UND_CLEAR Setting */ 469 470 #define MXC_F_SPI17Y_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */ 471 #define MXC_F_SPI17Y_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ 472 #define MXC_V_SPI17Y_INT_FL_RX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_OVR_CLEAR Value */ 473 #define MXC_S_SPI17Y_INT_FL_RX_OVR_CLEAR (MXC_V_SPI17Y_INT_FL_RX_OVR_CLEAR << MXC_F_SPI17Y_INT_FL_RX_OVR_POS) /**< INT_FL_RX_OVR_CLEAR Setting */ 474 475 #define MXC_F_SPI17Y_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */ 476 #define MXC_F_SPI17Y_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */ 477 #define MXC_V_SPI17Y_INT_FL_RX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_UND_CLEAR Value */ 478 #define MXC_S_SPI17Y_INT_FL_RX_UND_CLEAR (MXC_V_SPI17Y_INT_FL_RX_UND_CLEAR << MXC_F_SPI17Y_INT_FL_RX_UND_POS) /**< INT_FL_RX_UND_CLEAR Setting */ 479 480 /**@} end of group SPI17Y_INT_FL_Register */ 481 482 /** 483 * @ingroup spi17y_registers 484 * @defgroup SPI17Y_INT_EN SPI17Y_INT_EN 485 * @brief Register for enabling interrupts. 486 * @{ 487 */ 488 #define MXC_F_SPI17Y_INT_EN_TX_THRESH_POS 0 /**< INT_EN_TX_THRESH Position */ 489 #define MXC_F_SPI17Y_INT_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS)) /**< INT_EN_TX_THRESH Mask */ 490 #define MXC_V_SPI17Y_INT_EN_TX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_THRESH_DIS Value */ 491 #define MXC_S_SPI17Y_INT_EN_TX_THRESH_DIS (MXC_V_SPI17Y_INT_EN_TX_THRESH_DIS << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS) /**< INT_EN_TX_THRESH_DIS Setting */ 492 #define MXC_V_SPI17Y_INT_EN_TX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN_TX_THRESH_EN Value */ 493 #define MXC_S_SPI17Y_INT_EN_TX_THRESH_EN (MXC_V_SPI17Y_INT_EN_TX_THRESH_EN << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS) /**< INT_EN_TX_THRESH_EN Setting */ 494 495 #define MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */ 496 #define MXC_F_SPI17Y_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */ 497 #define MXC_V_SPI17Y_INT_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_EMPTY_DIS Value */ 498 #define MXC_S_SPI17Y_INT_EN_TX_EMPTY_DIS (MXC_V_SPI17Y_INT_EN_TX_EMPTY_DIS << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_DIS Setting */ 499 #define MXC_V_SPI17Y_INT_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< INT_EN_TX_EMPTY_EN Value */ 500 #define MXC_S_SPI17Y_INT_EN_TX_EMPTY_EN (MXC_V_SPI17Y_INT_EN_TX_EMPTY_EN << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_EN Setting */ 501 502 #define MXC_F_SPI17Y_INT_EN_RX_THRESH_POS 2 /**< INT_EN_RX_THRESH Position */ 503 #define MXC_F_SPI17Y_INT_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS)) /**< INT_EN_RX_THRESH Mask */ 504 #define MXC_V_SPI17Y_INT_EN_RX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_THRESH_DIS Value */ 505 #define MXC_S_SPI17Y_INT_EN_RX_THRESH_DIS (MXC_V_SPI17Y_INT_EN_RX_THRESH_DIS << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS) /**< INT_EN_RX_THRESH_DIS Setting */ 506 #define MXC_V_SPI17Y_INT_EN_RX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN_RX_THRESH_EN Value */ 507 #define MXC_S_SPI17Y_INT_EN_RX_THRESH_EN (MXC_V_SPI17Y_INT_EN_RX_THRESH_EN << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS) /**< INT_EN_RX_THRESH_EN Setting */ 508 509 #define MXC_F_SPI17Y_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */ 510 #define MXC_F_SPI17Y_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */ 511 #define MXC_V_SPI17Y_INT_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_FULL_DIS Value */ 512 #define MXC_S_SPI17Y_INT_EN_RX_FULL_DIS (MXC_V_SPI17Y_INT_EN_RX_FULL_DIS << MXC_F_SPI17Y_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_DIS Setting */ 513 #define MXC_V_SPI17Y_INT_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< INT_EN_RX_FULL_EN Value */ 514 #define MXC_S_SPI17Y_INT_EN_RX_FULL_EN (MXC_V_SPI17Y_INT_EN_RX_FULL_EN << MXC_F_SPI17Y_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_EN Setting */ 515 516 #define MXC_F_SPI17Y_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */ 517 #define MXC_F_SPI17Y_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */ 518 #define MXC_V_SPI17Y_INT_EN_SSA_DIS ((uint32_t)0x0UL) /**< INT_EN_SSA_DIS Value */ 519 #define MXC_S_SPI17Y_INT_EN_SSA_DIS (MXC_V_SPI17Y_INT_EN_SSA_DIS << MXC_F_SPI17Y_INT_EN_SSA_POS) /**< INT_EN_SSA_DIS Setting */ 520 #define MXC_V_SPI17Y_INT_EN_SSA_EN ((uint32_t)0x1UL) /**< INT_EN_SSA_EN Value */ 521 #define MXC_S_SPI17Y_INT_EN_SSA_EN (MXC_V_SPI17Y_INT_EN_SSA_EN << MXC_F_SPI17Y_INT_EN_SSA_POS) /**< INT_EN_SSA_EN Setting */ 522 523 #define MXC_F_SPI17Y_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */ 524 #define MXC_F_SPI17Y_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */ 525 #define MXC_V_SPI17Y_INT_EN_SSD_DIS ((uint32_t)0x0UL) /**< INT_EN_SSD_DIS Value */ 526 #define MXC_S_SPI17Y_INT_EN_SSD_DIS (MXC_V_SPI17Y_INT_EN_SSD_DIS << MXC_F_SPI17Y_INT_EN_SSD_POS) /**< INT_EN_SSD_DIS Setting */ 527 #define MXC_V_SPI17Y_INT_EN_SSD_EN ((uint32_t)0x1UL) /**< INT_EN_SSD_EN Value */ 528 #define MXC_S_SPI17Y_INT_EN_SSD_EN (MXC_V_SPI17Y_INT_EN_SSD_EN << MXC_F_SPI17Y_INT_EN_SSD_POS) /**< INT_EN_SSD_EN Setting */ 529 530 #define MXC_F_SPI17Y_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */ 531 #define MXC_F_SPI17Y_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */ 532 #define MXC_V_SPI17Y_INT_EN_FAULT_DIS ((uint32_t)0x0UL) /**< INT_EN_FAULT_DIS Value */ 533 #define MXC_S_SPI17Y_INT_EN_FAULT_DIS (MXC_V_SPI17Y_INT_EN_FAULT_DIS << MXC_F_SPI17Y_INT_EN_FAULT_POS) /**< INT_EN_FAULT_DIS Setting */ 534 #define MXC_V_SPI17Y_INT_EN_FAULT_EN ((uint32_t)0x1UL) /**< INT_EN_FAULT_EN Value */ 535 #define MXC_S_SPI17Y_INT_EN_FAULT_EN (MXC_V_SPI17Y_INT_EN_FAULT_EN << MXC_F_SPI17Y_INT_EN_FAULT_POS) /**< INT_EN_FAULT_EN Setting */ 536 537 #define MXC_F_SPI17Y_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */ 538 #define MXC_F_SPI17Y_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */ 539 #define MXC_V_SPI17Y_INT_EN_ABORT_DIS ((uint32_t)0x0UL) /**< INT_EN_ABORT_DIS Value */ 540 #define MXC_S_SPI17Y_INT_EN_ABORT_DIS (MXC_V_SPI17Y_INT_EN_ABORT_DIS << MXC_F_SPI17Y_INT_EN_ABORT_POS) /**< INT_EN_ABORT_DIS Setting */ 541 #define MXC_V_SPI17Y_INT_EN_ABORT_EN ((uint32_t)0x1UL) /**< INT_EN_ABORT_EN Value */ 542 #define MXC_S_SPI17Y_INT_EN_ABORT_EN (MXC_V_SPI17Y_INT_EN_ABORT_EN << MXC_F_SPI17Y_INT_EN_ABORT_POS) /**< INT_EN_ABORT_EN Setting */ 543 544 #define MXC_F_SPI17Y_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */ 545 #define MXC_F_SPI17Y_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */ 546 #define MXC_V_SPI17Y_INT_EN_M_DONE_DIS ((uint32_t)0x0UL) /**< INT_EN_M_DONE_DIS Value */ 547 #define MXC_S_SPI17Y_INT_EN_M_DONE_DIS (MXC_V_SPI17Y_INT_EN_M_DONE_DIS << MXC_F_SPI17Y_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_DIS Setting */ 548 #define MXC_V_SPI17Y_INT_EN_M_DONE_EN ((uint32_t)0x1UL) /**< INT_EN_M_DONE_EN Value */ 549 #define MXC_S_SPI17Y_INT_EN_M_DONE_EN (MXC_V_SPI17Y_INT_EN_M_DONE_EN << MXC_F_SPI17Y_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_EN Setting */ 550 551 #define MXC_F_SPI17Y_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */ 552 #define MXC_F_SPI17Y_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */ 553 #define MXC_V_SPI17Y_INT_EN_TX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_OVR_DIS Value */ 554 #define MXC_S_SPI17Y_INT_EN_TX_OVR_DIS (MXC_V_SPI17Y_INT_EN_TX_OVR_DIS << MXC_F_SPI17Y_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_DIS Setting */ 555 #define MXC_V_SPI17Y_INT_EN_TX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_TX_OVR_EN Value */ 556 #define MXC_S_SPI17Y_INT_EN_TX_OVR_EN (MXC_V_SPI17Y_INT_EN_TX_OVR_EN << MXC_F_SPI17Y_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_EN Setting */ 557 558 #define MXC_F_SPI17Y_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */ 559 #define MXC_F_SPI17Y_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */ 560 #define MXC_V_SPI17Y_INT_EN_TX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_UND_DIS Value */ 561 #define MXC_S_SPI17Y_INT_EN_TX_UND_DIS (MXC_V_SPI17Y_INT_EN_TX_UND_DIS << MXC_F_SPI17Y_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_DIS Setting */ 562 #define MXC_V_SPI17Y_INT_EN_TX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_TX_UND_EN Value */ 563 #define MXC_S_SPI17Y_INT_EN_TX_UND_EN (MXC_V_SPI17Y_INT_EN_TX_UND_EN << MXC_F_SPI17Y_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_EN Setting */ 564 565 #define MXC_F_SPI17Y_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */ 566 #define MXC_F_SPI17Y_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */ 567 #define MXC_V_SPI17Y_INT_EN_RX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_OVR_DIS Value */ 568 #define MXC_S_SPI17Y_INT_EN_RX_OVR_DIS (MXC_V_SPI17Y_INT_EN_RX_OVR_DIS << MXC_F_SPI17Y_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_DIS Setting */ 569 #define MXC_V_SPI17Y_INT_EN_RX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_RX_OVR_EN Value */ 570 #define MXC_S_SPI17Y_INT_EN_RX_OVR_EN (MXC_V_SPI17Y_INT_EN_RX_OVR_EN << MXC_F_SPI17Y_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_EN Setting */ 571 572 #define MXC_F_SPI17Y_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */ 573 #define MXC_F_SPI17Y_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */ 574 #define MXC_V_SPI17Y_INT_EN_RX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_UND_DIS Value */ 575 #define MXC_S_SPI17Y_INT_EN_RX_UND_DIS (MXC_V_SPI17Y_INT_EN_RX_UND_DIS << MXC_F_SPI17Y_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_DIS Setting */ 576 #define MXC_V_SPI17Y_INT_EN_RX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_RX_UND_EN Value */ 577 #define MXC_S_SPI17Y_INT_EN_RX_UND_EN (MXC_V_SPI17Y_INT_EN_RX_UND_EN << MXC_F_SPI17Y_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_EN Setting */ 578 579 /**@} end of group SPI17Y_INT_EN_Register */ 580 581 /** 582 * @ingroup spi17y_registers 583 * @defgroup SPI17Y_WAKE_FL SPI17Y_WAKE_FL 584 * @brief Register for wake up flags. All bits in this register are write 1 to clear. 585 * @{ 586 */ 587 #define MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS 0 /**< WAKE_FL_TX_THRESH Position */ 588 #define MXC_F_SPI17Y_WAKE_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS)) /**< WAKE_FL_TX_THRESH Mask */ 589 #define MXC_V_SPI17Y_WAKE_FL_TX_THRESH_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_THRESH_CLEAR Value */ 590 #define MXC_S_SPI17Y_WAKE_FL_TX_THRESH_CLEAR (MXC_V_SPI17Y_WAKE_FL_TX_THRESH_CLEAR << MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS) /**< WAKE_FL_TX_THRESH_CLEAR Setting */ 591 592 #define MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */ 593 #define MXC_F_SPI17Y_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */ 594 #define MXC_V_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_EMPTY_CLEAR Value */ 595 #define MXC_S_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR (MXC_V_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR << MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS) /**< WAKE_FL_TX_EMPTY_CLEAR Setting */ 596 597 #define MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS 2 /**< WAKE_FL_RX_THRESH Position */ 598 #define MXC_F_SPI17Y_WAKE_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS)) /**< WAKE_FL_RX_THRESH Mask */ 599 #define MXC_V_SPI17Y_WAKE_FL_RX_THRESH_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_THRESH_CLEAR Value */ 600 #define MXC_S_SPI17Y_WAKE_FL_RX_THRESH_CLEAR (MXC_V_SPI17Y_WAKE_FL_RX_THRESH_CLEAR << MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS) /**< WAKE_FL_RX_THRESH_CLEAR Setting */ 601 602 #define MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */ 603 #define MXC_F_SPI17Y_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */ 604 #define MXC_V_SPI17Y_WAKE_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_FULL_CLEAR Value */ 605 #define MXC_S_SPI17Y_WAKE_FL_RX_FULL_CLEAR (MXC_V_SPI17Y_WAKE_FL_RX_FULL_CLEAR << MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS) /**< WAKE_FL_RX_FULL_CLEAR Setting */ 606 607 /**@} end of group SPI17Y_WAKE_FL_Register */ 608 609 /** 610 * @ingroup spi17y_registers 611 * @defgroup SPI17Y_WAKE_EN SPI17Y_WAKE_EN 612 * @brief Register for wake up enable. 613 * @{ 614 */ 615 #define MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS 0 /**< WAKE_EN_TX_THRESH Position */ 616 #define MXC_F_SPI17Y_WAKE_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS)) /**< WAKE_EN_TX_THRESH Mask */ 617 #define MXC_V_SPI17Y_WAKE_EN_TX_THRESH_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_THRESH_DIS Value */ 618 #define MXC_S_SPI17Y_WAKE_EN_TX_THRESH_DIS (MXC_V_SPI17Y_WAKE_EN_TX_THRESH_DIS << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS) /**< WAKE_EN_TX_THRESH_DIS Setting */ 619 #define MXC_V_SPI17Y_WAKE_EN_TX_THRESH_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_THRESH_EN Value */ 620 #define MXC_S_SPI17Y_WAKE_EN_TX_THRESH_EN (MXC_V_SPI17Y_WAKE_EN_TX_THRESH_EN << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS) /**< WAKE_EN_TX_THRESH_EN Setting */ 621 622 #define MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */ 623 #define MXC_F_SPI17Y_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */ 624 #define MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_EMPTY_DIS Value */ 625 #define MXC_S_SPI17Y_WAKE_EN_TX_EMPTY_DIS (MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_DIS << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_DIS Setting */ 626 #define MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_EMPTY_EN Value */ 627 #define MXC_S_SPI17Y_WAKE_EN_TX_EMPTY_EN (MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_EN << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_EN Setting */ 628 629 #define MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS 2 /**< WAKE_EN_RX_THRESH Position */ 630 #define MXC_F_SPI17Y_WAKE_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS)) /**< WAKE_EN_RX_THRESH Mask */ 631 #define MXC_V_SPI17Y_WAKE_EN_RX_THRESH_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_THRESH_DIS Value */ 632 #define MXC_S_SPI17Y_WAKE_EN_RX_THRESH_DIS (MXC_V_SPI17Y_WAKE_EN_RX_THRESH_DIS << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS) /**< WAKE_EN_RX_THRESH_DIS Setting */ 633 #define MXC_V_SPI17Y_WAKE_EN_RX_THRESH_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_THRESH_EN Value */ 634 #define MXC_S_SPI17Y_WAKE_EN_RX_THRESH_EN (MXC_V_SPI17Y_WAKE_EN_RX_THRESH_EN << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS) /**< WAKE_EN_RX_THRESH_EN Setting */ 635 636 #define MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */ 637 #define MXC_F_SPI17Y_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */ 638 #define MXC_V_SPI17Y_WAKE_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_FULL_DIS Value */ 639 #define MXC_S_SPI17Y_WAKE_EN_RX_FULL_DIS (MXC_V_SPI17Y_WAKE_EN_RX_FULL_DIS << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_DIS Setting */ 640 #define MXC_V_SPI17Y_WAKE_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_FULL_EN Value */ 641 #define MXC_S_SPI17Y_WAKE_EN_RX_FULL_EN (MXC_V_SPI17Y_WAKE_EN_RX_FULL_EN << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_EN Setting */ 642 643 /**@} end of group SPI17Y_WAKE_EN_Register */ 644 645 /** 646 * @ingroup spi17y_registers 647 * @defgroup SPI17Y_STAT SPI17Y_STAT 648 * @brief SPI Status register. 649 * @{ 650 */ 651 #define MXC_F_SPI17Y_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ 652 #define MXC_F_SPI17Y_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI17Y_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ 653 #define MXC_V_SPI17Y_STAT_BUSY_NOT ((uint32_t)0x0UL) /**< STAT_BUSY_NOT Value */ 654 #define MXC_S_SPI17Y_STAT_BUSY_NOT (MXC_V_SPI17Y_STAT_BUSY_NOT << MXC_F_SPI17Y_STAT_BUSY_POS) /**< STAT_BUSY_NOT Setting */ 655 #define MXC_V_SPI17Y_STAT_BUSY_ACTIVE ((uint32_t)0x1UL) /**< STAT_BUSY_ACTIVE Value */ 656 #define MXC_S_SPI17Y_STAT_BUSY_ACTIVE (MXC_V_SPI17Y_STAT_BUSY_ACTIVE << MXC_F_SPI17Y_STAT_BUSY_POS) /**< STAT_BUSY_ACTIVE Setting */ 657 658 /**@} end of group SPI17Y_STAT_Register */ 659 660 #ifdef __cplusplus 661 } 662 #endif 663 664 #endif /* _SPI17Y_REGS_H_ */ 665