1;/*---------------------------------------------------------------------------------------------------------*/ 2;/* Holtek Semiconductor Inc. */ 3;/* */ 4;/* Copyright (C) Holtek Semiconductor Inc. */ 5;/* All rights reserved. */ 6;/* */ 7;/*----------------------------------------------------------------------------------------------------------- 8; File Name : startup_ht32f5xxxx_03.s 9; Version : $Rev:: 7594 $ 10; Date : $Date:: 2024-02-23 #$ 11; Description : Startup code. 12;-----------------------------------------------------------------------------------------------------------*/ 13 14; Supported Device 15; ======================================== 16; HT32F0008 17; HT32F52142 18; HT32F52344, HT32F52354 19; HT32F52357, HT32F52367 20; HT50F3200T 21 22;/* <<< Use Configuration Wizard in Context Menu >>> */ 23 24;// <o> HT32 Device 25;// <i> Select HT32 Device for the assembly setting. 26;// <i> Notice that the project's Asm Define has the higher priority. 27;// <0=> By Project Asm Define 28;// <6=> HT32F0008 29;// <6=> HT32F52142 30;// <9=> HT32F52344/54 31;// <11=> HT32F52357/67 32;// <11=> HT50F3200T 33USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. 34 35_HT32FWID EQU 0xFFFFFFFF 36;_HT32FWID EQU 0x00000008 37;_HT32FWID EQU 0x00052142 38;_HT32FWID EQU 0x00052344 39;_HT32FWID EQU 0x00052354 40;_HT32FWID EQU 0x00052357 41;_HT32FWID EQU 0x00052367 42;_HT32FWID EQU 0x0003200F 43 44HT32F0008 EQU 6 45HT32F52142 EQU 6 46HT32F52344_54 EQU 9 47HT32F52357_67 EQU 11 48HT50F3200T EQU 11 49 50 IF USE_HT32_CHIP_SET=0 51 ; Use project's Asm Define setting (default) 52 ELSE 53 IF :DEF:USE_HT32_CHIP 54 ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") 55 ELSE 56 ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file 57USE_HT32_CHIP EQU USE_HT32_CHIP_SET 58 ENDIF 59 ENDIF 60 61; Amount of memory (in bytes) allocated for Stack and Heap 62; Tailor those values to your application needs 63 64;// <o> Stack Location 65;// <0=> After the RW/ZI/Heap (Default) 66;// <1=> On the top of the SRAM (The end of the SRAM) 67USE_STACK_ON_TOP EQU 0 68 69;// <o> Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> 70;// <i> Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). 71Stack_Size EQU 512 72 73 AREA STACK, NOINIT, READWRITE, ALIGN = 3 74__HT_check_sp 75Stack_Mem SPACE Stack_Size 76 IF (USE_STACK_ON_TOP = 1) 77__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE 78 ELSE 79__initial_sp 80 ENDIF 81 82;// <o> Heap Size (in Bytes) <0-16384:8> 83Heap_Size EQU 0 84 85 AREA HEAP, NOINIT, READWRITE, ALIGN = 3 86__HT_check_heap 87__heap_base 88Heap_Mem SPACE Heap_Size 89__heap_limit 90 91 PRESERVE8 92 THUMB 93 94;******************************************************************************* 95; Fill-up the Vector Table entries with the exceptions ISR address 96;******************************************************************************* 97 AREA RESET, CODE, READONLY 98 EXPORT __Vectors 99_RESERVED EQU 0xFFFFFFFF 100__Vectors 101 DCD __initial_sp ; ---, 00, 0x000, Top address of Stack 102 DCD Reset_Handler ; ---, 01, 0x004, Reset Handler 103 DCD NMI_Handler ; -14, 02, 0x008, NMI Handler 104 DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler 105 DCD _RESERVED ; ---, 04, 0x010, Reserved 106 DCD _RESERVED ; ---, 05, 0x014, Reserved 107 DCD _RESERVED ; ---, 06, 0x018, Reserved 108 DCD _RESERVED ; ---, 07, 0x01C, Reserved 109 DCD _HT32FWID ; ---, 08, 0x020, Reserved 110 DCD _RESERVED ; ---, 09, 0x024, Reserved 111 DCD _RESERVED ; ---, 10, 0x028, Reserved 112 DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler 113 DCD _RESERVED ; ---, 12, 0x030, Reserved 114 DCD _RESERVED ; ---, 13, 0x034, Reserved 115 DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler 116 DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler 117 118 ; External Interrupt Handler 119 DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, 120 DCD RTC_IRQHandler ; 01, 17, 0x044, 121 DCD FLASH_IRQHandler ; 02, 18, 0x048, 122 DCD EVWUP_IRQHandler ; 03, 19, 0x04C, 123 DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, 124 DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, 125 DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, 126 IF (USE_HT32_CHIP=HT32F0008) 127 DCD _RESERVED ; 07, 23, 0x05C, 128 ENDIF 129 IF (USE_HT32_CHIP=HT32F52344_54) 130 DCD COMP_IRQHandler ; 07, 23, 0x05C, 131 ENDIF 132 IF (USE_HT32_CHIP=HT32F52357_67) 133 DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, 134 ENDIF 135 IF (USE_HT32_CHIP=HT32F0008) 136 DCD _RESERVED ; 08, 24, 0x060, 137 ELSE 138 DCD ADC_IRQHandler ; 08, 24, 0x060, 139 ENDIF 140 IF (USE_HT32_CHIP=HT32F52357_67) 141 DCD AES_IRQHandler ; 09, 25, 0x064, 142 ELSE 143 DCD _RESERVED ; 09, 25, 0x064, 144 ENDIF 145 IF (USE_HT32_CHIP=HT32F0008) 146 DCD _RESERVED ; 10, 26, 0x068, 147 ELSE 148 DCD MCTM0_IRQHandler ; 10, 26, 0x068, 149 ENDIF 150 IF (USE_HT32_CHIP=HT32F52357_67) 151 DCD QSPI_IRQHandler ; 11, 27, 0x06C, 152 ELSE 153 DCD _RESERVED ; 11, 27, 0x06C, 154 ENDIF 155 DCD GPTM0_IRQHandler ; 12, 28, 0x070, 156 IF (USE_HT32_CHIP=HT32F0008) 157 DCD _RESERVED ; 13, 29, 0x074, 158 DCD _RESERVED ; 14, 30, 0x078, 159 ELSE 160 DCD SCTM0_IRQHandler ; 13, 29, 0x074, 161 DCD SCTM1_IRQHandler ; 14, 30, 0x078, 162 ENDIF 163 IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) 164 DCD PWM0_IRQHandler ; 15, 31, 0x07C, 165 DCD PWM1_IRQHandler ; 16, 32, 0x080, 166 ENDIF 167 IF (USE_HT32_CHIP=HT32F52344_54) 168 DCD _RESERVED ; 15, 31, 0x07C, 169 DCD _RESERVED ; 16, 32, 0x080, 170 ENDIF 171 DCD BFTM0_IRQHandler ; 17, 33, 0x084, 172 DCD BFTM1_IRQHandler ; 18, 34, 0x088, 173 DCD I2C0_IRQHandler ; 19, 35, 0x08C, 174 IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) 175 DCD _RESERVED ; 20, 36, 0x090, 176 ELSE 177 DCD I2C1_IRQHandler ; 20, 36, 0x090, 178 ENDIF 179 DCD SPI0_IRQHandler ; 21, 37, 0x094, 180 IF (USE_HT32_CHIP=HT32F0008) 181 DCD _RESERVED ; 22, 38, 0x098, 182 ELSE 183 DCD SPI1_IRQHandler ; 22, 38, 0x098, 184 ENDIF 185 IF (USE_HT32_CHIP=HT32F52344_54) 186 DCD _RESERVED ; 23, 39, 0x09C, 187 ELSE 188 DCD USART0_IRQHandler ; 23, 39, 0x09C, 189 ENDIF 190 IF (USE_HT32_CHIP=HT32F0008) 191 DCD _RESERVED ; 24, 40, 0x0A0, 192 DCD UART0_IRQHandler ; 25, 41, 0x0A4, 193 DCD _RESERVED ; 26, 42, 0x0A8, 194 ENDIF 195 IF (USE_HT32_CHIP=HT32F52344_54) 196 DCD _RESERVED ; 24, 40, 0x0A0, 197 DCD UART0_IRQHandler ; 25, 41, 0x0A4, 198 DCD UART1_IRQHandler ; 26, 42, 0x0A8, 199 ENDIF 200 IF (USE_HT32_CHIP=HT32F52357_67) 201 DCD USART1_IRQHandler ; 24, 40, 0x0A0, 202 DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, 203 DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, 204 ENDIF 205 IF (USE_HT32_CHIP=HT32F52357_67) 206 DCD SCI_IRQHandler ; 27, 43, 0xAC, 207 ELSE 208 DCD _RESERVED ; 27, 43, 0xAC, 209 ENDIF 210 IF (USE_HT32_CHIP=HT32F0008) 211 DCD AES_IRQHandler ; 28, 44, 0x0B0, 212 ENDIF 213 IF (USE_HT32_CHIP=HT32F52344_54) 214 DCD _RESERVED ; 28, 44, 0x0B0, 215 ENDIF 216 IF (USE_HT32_CHIP=HT32F52357_67) 217 DCD I2S_IRQHandler ; 28, 44, 0x0B0, 218 ENDIF 219 DCD USB_IRQHandler ; 29, 45, 0x0B4, 220 DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, 221 DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, 222 223; Reset handler routine 224Reset_Handler PROC 225 EXPORT Reset_Handler [WEAK] 226 IMPORT SystemInit 227 IMPORT __main 228 LDR R0, =BootProcess 229 BLX R0 230 LDR R0, =SystemInit 231 BLX R0 232 LDR R0, =__main 233 BX R0 234 ENDP 235 236BootProcess PROC 237 LDR R0, =0x40080300 238 LDR R1,[R0, #0x10] 239 CMP R1, #0 240 BNE BP1 241 LDR R1,[R0, #0x14] 242 CMP R1, #0 243 BNE BP1 244 LDR R1,[R0, #0x18] 245 CMP R1, #0 246 BNE BP1 247 LDR R1,[R0, #0x1C] 248 CMP R1, #0 249 BEQ BP2 250BP1 LDR R0, =0x40080180 251 LDR R1,[R0, #0xC] 252 LSLS R1, R1, #4 253 LSRS R1, R1, #20 254 CMP R1, #0 255 BEQ BP3 256 CMP R1, #5 257 BEQ BP3 258 CMP R1, #6 259 BEQ BP3 260BP2 DSB 261 LDR R0, =0x20000000 262 LDR R1, =0x05fa0004 263 STR R1, [R0] 264 LDR R1, =0xe000ed00 265 LDR R0, =0x05fa0004 266 STR R0, [R1, #0xC] 267 DSB 268 B . 269BP3 LDR R0, =0x20000000 270 LDR R1, [R0] 271 LDR R0, =0x05fa0004 272 CMP R0, R1 273 BEQ BP4 274 BX LR 275BP4 LDR R0, =0x40088100 276 LDR R1, =0x00000001 277 STR R1, [R0] 278 LDR R0, =0x20000000 279 LDR R1, =0x0 280 STR R1, [R0] 281 BX LR 282 ENDP 283 284; Dummy Exception Handlers 285NMI_Handler PROC 286 EXPORT NMI_Handler [WEAK] 287 B . 288 ENDP 289 290HardFault_Handler PROC 291 EXPORT HardFault_Handler [WEAK] 292 B . 293 ENDP 294 295SVC_Handler PROC 296 EXPORT SVC_Handler [WEAK] 297 B . 298 ENDP 299 300PendSV_Handler PROC 301 EXPORT PendSV_Handler [WEAK] 302 B . 303 ENDP 304 305SysTick_Handler PROC 306 EXPORT SysTick_Handler [WEAK] 307 B . 308 ENDP 309 310Default_Handler PROC 311 EXPORT LVD_BOD_IRQHandler [WEAK] 312 EXPORT RTC_IRQHandler [WEAK] 313 EXPORT FLASH_IRQHandler [WEAK] 314 EXPORT EVWUP_IRQHandler [WEAK] 315 EXPORT EXTI0_1_IRQHandler [WEAK] 316 EXPORT EXTI2_3_IRQHandler [WEAK] 317 EXPORT EXTI4_15_IRQHandler [WEAK] 318 EXPORT COMP_IRQHandler [WEAK] 319 EXPORT COMP_DAC_IRQHandler [WEAK] 320 EXPORT ADC_IRQHandler [WEAK] 321 EXPORT MCTM0_IRQHandler [WEAK] 322 EXPORT GPTM0_IRQHandler [WEAK] 323 EXPORT SCTM0_IRQHandler [WEAK] 324 EXPORT SCTM1_IRQHandler [WEAK] 325 EXPORT PWM0_IRQHandler [WEAK] 326 EXPORT PWM1_IRQHandler [WEAK] 327 EXPORT BFTM0_IRQHandler [WEAK] 328 EXPORT BFTM1_IRQHandler [WEAK] 329 EXPORT I2C0_IRQHandler [WEAK] 330 EXPORT I2C1_IRQHandler [WEAK] 331 EXPORT SPI0_IRQHandler [WEAK] 332 EXPORT SPI1_IRQHandler [WEAK] 333 EXPORT QSPI_IRQHandler [WEAK] 334 EXPORT USART0_IRQHandler [WEAK] 335 EXPORT USART1_IRQHandler [WEAK] 336 EXPORT UART0_IRQHandler [WEAK] 337 EXPORT UART1_IRQHandler [WEAK] 338 EXPORT UART0_UART2_IRQHandler [WEAK] 339 EXPORT UART1_UART3_IRQHandler [WEAK] 340 EXPORT SCI_IRQHandler [WEAK] 341 EXPORT I2S_IRQHandler [WEAK] 342 EXPORT AES_IRQHandler [WEAK] 343 EXPORT USB_IRQHandler [WEAK] 344 EXPORT PDMA_CH0_1_IRQHandler [WEAK] 345 EXPORT PDMA_CH2_5_IRQHandler [WEAK] 346 347LVD_BOD_IRQHandler 348RTC_IRQHandler 349FLASH_IRQHandler 350EVWUP_IRQHandler 351EXTI0_1_IRQHandler 352EXTI2_3_IRQHandler 353EXTI4_15_IRQHandler 354COMP_IRQHandler 355COMP_DAC_IRQHandler 356ADC_IRQHandler 357MCTM0_IRQHandler 358GPTM0_IRQHandler 359SCTM0_IRQHandler 360SCTM1_IRQHandler 361PWM0_IRQHandler 362PWM1_IRQHandler 363BFTM0_IRQHandler 364BFTM1_IRQHandler 365I2C0_IRQHandler 366I2C1_IRQHandler 367SPI0_IRQHandler 368SPI1_IRQHandler 369QSPI_IRQHandler 370USART0_IRQHandler 371USART1_IRQHandler 372UART0_IRQHandler 373UART1_IRQHandler 374UART0_UART2_IRQHandler 375UART1_UART3_IRQHandler 376SCI_IRQHandler 377I2S_IRQHandler 378AES_IRQHandler 379USB_IRQHandler 380PDMA_CH0_1_IRQHandler 381PDMA_CH2_5_IRQHandler 382 B . 383 ENDP 384 385 ALIGN 386 387;******************************************************************************* 388; User Stack and Heap initialization 389;******************************************************************************* 390 EXPORT __HT_check_heap 391 EXPORT __HT_check_sp 392 393 IF :DEF:__MICROLIB 394 395 EXPORT __initial_sp 396 EXPORT __heap_base 397 EXPORT __heap_limit 398 399 ELSE 400 401 IMPORT __use_two_region_memory 402 EXPORT __user_initial_stackheap 403__user_initial_stackheap 404 405 IF (USE_STACK_ON_TOP = 1) 406 LDR R0, = Heap_Mem 407 LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) 408 LDR R2, = (Heap_Mem + Heap_Size) 409 LDR R3, = (Heap_Mem + Heap_Size) 410 BX LR 411 ELSE 412 LDR R0, = Heap_Mem 413 LDR R1, = (Stack_Mem + Stack_Size) 414 LDR R2, = (Heap_Mem + Heap_Size) 415 LDR R3, = Stack_Mem 416 BX LR 417 ENDIF 418 419 ALIGN 420 421 ENDIF 422 423 END 424