1;/***************************************************************************** 2; * @file startup_SAME54.s 3; * @brief CMSIS Cortex-M4 Core Device Startup File for 4; * Atmel SAME54 Device Series 5; * @version V1.0.0 6; * @date 16. January 2017 7; * 8; * @note 9; * Copyright (C) 2017 ARM Limited. All rights reserved. 10; * 11; * @par 12; * ARM Limited (ARM) is supplying this software for use with Cortex-M 13; * processor based microcontrollers. This file can be freely distributed 14; * within development tools that are supporting such ARM based processors. 15; * 16; * @par 17; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 18; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 19; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 20; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 21; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 22; * 23; ******************************************************************************/ 24;/* 25;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 26;*/ 27 28 29; <h> Stack Configuration 30; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 31; </h> 32 33Stack_Size EQU 0x00000200 34 35 AREA STACK, NOINIT, READWRITE, ALIGN=3 36Stack_Mem SPACE Stack_Size 37__initial_sp 38 39 40; <h> Heap Configuration 41; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 42; </h> 43 44Heap_Size EQU 0x00000000 45 46 AREA HEAP, NOINIT, READWRITE, ALIGN=3 47__heap_base 48Heap_Mem SPACE Heap_Size 49__heap_limit 50 51 52 PRESERVE8 53 THUMB 54 55 56; Vector Table Mapped to Address 0 at Reset 57 58 AREA RESET, DATA, READONLY 59 EXPORT __Vectors 60 EXPORT __Vectors_End 61 EXPORT __Vectors_Size 62 63__Vectors DCD __initial_sp ; Top of Stack 64 DCD Reset_Handler ; Reset Handler 65 DCD NMI_Handler ; NMI Handler 66 DCD HardFault_Handler ; Hard Fault Handler 67 DCD MemManage_Handler ; MPU Fault Handler 68 DCD BusFault_Handler ; Bus Fault Handler 69 DCD UsageFault_Handler ; Usage Fault Handler 70 DCD 0 ; Reserved 71 DCD 0 ; Reserved 72 DCD 0 ; Reserved 73 DCD 0 ; Reserved 74 DCD SVC_Handler ; SVCall Handler 75 DCD DebugMon_Handler ; Debug Monitor Handler 76 DCD 0 ; Reserved 77 DCD PendSV_Handler ; PendSV Handler 78 DCD SysTick_Handler ; SysTick Handler 79 80 ; External Interrupts 81 DCD PM_Handler ; 0 Power Manager 82 DCD MCLK_Handler ; 1 Main Clock 83 DCD OSCCTRL_0_Handler ; 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 84 DCD OSCCTRL_1_Handler ; 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 85 DCD OSCCTRL_2_Handler ; 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY 86 DCD OSCCTRL_3_Handler ; 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 87 DCD OSCCTRL_4_Handler ; 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 88 DCD OSC32KCTRL_Handler ; 7 32kHz Oscillators Control 89 DCD SUPC_0_Handler ; 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY 90 DCD SUPC_1_Handler ; 9 SUPC_BOD12DET, SUPC_BOD33DET 91 DCD WDT_Handler ; 10 Watchdog Timer 92 DCD RTC_Handler ; 11 Real-Time Counter 93 DCD EIC_0_Handler ; 12 EIC_EXTINT_0 94 DCD EIC_1_Handler ; 13 EIC_EXTINT_1 95 DCD EIC_2_Handler ; 14 EIC_EXTINT_2 96 DCD EIC_3_Handler ; 15 EIC_EXTINT_3 97 DCD EIC_4_Handler ; 16 EIC_EXTINT_4 98 DCD EIC_5_Handler ; 17 EIC_EXTINT_5 99 DCD EIC_6_Handler ; 18 EIC_EXTINT_6 100 DCD EIC_7_Handler ; 19 EIC_EXTINT_7 101 DCD EIC_8_Handler ; 20 EIC_EXTINT_8 102 DCD EIC_9_Handler ; 21 EIC_EXTINT_9 103 DCD EIC_10_Handler ; 22 EIC_EXTINT_10 104 DCD EIC_11_Handler ; 23 EIC_EXTINT_11 105 DCD EIC_12_Handler ; 24 EIC_EXTINT_12 106 DCD EIC_13_Handler ; 25 EIC_EXTINT_13 107 DCD EIC_14_Handler ; 26 EIC_EXTINT_14 108 DCD EIC_15_Handler ; 27 EIC_EXTINT_15 109 DCD FREQM_Handler ; 28 Frequency Meter 110 DCD NVMCTRL_0_Handler ; 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 111 DCD NVMCTRL_1_Handler ; 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 112 DCD DMAC_0_Handler ; 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 113 DCD DMAC_1_Handler ; 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 114 DCD DMAC_2_Handler ; 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 115 DCD DMAC_3_Handler ; 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 116 DCD DMAC_4_Handler ; 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 117 DCD EVSYS_0_Handler ; 36 EVSYS_EVD_0, EVSYS_OVR_0 118 DCD EVSYS_1_Handler ; 37 EVSYS_EVD_1, EVSYS_OVR_1 119 DCD EVSYS_2_Handler ; 38 EVSYS_EVD_2, EVSYS_OVR_2 120 DCD EVSYS_3_Handler ; 39 EVSYS_EVD_3, EVSYS_OVR_3 121 DCD EVSYS_4_Handler ; 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 122 DCD PAC_Handler ; 41 Peripheral Access Controller 123 DCD TAL_0_Handler ; 42 TAL_BRK 124 DCD TAL_1_Handler ; 43 TAL_IPS_0, TAL_IPS_1 125 DCD 0 ; 44 Reserved 126 DCD RAMECC_Handler ; 45 RAM ECC 127 DCD SERCOM0_0_Handler ; 46 SERCOM0_0 128 DCD SERCOM0_1_Handler ; 47 SERCOM0_1 129 DCD SERCOM0_2_Handler ; 48 SERCOM0_2 130 DCD SERCOM0_3_Handler ; 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 131 DCD SERCOM1_0_Handler ; 50 SERCOM1_0 132 DCD SERCOM1_1_Handler ; 51 SERCOM1_1 133 DCD SERCOM1_2_Handler ; 52 SERCOM1_2 134 DCD SERCOM1_3_Handler ; 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 135 DCD SERCOM2_0_Handler ; 54 SERCOM2_0 136 DCD SERCOM2_1_Handler ; 55 SERCOM2_1 137 DCD SERCOM2_2_Handler ; 56 SERCOM2_2 138 DCD SERCOM2_3_Handler ; 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 139 DCD SERCOM3_0_Handler ; 58 SERCOM3_0 140 DCD SERCOM3_1_Handler ; 59 SERCOM3_1 141 DCD SERCOM3_2_Handler ; 60 SERCOM3_2 142 DCD SERCOM3_3_Handler ; 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 143 DCD SERCOM4_0_Handler ; 62 SERCOM4_0 144 DCD SERCOM4_1_Handler ; 63 SERCOM4_1 145 DCD SERCOM4_2_Handler ; 64 SERCOM4_2 146 DCD SERCOM4_3_Handler ; 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 147 DCD SERCOM5_0_Handler ; 66 SERCOM5_0 148 DCD SERCOM5_1_Handler ; 67 SERCOM5_1 149 DCD SERCOM5_2_Handler ; 68 SERCOM5_2 150 DCD SERCOM5_3_Handler ; 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 151 DCD SERCOM6_0_Handler ; 70 SERCOM6_0 152 DCD SERCOM6_1_Handler ; 71 SERCOM6_1 153 DCD SERCOM6_2_Handler ; 72 SERCOM6_2 154 DCD SERCOM6_3_Handler ; 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 155 DCD SERCOM7_0_Handler ; 74 SERCOM7_0 156 DCD SERCOM7_1_Handler ; 75 SERCOM7_1 157 DCD SERCOM7_2_Handler ; 76 SERCOM7_2 158 DCD SERCOM7_3_Handler ; 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 159 DCD CAN0_Handler ; 78 Control Area Network 0 160 DCD CAN1_Handler ; 79 Control Area Network 1 161 DCD USB_0_Handler ; 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP 162 DCD USB_1_Handler ; 81 USB_SOF_HSOF 163 DCD USB_2_Handler ; 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 164 DCD USB_3_Handler ; 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 165 DCD GMAC_Handler ; 84 Ethernet MAC 166 DCD TCC0_0_Handler ; 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A 167 DCD TCC0_1_Handler ; 86 TCC0_MC_0 168 DCD TCC0_2_Handler ; 87 TCC0_MC_1 169 DCD TCC0_3_Handler ; 88 TCC0_MC_2 170 DCD TCC0_4_Handler ; 89 TCC0_MC_3 171 DCD TCC0_5_Handler ; 90 TCC0_MC_4 172 DCD TCC0_6_Handler ; 91 TCC0_MC_5 173 DCD TCC1_0_Handler ; 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A 174 DCD TCC1_1_Handler ; 93 TCC1_MC_0 175 DCD TCC1_2_Handler ; 94 TCC1_MC_1 176 DCD TCC1_3_Handler ; 95 TCC1_MC_2 177 DCD TCC1_4_Handler ; 96 TCC1_MC_3 178 DCD TCC2_0_Handler ; 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A 179 DCD TCC2_1_Handler ; 98 TCC2_MC_0 180 DCD TCC2_2_Handler ; 99 TCC2_MC_1 181 DCD TCC2_3_Handler ; 100 TCC2_MC_2 182 DCD TCC3_0_Handler ; 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A 183 DCD TCC3_1_Handler ; 102 TCC3_MC_0 184 DCD TCC3_2_Handler ; 103 TCC3_MC_1 185 DCD TCC4_0_Handler ; 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A 186 DCD TCC4_1_Handler ; 105 TCC4_MC_0 187 DCD TCC4_2_Handler ; 106 TCC4_MC_1 188 DCD TC0_Handler ; 107 Basic Timer Counter 0 189 DCD TC1_Handler ; 108 Basic Timer Counter 1 190 DCD TC2_Handler ; 109 Basic Timer Counter 2 191 DCD TC3_Handler ; 110 Basic Timer Counter 3 192 DCD TC4_Handler ; 111 Basic Timer Counter 4 193 DCD TC5_Handler ; 112 Basic Timer Counter 5 194 DCD TC6_Handler ; 113 Basic Timer Counter 6 195 DCD TC7_Handler ; 114 Basic Timer Counter 7 196 DCD PDEC_0_Handler ; 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A 197 DCD PDEC_1_Handler ; 116 PDEC_MC_0 198 DCD PDEC_2_Handler ; 117 PDEC_MC_1 199 DCD ADC0_0_Handler ; 118 ADC0_OVERRUN, ADC0_WINMON 200 DCD ADC0_1_Handler ; 119 ADC0_RESRDY 201 DCD ADC1_0_Handler ; 120 ADC1_OVERRUN, ADC1_WINMON 202 DCD ADC1_1_Handler ; 121 ADC1_RESRDY 203 DCD AC_Handler ; 122 Analog Comparators 204 DCD DAC_0_Handler ; 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 205 DCD DAC_1_Handler ; 124 DAC_EMPTY_0 206 DCD DAC_2_Handler ; 125 DAC_EMPTY_1 207 DCD DAC_3_Handler ; 126 DAC_RESRDY_0 208 DCD DAC_4_Handler ; 127 DAC_RESRDY_1 209 DCD I2S_Handler ; 128 Inter-IC Sound Interface 210 DCD PCC_Handler ; 129 Parallel Capture Controller 211 DCD AES_Handler ; 130 Advanced Encryption Standard 212 DCD TRNG_Handler ; 131 True Random Generator 213 DCD ICM_Handler ; 132 Integrity Check Monitor 214 DCD PUKCC_Handler ; 133 PUblic-Key Cryptography Controller 215 DCD QSPI_Handler ; 134 Quad SPI interface 216 DCD SDHC0_Handler ; 135 SD/MMC Host Controller 0 217 DCD SDHC1_Handler ; 136 SD/MMC Host Controller 1 218__Vectors_End 219 220__Vectors_Size EQU __Vectors_End - __Vectors 221 222 AREA |.text|, CODE, READONLY 223 224 225; Reset Handler 226 227Reset_Handler PROC 228 EXPORT Reset_Handler [WEAK] 229 IMPORT SystemInit 230 IMPORT __main 231 LDR R0, =SystemInit 232 BLX R0 233 LDR R0, =__main 234 BX R0 235 ENDP 236 237 238; Dummy Exception Handlers (infinite loops which can be modified) 239 240NMI_Handler PROC 241 EXPORT NMI_Handler [WEAK] 242 B . 243 ENDP 244HardFault_Handler\ 245 PROC 246 EXPORT HardFault_Handler [WEAK] 247 B . 248 ENDP 249MemManage_Handler\ 250 PROC 251 EXPORT MemManage_Handler [WEAK] 252 B . 253 ENDP 254BusFault_Handler\ 255 PROC 256 EXPORT BusFault_Handler [WEAK] 257 B . 258 ENDP 259UsageFault_Handler\ 260 PROC 261 EXPORT UsageFault_Handler [WEAK] 262 B . 263 ENDP 264SVC_Handler PROC 265 EXPORT SVC_Handler [WEAK] 266 B . 267 ENDP 268DebugMon_Handler\ 269 PROC 270 EXPORT DebugMon_Handler [WEAK] 271 B . 272 ENDP 273PendSV_Handler PROC 274 EXPORT PendSV_Handler [WEAK] 275 B . 276 ENDP 277SysTick_Handler PROC 278 EXPORT SysTick_Handler [WEAK] 279 B . 280 ENDP 281 282Default_Handler PROC 283 EXPORT PM_Handler [WEAK] 284 EXPORT MCLK_Handler [WEAK] 285 EXPORT OSCCTRL_0_Handler [WEAK] 286 EXPORT OSCCTRL_1_Handler [WEAK] 287 EXPORT OSCCTRL_2_Handler [WEAK] 288 EXPORT OSCCTRL_3_Handler [WEAK] 289 EXPORT OSCCTRL_4_Handler [WEAK] 290 EXPORT OSC32KCTRL_Handler [WEAK] 291 EXPORT SUPC_0_Handler [WEAK] 292 EXPORT SUPC_1_Handler [WEAK] 293 EXPORT WDT_Handler [WEAK] 294 EXPORT RTC_Handler [WEAK] 295 EXPORT EIC_0_Handler [WEAK] 296 EXPORT EIC_1_Handler [WEAK] 297 EXPORT EIC_2_Handler [WEAK] 298 EXPORT EIC_3_Handler [WEAK] 299 EXPORT EIC_4_Handler [WEAK] 300 EXPORT EIC_5_Handler [WEAK] 301 EXPORT EIC_6_Handler [WEAK] 302 EXPORT EIC_7_Handler [WEAK] 303 EXPORT EIC_8_Handler [WEAK] 304 EXPORT EIC_9_Handler [WEAK] 305 EXPORT EIC_10_Handler [WEAK] 306 EXPORT EIC_11_Handler [WEAK] 307 EXPORT EIC_12_Handler [WEAK] 308 EXPORT EIC_13_Handler [WEAK] 309 EXPORT EIC_14_Handler [WEAK] 310 EXPORT EIC_15_Handler [WEAK] 311 EXPORT FREQM_Handler [WEAK] 312 EXPORT NVMCTRL_0_Handler [WEAK] 313 EXPORT NVMCTRL_1_Handler [WEAK] 314 EXPORT DMAC_0_Handler [WEAK] 315 EXPORT DMAC_1_Handler [WEAK] 316 EXPORT DMAC_2_Handler [WEAK] 317 EXPORT DMAC_3_Handler [WEAK] 318 EXPORT DMAC_4_Handler [WEAK] 319 EXPORT EVSYS_0_Handler [WEAK] 320 EXPORT EVSYS_1_Handler [WEAK] 321 EXPORT EVSYS_2_Handler [WEAK] 322 EXPORT EVSYS_3_Handler [WEAK] 323 EXPORT EVSYS_4_Handler [WEAK] 324 EXPORT PAC_Handler [WEAK] 325 EXPORT TAL_0_Handler [WEAK] 326 EXPORT TAL_1_Handler [WEAK] 327 EXPORT RAMECC_Handler [WEAK] 328 EXPORT SERCOM0_0_Handler [WEAK] 329 EXPORT SERCOM0_1_Handler [WEAK] 330 EXPORT SERCOM0_2_Handler [WEAK] 331 EXPORT SERCOM0_3_Handler [WEAK] 332 EXPORT SERCOM1_0_Handler [WEAK] 333 EXPORT SERCOM1_1_Handler [WEAK] 334 EXPORT SERCOM1_2_Handler [WEAK] 335 EXPORT SERCOM1_3_Handler [WEAK] 336 EXPORT SERCOM2_0_Handler [WEAK] 337 EXPORT SERCOM2_1_Handler [WEAK] 338 EXPORT SERCOM2_2_Handler [WEAK] 339 EXPORT SERCOM2_3_Handler [WEAK] 340 EXPORT SERCOM3_0_Handler [WEAK] 341 EXPORT SERCOM3_1_Handler [WEAK] 342 EXPORT SERCOM3_2_Handler [WEAK] 343 EXPORT SERCOM3_3_Handler [WEAK] 344 EXPORT SERCOM4_0_Handler [WEAK] 345 EXPORT SERCOM4_1_Handler [WEAK] 346 EXPORT SERCOM4_2_Handler [WEAK] 347 EXPORT SERCOM4_3_Handler [WEAK] 348 EXPORT SERCOM5_0_Handler [WEAK] 349 EXPORT SERCOM5_1_Handler [WEAK] 350 EXPORT SERCOM5_2_Handler [WEAK] 351 EXPORT SERCOM5_3_Handler [WEAK] 352 EXPORT SERCOM6_0_Handler [WEAK] 353 EXPORT SERCOM6_1_Handler [WEAK] 354 EXPORT SERCOM6_2_Handler [WEAK] 355 EXPORT SERCOM6_3_Handler [WEAK] 356 EXPORT SERCOM7_0_Handler [WEAK] 357 EXPORT SERCOM7_1_Handler [WEAK] 358 EXPORT SERCOM7_2_Handler [WEAK] 359 EXPORT SERCOM7_3_Handler [WEAK] 360 EXPORT CAN0_Handler [WEAK] 361 EXPORT CAN1_Handler [WEAK] 362 EXPORT USB_0_Handler [WEAK] 363 EXPORT USB_1_Handler [WEAK] 364 EXPORT USB_2_Handler [WEAK] 365 EXPORT USB_3_Handler [WEAK] 366 EXPORT GMAC_Handler [WEAK] 367 EXPORT TCC0_0_Handler [WEAK] 368 EXPORT TCC0_1_Handler [WEAK] 369 EXPORT TCC0_2_Handler [WEAK] 370 EXPORT TCC0_3_Handler [WEAK] 371 EXPORT TCC0_4_Handler [WEAK] 372 EXPORT TCC0_5_Handler [WEAK] 373 EXPORT TCC0_6_Handler [WEAK] 374 EXPORT TCC1_0_Handler [WEAK] 375 EXPORT TCC1_1_Handler [WEAK] 376 EXPORT TCC1_2_Handler [WEAK] 377 EXPORT TCC1_3_Handler [WEAK] 378 EXPORT TCC1_4_Handler [WEAK] 379 EXPORT TCC2_0_Handler [WEAK] 380 EXPORT TCC2_1_Handler [WEAK] 381 EXPORT TCC2_2_Handler [WEAK] 382 EXPORT TCC2_3_Handler [WEAK] 383 EXPORT TCC3_0_Handler [WEAK] 384 EXPORT TCC3_1_Handler [WEAK] 385 EXPORT TCC3_2_Handler [WEAK] 386 EXPORT TCC4_0_Handler [WEAK] 387 EXPORT TCC4_1_Handler [WEAK] 388 EXPORT TCC4_2_Handler [WEAK] 389 EXPORT TC0_Handler [WEAK] 390 EXPORT TC1_Handler [WEAK] 391 EXPORT TC2_Handler [WEAK] 392 EXPORT TC3_Handler [WEAK] 393 EXPORT TC4_Handler [WEAK] 394 EXPORT TC5_Handler [WEAK] 395 EXPORT TC6_Handler [WEAK] 396 EXPORT TC7_Handler [WEAK] 397 EXPORT PDEC_0_Handler [WEAK] 398 EXPORT PDEC_1_Handler [WEAK] 399 EXPORT PDEC_2_Handler [WEAK] 400 EXPORT ADC0_0_Handler [WEAK] 401 EXPORT ADC0_1_Handler [WEAK] 402 EXPORT ADC1_0_Handler [WEAK] 403 EXPORT ADC1_1_Handler [WEAK] 404 EXPORT AC_Handler [WEAK] 405 EXPORT DAC_0_Handler [WEAK] 406 EXPORT DAC_1_Handler [WEAK] 407 EXPORT DAC_2_Handler [WEAK] 408 EXPORT DAC_3_Handler [WEAK] 409 EXPORT DAC_4_Handler [WEAK] 410 EXPORT I2S_Handler [WEAK] 411 EXPORT PCC_Handler [WEAK] 412 EXPORT AES_Handler [WEAK] 413 EXPORT TRNG_Handler [WEAK] 414 EXPORT ICM_Handler [WEAK] 415 EXPORT PUKCC_Handler [WEAK] 416 EXPORT QSPI_Handler [WEAK] 417 EXPORT SDHC0_Handler [WEAK] 418 EXPORT SDHC1_Handler [WEAK] 419 420PM_Handler 421MCLK_Handler 422OSCCTRL_0_Handler 423OSCCTRL_1_Handler 424OSCCTRL_2_Handler 425OSCCTRL_3_Handler 426OSCCTRL_4_Handler 427OSC32KCTRL_Handler 428SUPC_0_Handler 429SUPC_1_Handler 430WDT_Handler 431RTC_Handler 432EIC_0_Handler 433EIC_1_Handler 434EIC_2_Handler 435EIC_3_Handler 436EIC_4_Handler 437EIC_5_Handler 438EIC_6_Handler 439EIC_7_Handler 440EIC_8_Handler 441EIC_9_Handler 442EIC_10_Handler 443EIC_11_Handler 444EIC_12_Handler 445EIC_13_Handler 446EIC_14_Handler 447EIC_15_Handler 448FREQM_Handler 449NVMCTRL_0_Handler 450NVMCTRL_1_Handler 451DMAC_0_Handler 452DMAC_1_Handler 453DMAC_2_Handler 454DMAC_3_Handler 455DMAC_4_Handler 456EVSYS_0_Handler 457EVSYS_1_Handler 458EVSYS_2_Handler 459EVSYS_3_Handler 460EVSYS_4_Handler 461PAC_Handler 462TAL_0_Handler 463TAL_1_Handler 464RAMECC_Handler 465SERCOM0_0_Handler 466SERCOM0_1_Handler 467SERCOM0_2_Handler 468SERCOM0_3_Handler 469SERCOM1_0_Handler 470SERCOM1_1_Handler 471SERCOM1_2_Handler 472SERCOM1_3_Handler 473SERCOM2_0_Handler 474SERCOM2_1_Handler 475SERCOM2_2_Handler 476SERCOM2_3_Handler 477SERCOM3_0_Handler 478SERCOM3_1_Handler 479SERCOM3_2_Handler 480SERCOM3_3_Handler 481SERCOM4_0_Handler 482SERCOM4_1_Handler 483SERCOM4_2_Handler 484SERCOM4_3_Handler 485SERCOM5_0_Handler 486SERCOM5_1_Handler 487SERCOM5_2_Handler 488SERCOM5_3_Handler 489SERCOM6_0_Handler 490SERCOM6_1_Handler 491SERCOM6_2_Handler 492SERCOM6_3_Handler 493SERCOM7_0_Handler 494SERCOM7_1_Handler 495SERCOM7_2_Handler 496SERCOM7_3_Handler 497CAN0_Handler 498CAN1_Handler 499USB_0_Handler 500USB_1_Handler 501USB_2_Handler 502USB_3_Handler 503GMAC_Handler 504TCC0_0_Handler 505TCC0_1_Handler 506TCC0_2_Handler 507TCC0_3_Handler 508TCC0_4_Handler 509TCC0_5_Handler 510TCC0_6_Handler 511TCC1_0_Handler 512TCC1_1_Handler 513TCC1_2_Handler 514TCC1_3_Handler 515TCC1_4_Handler 516TCC2_0_Handler 517TCC2_1_Handler 518TCC2_2_Handler 519TCC2_3_Handler 520TCC3_0_Handler 521TCC3_1_Handler 522TCC3_2_Handler 523TCC4_0_Handler 524TCC4_1_Handler 525TCC4_2_Handler 526TC0_Handler 527TC1_Handler 528TC2_Handler 529TC3_Handler 530TC4_Handler 531TC5_Handler 532TC6_Handler 533TC7_Handler 534PDEC_0_Handler 535PDEC_1_Handler 536PDEC_2_Handler 537ADC0_0_Handler 538ADC0_1_Handler 539ADC1_0_Handler 540ADC1_1_Handler 541AC_Handler 542DAC_0_Handler 543DAC_1_Handler 544DAC_2_Handler 545DAC_3_Handler 546DAC_4_Handler 547I2S_Handler 548PCC_Handler 549AES_Handler 550TRNG_Handler 551ICM_Handler 552PUKCC_Handler 553QSPI_Handler 554SDHC0_Handler 555SDHC1_Handler 556 B . 557 ENDP 558 559 560 ALIGN 561 562 563; User Initial Stack & Heap 564 565 IF :DEF:__MICROLIB 566 567 EXPORT __initial_sp 568 EXPORT __heap_base 569 EXPORT __heap_limit 570 571 ELSE 572 573 IMPORT __use_two_region_memory 574 EXPORT __user_initial_stackheap 575__user_initial_stackheap 576 577 LDR R0, = Heap_Mem 578 LDR R1, =(Stack_Mem + Stack_Size) 579 LDR R2, = (Heap_Mem + Heap_Size) 580 LDR R3, = Stack_Mem 581 BX LR 582 583 ALIGN 584 585 ENDIF 586 587 588 END 589