1 /**
2 ******************************************************************************
3 * @file bl602_aon.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl602_aon.h"
38
39 /** @addtogroup BL602_Peripheral_Driver
40 * @{
41 */
42
43 /** @addtogroup AON
44 * @{
45 */
46
47 /** @defgroup AON_Private_Macros
48 * @{
49 */
50 #define AON_CLK_SET_DUMMY_WAIT \
51 { \
52 __NOP(); \
53 __NOP(); \
54 __NOP(); \
55 __NOP(); \
56 __NOP(); \
57 __NOP(); \
58 __NOP(); \
59 __NOP(); \
60 }
61
62 /*@} end of group AON_Private_Macros */
63
64 /** @defgroup AON_Private_Types
65 * @{
66 */
67
68 /*@} end of group AON_Private_Types */
69
70 /** @defgroup AON_Private_Variables
71 * @{
72 */
73
74 /*@} end of group AON_Private_Variables */
75
76 /** @defgroup AON_Global_Variables
77 * @{
78 */
79
80 /*@} end of group AON_Global_Variables */
81
82 /** @defgroup AON_Private_Fun_Declaration
83 * @{
84 */
85
86 /*@} end of group AON_Private_Fun_Declaration */
87
88 /** @defgroup AON_Private_Functions
89 * @{
90 */
91
92 /*@} end of group AON_Private_Functions */
93
94 /** @defgroup AON_Public_Functions
95 * @{
96 */
97
98 /****************************************************************************/ /**
99 * @brief Power on MXX band gap
100 *
101 * @param None
102 *
103 * @return SUCCESS or ERROR
104 *
105 *******************************************************************************/
106 #ifndef BFLB_USE_ROM_DRIVER
107 __WEAK
AON_Power_On_MBG(void)108 BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
109 {
110 uint32_t tmpVal = 0;
111
112 /* Power up RF for PLL to work */
113 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
114 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
115 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
116
117 BL602_Delay_US(55);
118
119 return SUCCESS;
120 }
121 #endif
122
123 /****************************************************************************/ /**
124 * @brief Power off MXX band gap
125 *
126 * @param None
127 *
128 * @return SUCCESS or ERROR
129 *
130 *******************************************************************************/
131 #ifndef BFLB_USE_ROM_DRIVER
132 __WEAK
AON_Power_Off_MBG(void)133 BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
134 {
135 uint32_t tmpVal = 0;
136
137 /* Power OFF */
138 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
139 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
140 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
141
142 return SUCCESS;
143 }
144 #endif
145
146 /****************************************************************************/ /**
147 * @brief Power on XTAL
148 *
149 * @param None
150 *
151 * @return SUCCESS or ERROR
152 *
153 *******************************************************************************/
154 #ifndef BFLB_USE_ROM_DRIVER
155 __WEAK
AON_Power_On_XTAL(void)156 BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
157 {
158 uint32_t tmpVal = 0;
159 uint32_t timeOut = 0;
160
161 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
162 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON);
163 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
164 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
165
166 /* Polling for ready */
167 do {
168 BL602_Delay_US(10);
169 timeOut++;
170 tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
171 } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120);
172
173 if (timeOut >= 120) {
174 return TIMEOUT;
175 }
176
177 return SUCCESS;
178 }
179 #endif
180
181 /****************************************************************************/ /**
182 * @brief Set XTAL cap code
183 *
184 * @param capIn: Cap code in
185 * @param capOut: Cap code out
186 *
187 * @return SUCCESS or ERROR
188 *
189 *******************************************************************************/
190 #ifndef BFLB_USE_ROM_DRIVER
191 __WEAK
AON_Set_Xtal_CapCode(uint8_t capIn,uint8_t capOut)192 BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
193 {
194 uint32_t tmpVal = 0;
195
196 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
197 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn);
198 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut);
199 BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
200
201 BL602_Delay_US(100);
202
203 return SUCCESS;
204 }
205 #endif
206
207 /****************************************************************************/ /**
208 * @brief Get XTAL cap code
209 *
210 * @param None
211 *
212 * @return Cap code
213 *
214 *******************************************************************************/
215 #ifndef BFLB_USE_ROM_DRIVER
216 __WEAK
AON_Get_Xtal_CapCode(void)217 uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
218 {
219 uint32_t tmpVal = 0;
220
221 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
222
223 return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);
224 }
225 #endif
226
227 /****************************************************************************/ /**
228 * @brief Power off XTAL
229 *
230 * @param None
231 *
232 * @return SUCCESS or ERROR
233 *
234 *******************************************************************************/
235 #ifndef BFLB_USE_ROM_DRIVER
236 __WEAK
AON_Power_Off_XTAL(void)237 BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
238 {
239 uint32_t tmpVal = 0;
240
241 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
242 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON);
243 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
244 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
245
246 return SUCCESS;
247 }
248 #endif
249
250 /****************************************************************************/ /**
251 * @brief Power on bandgap system
252 *
253 * @param None
254 *
255 * @return SUCCESS or ERROR
256 *
257 *******************************************************************************/
258 #ifndef BFLB_USE_ROM_DRIVER
259 __WEAK
AON_Power_On_BG(void)260 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
261 {
262 uint32_t tmpVal = 0;
263
264 /* power up RF for PLL to work */
265 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
266 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
267 BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
268
269 BL602_Delay_US(55);
270
271 return SUCCESS;
272 }
273 #endif
274
275 /****************************************************************************/ /**
276 * @brief Power off bandgap system
277 *
278 * @param None
279 *
280 * @return SUCCESS or ERROR
281 *
282 *******************************************************************************/
283 #ifndef BFLB_USE_ROM_DRIVER
284 __WEAK
AON_Power_Off_BG(void)285 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
286 {
287 uint32_t tmpVal = 0;
288
289 /* power up RF for PLL to work */
290 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
291 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
292 BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
293
294 BL602_Delay_US(55);
295
296 return SUCCESS;
297 }
298 #endif
299
300 /****************************************************************************/ /**
301 * @brief Power on LDO11
302 *
303 * @param None
304 *
305 * @return SUCCESS or ERROR
306 *
307 *******************************************************************************/
308 #ifndef BFLB_USE_ROM_DRIVER
309 __WEAK
AON_Power_On_LDO11_SOC(void)310 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void)
311 {
312 uint32_t tmpVal = 0;
313
314 tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
315 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
316 BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
317
318 BL602_Delay_US(55);
319
320 return SUCCESS;
321 }
322 #endif
323
324 /****************************************************************************/ /**
325 * @brief Power off LDO11
326 *
327 * @param None
328 *
329 * @return SUCCESS or ERROR
330 *
331 *******************************************************************************/
332 #ifndef BFLB_USE_ROM_DRIVER
333 __WEAK
AON_Power_Off_LDO11_SOC(void)334 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void)
335 {
336 uint32_t tmpVal = 0;
337
338 tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
339 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
340 BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
341
342 BL602_Delay_US(55);
343
344 return SUCCESS;
345 }
346 #endif
347
348 /****************************************************************************/ /**
349 * @brief Power on LDO15_RF
350 *
351 * @param None
352 *
353 * @return SUCCESS or ERROR
354 *
355 *******************************************************************************/
356 #ifndef BFLB_USE_ROM_DRIVER
357 __WEAK
AON_Power_On_LDO15_RF(void)358 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
359 {
360 uint32_t tmpVal = 0;
361
362 /* ldo15rf power on */
363 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
364 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
365 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
366
367 BL602_Delay_US(90);
368
369 return SUCCESS;
370 }
371 #endif
372
373 /****************************************************************************/ /**
374 * @brief Power off LDO15_RF
375 *
376 * @param None
377 *
378 * @return SUCCESS or ERROR
379 *
380 *******************************************************************************/
381 #ifndef BFLB_USE_ROM_DRIVER
382 __WEAK
AON_Power_Off_LDO15_RF(void)383 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
384 {
385 uint32_t tmpVal = 0;
386
387 /* ldo15rf power off */
388 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
389 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
390 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
391
392 return SUCCESS;
393 }
394 #endif
395
396 /****************************************************************************/ /**
397 * @brief power on source follow regular
398 *
399 * @param None
400 *
401 * @return SUCCESS or ERROR
402 *
403 *******************************************************************************/
404 #ifndef BFLB_USE_ROM_DRIVER
405 __WEAK
AON_Power_On_SFReg(void)406 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
407 {
408 uint32_t tmpVal = 0;
409
410 /* power on sfreg */
411 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
412 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
413 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
414
415 BL602_Delay_US(10);
416
417 return SUCCESS;
418 }
419 #endif
420
421 /****************************************************************************/ /**
422 * @brief power off source follow regular
423 *
424 * @param None
425 *
426 * @return SUCCESS or ERROR
427 *
428 *******************************************************************************/
429 #ifndef BFLB_USE_ROM_DRIVER
430 __WEAK
AON_Power_Off_SFReg(void)431 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
432 {
433 uint32_t tmpVal = 0;
434
435 /* power off sfreg */
436 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
437 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
438 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
439
440 return SUCCESS;
441 }
442 #endif
443
444 /****************************************************************************/ /**
445 * @brief Power off the power can be shut down in PDS0
446 *
447 * @param None
448 *
449 * @return SUCCESS or ERROR
450 *
451 *******************************************************************************/
452 #ifndef BFLB_USE_ROM_DRIVER
453 __WEAK
AON_LowPower_Enter_PDS0(void)454 BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
455 {
456 uint32_t tmpVal = 0;
457
458 /* power off sfreg */
459 tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
460 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
461 BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
462
463 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
464 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
465 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
466 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
467 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
468
469 /* gating Clock */
470 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
471 tmpVal = tmpVal & (~(1 << 6));
472 tmpVal = tmpVal & (~(1 << 7));
473 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
474
475 return SUCCESS;
476 }
477 #endif
478
479 /****************************************************************************/ /**
480 * @brief Power on the power powered down in PDS0
481 *
482 * @param None
483 *
484 * @return SUCCESS or ERROR
485 *
486 *******************************************************************************/
487 #ifndef BFLB_USE_ROM_DRIVER
488 __WEAK
AON_LowPower_Exit_PDS0(void)489 BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
490 {
491 uint32_t tmpVal = 0;
492
493 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
494
495 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
496 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
497
498 BL602_Delay_US(20);
499
500 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
501 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
502
503 BL602_Delay_US(60);
504
505 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
506 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
507
508 BL602_Delay_US(20);
509
510 /* power on wb */
511 tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
512 tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
513 BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
514
515 /* ungating Clock */
516 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
517 tmpVal = tmpVal | ((1 << 6));
518 tmpVal = tmpVal | ((1 << 7));
519 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
520
521 return SUCCESS;
522 }
523 #endif
524
525 /****************************************************************************/ /**
526 * @brief Power on the power powered down in PDS0
527 *
528 * @param delay: None
529 *
530 * @return SUCCESS or ERROR
531 *
532 *******************************************************************************/
AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay)533 BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay)
534 {
535 uint32_t tmpVal = 0;
536
537 CHECK_PARAM((delay <= 0x3));
538
539 /* config ldo11soc_sstart_delay_aon */
540 tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
541 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_SSTART_DELAY_AON, delay);
542 BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
543
544 return SUCCESS;
545 }
546
547 /*@} end of group AON_Public_Functions */
548
549 /*@} end of group AON */
550
551 /*@} end of group BL602_Peripheral_Driver */
552