1 /**
2 ******************************************************************************
3 * @file bl602_glb.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl602_glb.h"
38 #include "bl602_hbn.h"
39
40 /** @addtogroup BL602_Peripheral_Driver
41 * @{
42 */
43
44 /** @addtogroup GLB
45 * @{
46 */
47
48 /** @defgroup GLB_Private_Macros
49 * @{
50 */
51 #define GLB_CLK_SET_DUMMY_WAIT \
52 { \
53 __NOP(); \
54 __NOP(); \
55 __NOP(); \
56 __NOP(); \
57 __NOP(); \
58 __NOP(); \
59 __NOP(); \
60 __NOP(); \
61 }
62 #define GLB_GPIO_Get_Reg(pin) (glb_gpio_reg_t *)(GLB_BASE + GLB_GPIO_OFFSET + (pin / 2) * 4)
63 #define GLB_GPIO_INT0_NUM (23)
64 #define GLB_REG_BCLK_DIS_TRUE (*(volatile uint32_t *)(0x40000FFC) = (0x00000001))
65 #define GLB_REG_BCLK_DIS_FALSE (*(volatile uint32_t *)(0x40000FFC) = (0x00000000))
66 #define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)
67
68 /*@} end of group GLB_Private_Macros */
69
70 /** @defgroup GLB_Private_Types
71 * @{
72 */
73
74 /*@} end of group GLB_Private_Types */
75
76 /** @defgroup GLB_Private_Variables
77 * @{
78 */
79 static intCallback_Type *glbBmxErrIntCbfArra[BMX_ERR_INT_ALL] = { NULL };
80 static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL };
81 static intCallback_Type *glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
82 NULL, NULL, NULL, NULL, NULL, NULL, NULL };
83
84 /*@} end of group GLB_Private_Variables */
85
86 /** @defgroup GLB_Global_Variables
87 * @{
88 */
89
90 /*@} end of group GLB_Global_Variables */
91
92 /** @defgroup GLB_Private_Fun_Declaration
93 * @{
94 */
95
96 /*@} end of group GLB_Private_Fun_Declaration */
97
98 /** @defgroup GLB_Private_Functions
99 * @{
100 */
101
102 /*@} end of group GLB_Private_Functions */
103
104 /** @defgroup GLB_Public_Functions
105 * @{
106 */
107
108 /****************************************************************************/ /**
109 * @brief get root clock selection
110 *
111 * @param None
112 *
113 * @return root clock selection
114 *
115 *******************************************************************************/
116 #ifndef BFLB_USE_ROM_DRIVER
117 __WEAK
GLB_Get_Root_CLK_Sel(void)118 GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void)
119 {
120 uint32_t tmpVal = 0;
121
122 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
123
124 switch (BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL)) {
125 case 0:
126 return GLB_ROOT_CLK_RC32M;
127
128 case 1:
129 return GLB_ROOT_CLK_XTAL;
130
131 case 2:
132 return GLB_ROOT_CLK_PLL;
133
134 case 3:
135 return GLB_ROOT_CLK_PLL;
136
137 default:
138 return GLB_ROOT_CLK_RC32M;
139 }
140 }
141 #endif
142
143 /****************************************************************************/ /**
144 * @brief Set System clock divider
145 *
146 * @param hclkDiv: HCLK divider
147 * @param bclkDiv: BCLK divider
148 *
149 * @return SUCCESS or ERROR
150 *
151 *******************************************************************************/
152 #ifndef BFLB_USE_ROM_DRIVER
153 __WEAK
GLB_Set_System_CLK_Div(uint8_t hclkDiv,uint8_t bclkDiv)154 BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv)
155 {
156 /***********************************************************************************/
157 /* NOTE */
158 /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
159 /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */
160 /***********************************************************************************/
161 uint32_t tmpVal;
162
163 /* recommended: fclk<=160MHz, bclk<=80MHz */
164 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
165 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, hclkDiv);
166 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, bclkDiv);
167 BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
168 GLB_REG_BCLK_DIS_TRUE;
169 GLB_REG_BCLK_DIS_FALSE;
170 SystemCoreClockSet(SystemCoreClockGet() / ((uint16_t)hclkDiv + 1));
171 GLB_CLK_SET_DUMMY_WAIT;
172
173 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
174 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN);
175 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN);
176 BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
177 GLB_CLK_SET_DUMMY_WAIT;
178
179 return SUCCESS;
180 }
181 #endif
182
183 /****************************************************************************/ /**
184 * @brief Get Bus clock divider
185 *
186 * @param None
187 *
188 * @return Clock Divider
189 *
190 *******************************************************************************/
191 #ifndef BFLB_USE_ROM_DRIVER
192 __WEAK
GLB_Get_BCLK_Div(void)193 uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void)
194 {
195 uint32_t tmpVal;
196
197 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
198
199 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
200 }
201 #endif
202
203 /****************************************************************************/ /**
204 * @brief Get CPU clock divider
205 *
206 * @param None
207 *
208 * @return Clock Divider
209 *
210 *******************************************************************************/
211 #ifndef BFLB_USE_ROM_DRIVER
212 __WEAK
GLB_Get_HCLK_Div(void)213 uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void)
214 {
215 uint32_t tmpVal;
216
217 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
218
219 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
220 }
221 #endif
222
223 /****************************************************************************/ /**
224 * @brief update SystemCoreClock value
225 *
226 * @param xtalType: XTAL frequency type
227 *
228 * @return SUCCESS or ERROR
229 *
230 *******************************************************************************/
231 #ifndef BFLB_USE_ROM_DRIVER
232 __WEAK
Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType)233 BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType)
234 {
235 CHECK_PARAM(IS_GLB_PLL_XTAL_TYPE(xtalType));
236
237 switch (xtalType) {
238 case GLB_PLL_XTAL_NONE:
239 break;
240
241 case GLB_PLL_XTAL_24M:
242 SystemCoreClockSet(24000000);
243 break;
244
245 case GLB_PLL_XTAL_32M:
246 SystemCoreClockSet(32000000);
247 break;
248
249 case GLB_PLL_XTAL_38P4M:
250 SystemCoreClockSet(38400000);
251 break;
252
253 case GLB_PLL_XTAL_40M:
254 SystemCoreClockSet(40000000);
255 break;
256
257 case GLB_PLL_XTAL_26M:
258 SystemCoreClockSet(26000000);
259 break;
260
261 case GLB_PLL_XTAL_RC32M:
262 SystemCoreClockSet(32000000);
263 break;
264
265 default:
266 break;
267 }
268
269 return SUCCESS;
270 }
271 #endif
272
273 /****************************************************************************/ /**
274 * @brief Set System clock
275 *
276 * @param xtalType: XTAL frequency type
277 * @param clkFreq: clock frequency selection
278 *
279 * @return SUCCESS or ERROR
280 *
281 *******************************************************************************/
282 #ifndef BFLB_USE_ROM_DRIVER
283 __WEAK
GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType,GLB_SYS_CLK_Type clkFreq)284 BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq)
285 {
286 uint32_t tmpVal;
287
288 CHECK_PARAM(IS_GLB_PLL_XTAL_TYPE(xtalType));
289 CHECK_PARAM(IS_GLB_SYS_CLK_TYPE(clkFreq));
290
291 /* reg_bclk_en = reg_hclk_en = reg_fclk_en = 1, cannot be zero */
292 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
293 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN);
294 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN);
295 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_FCLK_EN);
296 BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
297
298 /* Before config XTAL and PLL ,make sure root clk is from RC32M */
299 HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
300 GLB_Set_System_CLK_Div(0, 0);
301 SystemCoreClockSet(32 * 1000 * 1000);
302
303 /* Select PKA clock from hclk */
304 GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_HCLK);
305
306 if (xtalType == GLB_PLL_XTAL_NONE) {
307 if (clkFreq == GLB_SYS_CLK_RC32M) {
308 return SUCCESS;
309 } else {
310 return ERROR;
311 }
312 }
313
314 if (xtalType != GLB_PLL_XTAL_RC32M) {
315 /* power on xtal first */
316 AON_Power_On_XTAL();
317 }
318
319 /* always power up PLL and enable all PLL clock output */
320 PDS_Power_On_PLL((PDS_PLL_XTAL_Type)xtalType);
321 BL602_Delay_US(55);
322 PDS_Enable_PLL_All_Clks();
323
324 /* reg_pll_en = 1, cannot be zero */
325 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
326 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN);
327 BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
328
329 /* select pll output clock before select root clock */
330 if (clkFreq >= GLB_SYS_CLK_PLL48M) {
331 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
332 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL, clkFreq - GLB_SYS_CLK_PLL48M);
333 BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
334 }
335
336 /* select root clock */
337 switch (clkFreq) {
338 case GLB_SYS_CLK_RC32M:
339 break;
340
341 case GLB_SYS_CLK_XTAL:
342 HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL);
343 Update_SystemCoreClockWith_XTAL(xtalType);
344 break;
345
346 case GLB_SYS_CLK_PLL48M:
347 HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL);
348 SystemCoreClockSet(48 * 1000 * 1000);
349 break;
350
351 case GLB_SYS_CLK_PLL120M:
352 GLB_Set_System_CLK_Div(0, 1);
353 HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL);
354 SystemCoreClockSet(120 * 1000 * 1000);
355 break;
356
357 case GLB_SYS_CLK_PLL160M:
358 L1C_IROM_2T_Access_Set(ENABLE);
359 GLB_Set_System_CLK_Div(0, 1);
360 HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL);
361 SystemCoreClockSet(160 * 1000 * 1000);
362 break;
363
364 case GLB_SYS_CLK_PLL192M:
365 L1C_IROM_2T_Access_Set(ENABLE);
366 GLB_Set_System_CLK_Div(0, 1);
367 HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL);
368 SystemCoreClockSet(192 * 1000 * 1000);
369 break;
370
371 default:
372 break;
373 }
374
375 GLB_CLK_SET_DUMMY_WAIT;
376
377 /* select PKA clock from 120M since we power up PLL */
378 GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_PLL120M);
379
380 return SUCCESS;
381 }
382 #endif
383
384 /****************************************************************************/ /**
385 * @brief This is demo for user that use RC32M as default bootup clock instead of PLL,when APP is
386 * started, this function can be called to set PLL to 160M
387 *
388 * @param None
389 *
390 * @return SUCCESS or ERROR
391 *
392 *******************************************************************************/
393 #ifndef BFLB_USE_ROM_DRIVER
394 __WEAK
System_Core_Clock_Update_From_RC32M(void)395 BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void)
396 {
397 SF_Ctrl_Cfg_Type sfCtrlCfg = {
398 .owner = SF_CTRL_OWNER_IAHB,
399 .clkDelay = 1,
400 .clkInvert = 1,
401 .rxClkInvert = 1,
402 .doDelay = 0,
403 .diDelay = 0,
404 .oeDelay = 0,
405 };
406 /* Use RC32M as PLL ref source to set up PLL to 160M */
407 GLB_Set_System_CLK(GLB_PLL_XTAL_RC32M, GLB_SYS_CLK_PLL160M);
408 /* Flash controller also need changes since system (bus) clock changed */
409 SF_Ctrl_Enable(&sfCtrlCfg);
410 __NOP();
411 __NOP();
412 __NOP();
413 __NOP();
414
415 return SUCCESS;
416 }
417 #endif
418
419 /****************************************************************************/ /**
420 * @brief set BLE clock
421 *
422 * @param enable: Enable or disable BLE clock
423 *
424 * @return SUCCESS or ERROR
425 *
426 *******************************************************************************/
GLB_Set_BLE_CLK(uint8_t enable)427 BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable)
428 {
429 uint32_t tmpVal = 0;
430
431 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
432
433 if (enable) {
434 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BLE_EN);
435 } else {
436 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BLE_EN);
437 }
438
439 BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
440
441 return SUCCESS;
442 }
443
444 /****************************************************************************/ /**
445 * @brief set wifi core clock divider
446 *
447 * @param clkDiv: divider
448 *
449 * @return SUCCESS or ERROR
450 *
451 *******************************************************************************/
GLB_Set_WiFi_Core_CLK(uint8_t clkDiv)452 BL_Err_Type GLB_Set_WiFi_Core_CLK(uint8_t clkDiv)
453 {
454 uint32_t tmpVal = 0;
455
456 CHECK_PARAM((clkDiv <= 0x3));
457
458 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
459 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFI_MAC_CORE_DIV, clkDiv);
460 BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
461
462 return SUCCESS;
463 }
464
465 /****************************************************************************/ /**
466 * @brief set wifi encryption clock
467 *
468 * @param clkDiv: divider
469 *
470 * @return SUCCESS or ERROR
471 *
472 *******************************************************************************/
GLB_Set_WiFi_Encrypt_CLK(uint8_t clkDiv)473 BL_Err_Type GLB_Set_WiFi_Encrypt_CLK(uint8_t clkDiv)
474 {
475 uint32_t tmpVal = 0;
476
477 CHECK_PARAM((clkDiv <= 0x3));
478
479 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
480 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFI_MAC_WT_DIV, clkDiv);
481 BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
482
483 return SUCCESS;
484 }
485
486 /****************************************************************************/ /**
487 * @brief set DMA clock
488 *
489 * @param enable: Enable or disable BLE clock
490 * @param clk: DMA clock type
491 *
492 * @return SUCCESS or ERROR
493 *
494 *******************************************************************************/
GLB_Set_DMA_CLK(uint8_t enable,GLB_DMA_CLK_ID_Type clk)495 BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk)
496 {
497 uint32_t tmpVal;
498 uint32_t tmpVal2;
499
500 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
501 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN);
502
503 if (enable) {
504 tmpVal2 |= (1 << clk);
505 } else {
506 tmpVal2 &= (~(1 << clk));
507 }
508
509 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2);
510 BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
511
512 return SUCCESS;
513 }
514
515 /****************************************************************************/ /**
516 * @brief set IR clock divider
517 *
518 * @param enable: enable or disable IR clock
519 * @param clkSel: IR clock type
520 * @param div: divider
521 *
522 * @return SUCCESS or ERROR
523 *
524 *******************************************************************************/
GLB_Set_IR_CLK(uint8_t enable,GLB_IR_CLK_SRC_Type clkSel,uint8_t div)525 BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div)
526 {
527 uint32_t tmpVal = 0;
528
529 CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel));
530 CHECK_PARAM((div <= 0x3F));
531
532 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
533 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div);
534 BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
535
536 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
537
538 if (enable) {
539 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN);
540 } else {
541 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);
542 }
543
544 BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
545
546 return SUCCESS;
547 }
548
549 /****************************************************************************/ /**
550 * @brief set sflash clock
551 *
552 * @param enable: enable or disable sflash clock
553 * @param clkSel: sflash clock type
554 * @param div: divider
555 *
556 * @return SUCCESS or ERROR
557 *
558 *******************************************************************************/
559 #ifndef BFLB_USE_ROM_DRIVER
560 __WEAK
GLB_Set_SF_CLK(uint8_t enable,GLB_SFLASH_CLK_Type clkSel,uint8_t div)561 BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div)
562 {
563 uint32_t tmpVal = 0;
564 GLB_PLL_CLK_Type clk;
565
566 CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel));
567 CHECK_PARAM((div <= 0x7));
568
569 /* disable SFLASH clock first */
570 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
571 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
572 BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
573
574 /* Select flash clock, all Flash CLKs are divied by PLL_480M */
575 clk = GLB_PLL_CLK_480M;
576 PDS_Enable_PLL_Clk((PDS_PLL_CLK_Type)clk);
577 /* clock divider */
578 /* Select flash clock, all Flash CLKs are divied by PLL_480M */
579 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
580 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div);
581
582 switch (clkSel) {
583 case GLB_SFLASH_CLK_120M:
584 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
585 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0);
586 break;
587
588 case GLB_SFLASH_CLK_XTAL:
589 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
590 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1);
591 break;
592
593 case GLB_SFLASH_CLK_48M:
594 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
595 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3);
596 break;
597
598 case GLB_SFLASH_CLK_80M:
599 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1);
600 break;
601
602 case GLB_SFLASH_CLK_BCLK:
603 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2);
604 break;
605
606 case GLB_SFLASH_CLK_96M:
607 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3);
608 break;
609
610 default:
611 break;
612 }
613
614 BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
615
616 /* enable or disable flash clock */
617 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
618
619 if (enable) {
620 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN);
621 } else {
622 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
623 }
624
625 BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
626
627 return SUCCESS;
628 }
629 #endif
630
631 /****************************************************************************/ /**
632 * @brief Set UART clock
633 *
634 * @param enable: Enable or disable UART clock
635 * @param clkSel: UART clock type
636 * @param div: UART clock divider
637 *
638 * @return SUCCESS or ERROR
639 *
640 *******************************************************************************/
GLB_Set_UART_CLK(uint8_t enable,HBN_UART_CLK_Type clkSel,uint8_t div)641 BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div)
642 {
643 uint32_t tmpVal = 0;
644
645 CHECK_PARAM((div <= 0x7));
646 CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));
647
648 /* disable UART clock first */
649 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
650 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
651 BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
652
653 /* Set div */
654 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
655 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div);
656 BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
657
658 /* Select clock source for uart */
659 HBN_Set_UART_CLK_Sel(clkSel);
660
661 /* Set enable or disable */
662 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
663
664 if (enable) {
665 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN);
666 } else {
667 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
668 }
669
670 BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
671
672 return SUCCESS;
673 }
674
675 /****************************************************************************/ /**
676 * @brief set I2C clock
677 *
678 * @param enable: Enable or disable I2C clock
679 * @param div: divider
680 *
681 * @return SUCCESS or ERROR
682 *
683 *******************************************************************************/
GLB_Set_I2C_CLK(uint8_t enable,uint8_t div)684 BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div)
685 {
686 uint32_t tmpVal = 0;
687
688 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
689 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div);
690 BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
691
692 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
693
694 if (enable) {
695 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
696 } else {
697 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
698 }
699
700 BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
701
702 return SUCCESS;
703 }
704
705 /****************************************************************************/ /**
706 * @brief set SPI clock
707 *
708 * @param enable: Enable or disable SPI clock
709 * @param div: divider
710 *
711 * @return SUCCESS or ERROR
712 *
713 *******************************************************************************/
GLB_Set_SPI_CLK(uint8_t enable,uint8_t div)714 BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div)
715 {
716 uint32_t tmpVal = 0;
717
718 CHECK_PARAM((div <= 0x1F));
719
720 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
721 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div);
722 BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
723
724 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
725
726 if (enable) {
727 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
728 } else {
729 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
730 }
731
732 BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
733
734 return SUCCESS;
735 }
736
737 /****************************************************************************/ /**
738 * @brief select PKA clock source
739 *
740 * @param clkSel: PKA clock selection
741 *
742 * @return SUCCESS or ERROR
743 *
744 *******************************************************************************/
745 #ifndef BFLB_USE_ROM_DRIVER
746 __WEAK
GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel)747 BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel)
748 {
749 uint32_t tmpVal = 0;
750
751 CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel));
752
753 tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
754 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel);
755 BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
756
757 return SUCCESS;
758 }
759 #endif
760
761 /****************************************************************************/ /**
762 * @brief Software system reset
763 *
764 * @param None
765 *
766 * @return SUCCESS or ERROR
767 *
768 *******************************************************************************/
769 #ifndef BFLB_USE_ROM_DRIVER
770 __WEAK
GLB_SW_System_Reset(void)771 BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void)
772 {
773 /***********************************************************************************/
774 /* NOTE */
775 /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
776 /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */
777 /***********************************************************************************/
778 uint32_t tmpVal;
779
780 /* Swicth clock to 32M as default */
781 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
782 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
783 BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
784 GLB_CLK_SET_DUMMY_WAIT;
785
786 /* HCLK is RC32M , so BCLK/HCLK no need divider */
787 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
788 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
789 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
790 BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
791 GLB_REG_BCLK_DIS_TRUE;
792 GLB_REG_BCLK_DIS_FALSE;
793 GLB_CLK_SET_DUMMY_WAIT;
794
795 /* Do reset */
796 tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
797 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
798 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
799 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
800 BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
801
802 tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
803 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
804 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
805 //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST);
806 BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
807
808 /* waiting for reset */
809 while (1) {
810 BL602_Delay_US(10);
811 }
812
813 return SUCCESS;
814 }
815 #endif
816
817 /****************************************************************************/ /**
818 * @brief Software CPU reset
819 *
820 * @param None
821 *
822 * @return SUCCESS or ERROR
823 *
824 *******************************************************************************/
825 #ifndef BFLB_USE_ROM_DRIVER
826 __WEAK
GLB_SW_CPU_Reset(void)827 BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void)
828 {
829 /***********************************************************************************/
830 /* NOTE */
831 /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
832 /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */
833 /***********************************************************************************/
834 uint32_t tmpVal;
835
836 /* Swicth clock to 32M as default */
837 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
838 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
839 BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
840 GLB_CLK_SET_DUMMY_WAIT;
841
842 /* HCLK is RC32M , so BCLK/HCLK no need divider */
843 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
844 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
845 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
846 BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
847 GLB_REG_BCLK_DIS_TRUE;
848 GLB_REG_BCLK_DIS_FALSE;
849 GLB_CLK_SET_DUMMY_WAIT;
850
851 /* Do reset */
852 tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
853 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
854 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
855 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
856 BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
857
858 tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
859 //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_SYS_RESET);
860 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
861 //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST);
862 BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
863
864 /* waiting for reset */
865 while (1) {
866 BL602_Delay_US(10);
867 }
868
869 return SUCCESS;
870 }
871 #endif
872
873 /****************************************************************************/ /**
874 * @brief Software power on reset
875 *
876 * @param None
877 *
878 * @return SUCCESS or ERROR
879 *
880 *******************************************************************************/
881 #ifndef BFLB_USE_ROM_DRIVER
882 __WEAK
GLB_SW_POR_Reset(void)883 BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void)
884 {
885 /***********************************************************************************/
886 /* NOTE */
887 /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
888 /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */
889 /***********************************************************************************/
890 uint32_t tmpVal;
891
892 /* Swicth clock to 32M as default */
893 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
894 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
895 BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
896 GLB_CLK_SET_DUMMY_WAIT;
897
898 /* HCLK is RC32M , so BCLK/HCLK no need divider */
899 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
900 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
901 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
902 BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
903 GLB_REG_BCLK_DIS_TRUE;
904 GLB_REG_BCLK_DIS_FALSE;
905 GLB_CLK_SET_DUMMY_WAIT;
906
907 /* Do reset */
908 tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
909 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
910 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
911 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
912 BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
913
914 tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
915 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
916 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
917 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
918 BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
919
920 /* waiting for reset */
921 while (1) {
922 BL602_Delay_US(10);
923 }
924
925 return SUCCESS;
926 }
927 #endif
928
929 /****************************************************************************/ /**
930 * @brief Reset slave 1
931 *
932 * @param slave1: slave num
933 *
934 * @return SUCCESS or ERROR
935 *
936 *******************************************************************************/
GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1)937 BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1)
938 {
939 uint32_t tmpVal = 0;
940
941 tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
942 tmpVal &= (~(1 << slave1));
943 BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
944 BL_DRV_DUMMY;
945 tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
946 tmpVal |= (1 << slave1);
947 BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
948 BL_DRV_DUMMY;
949 tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
950 tmpVal &= (~(1 << slave1));
951 BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
952
953 return SUCCESS;
954 }
955
956 /****************************************************************************/ /**
957 * @brief clock gate
958 *
959 * @param enable: ENABLE or DISABLE
960 * @param slave1: AHB slaveClk type
961 *
962 * @return SUCCESS or ERROR
963 *
964 *******************************************************************************/
GLB_AHB_Slave1_Clock_Gate(uint8_t enable,BL_AHB_Slave1_Type slave1)965 BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1)
966 {
967 uint32_t tmpVal = 0;
968
969 if ((BL_AHB_SLAVE1_GLB == slave1) || (BL_AHB_SLAVE1_TZ2 == slave1) ||
970 (BL_AHB_SLAVE1_CCI == slave1) || (BL_AHB_SLAVE1_L1C == slave1) ||
971 (BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM == slave1)) {
972 /* not support */
973 return ERROR;
974 }
975
976 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
977
978 if (enable) {
979 /* clear bit means clock gate */
980 tmpVal &= (~(1 << slave1));
981 } else {
982 /* set bit means clock pass */
983 tmpVal |= (1 << slave1);
984 }
985
986 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
987
988 return SUCCESS;
989 }
990
991 /****************************************************************************/ /**
992 * @brief BMX init
993 *
994 * @param BmxCfg: BMX config
995 *
996 * @return SUCCESS or ERROR
997 *
998 *******************************************************************************/
GLB_BMX_Init(BMX_Cfg_Type * BmxCfg)999 BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg)
1000 {
1001 uint32_t tmpVal = 0;
1002
1003 CHECK_PARAM((BmxCfg->timeoutEn) <= 0xF);
1004
1005 tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
1006 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_TIMEOUT_EN, BmxCfg->timeoutEn);
1007 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_EN, BmxCfg->errEn);
1008 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ARB_MODE, BmxCfg->arbMod);
1009 BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);
1010
1011 #ifndef BFLB_USE_HAL_DRIVER
1012 Interrupt_Handler_Register(BMX_ERR_IRQn, BMX_ERR_IRQHandler);
1013 Interrupt_Handler_Register(BMX_TO_IRQn, BMX_TO_IRQHandler);
1014 #endif
1015
1016 return SUCCESS;
1017 }
1018
1019 /****************************************************************************/ /**
1020 * @brief BMX address monitor enable
1021 *
1022 * @param None
1023 *
1024 * @return SUCCESS or ERROR
1025 *
1026 *******************************************************************************/
GLB_BMX_Addr_Monitor_Enable(void)1027 BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void)
1028 {
1029 uint32_t tmpVal = 0;
1030
1031 tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
1032 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS);
1033 BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal);
1034
1035 return SUCCESS;
1036 }
1037
1038 /****************************************************************************/ /**
1039 * @brief BMX address monitor disable
1040 *
1041 * @param None
1042 *
1043 * @return SUCCESS or ERROR
1044 *
1045 *******************************************************************************/
GLB_BMX_Addr_Monitor_Disable(void)1046 BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void)
1047 {
1048 uint32_t tmpVal = 0;
1049
1050 tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
1051 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS);
1052 BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal);
1053
1054 return SUCCESS;
1055 }
1056
1057 /****************************************************************************/ /**
1058 * @brief BMX bus error response enable
1059 *
1060 * @param None
1061 *
1062 * @return SUCCESS or ERROR
1063 *
1064 *******************************************************************************/
GLB_BMX_BusErrResponse_Enable(void)1065 BL_Err_Type GLB_BMX_BusErrResponse_Enable(void)
1066 {
1067 uint32_t tmpVal = 0;
1068
1069 tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
1070 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_EN);
1071 BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);
1072
1073 return SUCCESS;
1074 }
1075
1076 /****************************************************************************/ /**
1077 * @brief BMX bus error response disable
1078 *
1079 * @param None
1080 *
1081 * @return SUCCESS or ERROR
1082 *
1083 *******************************************************************************/
GLB_BMX_BusErrResponse_Disable(void)1084 BL_Err_Type GLB_BMX_BusErrResponse_Disable(void)
1085 {
1086 uint32_t tmpVal = 0;
1087
1088 tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
1089 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_EN);
1090 BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);
1091
1092 return SUCCESS;
1093 }
1094
1095 /****************************************************************************/ /**
1096 * @brief Get BMX error status
1097 *
1098 * @param errType: BMX error status type
1099 *
1100 * @return SET or RESET
1101 *
1102 *******************************************************************************/
GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType)1103 BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType)
1104 {
1105 uint32_t tmpVal = 0;
1106
1107 CHECK_PARAM(IS_BMX_BUS_ERR_TYPE(errType));
1108
1109 tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
1110
1111 if (errType == BMX_BUS_ERR_TRUSTZONE_DECODE) {
1112 return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_TZ) ? SET : RESET;
1113 } else {
1114 return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_DEC) ? SET : RESET;
1115 }
1116 }
1117
1118 /****************************************************************************/ /**
1119 * @brief Get BMX error address
1120 *
1121 * @param None
1122 *
1123 * @return NP BMX error address
1124 *
1125 *******************************************************************************/
GLB_BMX_Get_Err_Addr(void)1126 uint32_t GLB_BMX_Get_Err_Addr(void)
1127 {
1128 return BL_RD_REG(GLB_BASE, GLB_BMX_ERR_ADDR);
1129 }
1130
1131 /****************************************************************************/ /**
1132 * @brief BMX error interrupt callback install
1133 *
1134 * @param intType: BMX error interrupt type
1135 * @param cbFun: callback
1136 *
1137 * @return SUCCESS or ERROR
1138 *
1139 *******************************************************************************/
BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType,intCallback_Type * cbFun)1140 BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun)
1141 {
1142 CHECK_PARAM(IS_BMX_ERR_INT_TYPE(intType));
1143
1144 glbBmxErrIntCbfArra[intType] = cbFun;
1145
1146 return SUCCESS;
1147 }
1148
1149 /****************************************************************************/ /**
1150 * @brief BMX ERR interrupt IRQ handler
1151 *
1152 * @param None
1153 *
1154 * @return None
1155 *
1156 *******************************************************************************/
1157 #ifndef BFLB_USE_HAL_DRIVER
BMX_ERR_IRQHandler(void)1158 void BMX_ERR_IRQHandler(void)
1159 {
1160 BMX_ERR_INT_Type intType;
1161
1162 for (intType = BMX_ERR_INT_ERR; intType < BMX_ERR_INT_ALL; intType++) {
1163 if (glbBmxErrIntCbfArra[intType] != NULL) {
1164 glbBmxErrIntCbfArra[intType]();
1165 }
1166 }
1167
1168 while (1) {
1169 MSG("BMX_ERR_IRQHandler\r\n");
1170 BL602_Delay_MS(1000);
1171 }
1172 }
1173 #endif
1174
1175 /****************************************************************************/ /**
1176 * @brief BMX timeout interrupt callback install
1177 *
1178 * @param intType: BMX timeout interrupt type
1179 * @param cbFun: callback
1180 *
1181 * @return SUCCESS or ERROR
1182 *
1183 *******************************************************************************/
BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType,intCallback_Type * cbFun)1184 BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun)
1185 {
1186 CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType));
1187
1188 glbBmxToIntCbfArra[intType] = cbFun;
1189
1190 return SUCCESS;
1191 }
1192
1193 /****************************************************************************/ /**
1194 * @brief BMX Time Out interrupt IRQ handler
1195 *
1196 * @param None
1197 *
1198 * @return None
1199 *
1200 *******************************************************************************/
1201 #ifndef BFLB_USE_HAL_DRIVER
BMX_TO_IRQHandler(void)1202 void BMX_TO_IRQHandler(void)
1203 {
1204 BMX_TO_INT_Type intType;
1205
1206 for (intType = BMX_TO_INT_TIMEOUT; intType < BMX_TO_INT_ALL; intType++) {
1207 if (glbBmxToIntCbfArra[intType] != NULL) {
1208 glbBmxToIntCbfArra[intType]();
1209 }
1210 }
1211
1212 while (1) {
1213 MSG("BMX_TO_IRQHandler\r\n");
1214 BL602_Delay_MS(1000);
1215 }
1216 }
1217 #endif
1218
1219 /****************************************************************************/ /**
1220 * @brief set sram_ret value
1221 *
1222 * @param value: value
1223 *
1224 * @return SUCCESS or ERROR
1225 *
1226 *******************************************************************************/
GLB_Set_SRAM_RET(uint32_t value)1227 BL_Err_Type GLB_Set_SRAM_RET(uint32_t value)
1228 {
1229 BL_WR_REG(GLB_BASE, GLB_SRAM_RET, value);
1230
1231 return SUCCESS;
1232 }
1233
1234 /****************************************************************************/ /**
1235 * @brief get sram_ret value
1236 *
1237 * @param None
1238 *
1239 * @return value
1240 *
1241 *******************************************************************************/
GLB_Get_SRAM_RET(void)1242 uint32_t GLB_Get_SRAM_RET(void)
1243 {
1244 return BL_RD_REG(GLB_BASE, GLB_SRAM_RET);
1245 }
1246
1247 /****************************************************************************/ /**
1248 * @brief set sram_slp value
1249 *
1250 * @param value: value
1251 *
1252 * @return SUCCESS or ERROR
1253 *
1254 *******************************************************************************/
GLB_Set_SRAM_SLP(uint32_t value)1255 BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value)
1256 {
1257 BL_WR_REG(GLB_BASE, GLB_SRAM_SLP, value);
1258
1259 return SUCCESS;
1260 }
1261
1262 /****************************************************************************/ /**
1263 * @brief get sram_slp value
1264 *
1265 * @param None
1266 *
1267 * @return value
1268 *
1269 *******************************************************************************/
GLB_Get_SRAM_SLP(void)1270 uint32_t GLB_Get_SRAM_SLP(void)
1271 {
1272 return BL_RD_REG(GLB_BASE, GLB_SRAM_SLP);
1273 }
1274
1275 /****************************************************************************/ /**
1276 * @brief set sram_param value
1277 *
1278 * @param value: value
1279 *
1280 * @return SUCCESS or ERROR
1281 *
1282 *******************************************************************************/
GLB_Set_SRAM_PARM(uint32_t value)1283 BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value)
1284 {
1285 BL_WR_REG(GLB_BASE, GLB_SRAM_PARM, value);
1286
1287 return SUCCESS;
1288 }
1289
1290 /****************************************************************************/ /**
1291 * @brief get sram_parm value
1292 *
1293 * @param None
1294 *
1295 * @return value
1296 *
1297 *******************************************************************************/
GLB_Get_SRAM_PARM(void)1298 uint32_t GLB_Get_SRAM_PARM(void)
1299 {
1300 return BL_RD_REG(GLB_BASE, GLB_SRAM_PARM);
1301 }
1302
1303 /****************************************************************************/ /**
1304 * @brief select EM type
1305 *
1306 * @param emType: EM type
1307 *
1308 * @return SUCCESS or ERROR
1309 *
1310 *******************************************************************************/
GLB_Set_EM_Sel(GLB_EM_Type emType)1311 BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType)
1312 {
1313 uint32_t tmpVal = 0;
1314
1315 CHECK_PARAM(IS_GLB_EM_TYPE(emType));
1316
1317 tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
1318 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, emType);
1319 BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
1320
1321 return SUCCESS;
1322 }
1323
1324 /****************************************************************************/ /**
1325 * @brief swap UART gpio pins sig function
1326 *
1327 * @param swapSel: UART swap set gpio pins selection
1328 *
1329 * @return SUCCESS or ERROR
1330 *
1331 *******************************************************************************/
GLB_UART_Sig_Swap_Set(uint8_t swapSel)1332 BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel)
1333 {
1334 uint32_t tmpVal = 0;
1335
1336 CHECK_PARAM((swapSel <= 0x7));
1337
1338 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
1339 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, swapSel);
1340 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
1341
1342 return SUCCESS;
1343 }
1344
1345 /****************************************************************************/ /**
1346 * @brief swap JTAG gpio pins function
1347 *
1348 * @param swapSel: ENABLE or DISABLE
1349 *
1350 * @return SUCCESS or ERROR
1351 *
1352 *******************************************************************************/
GLB_JTAG_Sig_Swap_Set(uint8_t swapSel)1353 BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel)
1354 {
1355 uint32_t tmpVal = 0;
1356
1357 CHECK_PARAM((swapSel <= 0x3F));
1358
1359 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
1360 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_JTAG_SWAP_SET, swapSel);
1361 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
1362
1363 return SUCCESS;
1364 }
1365
1366 /****************************************************************************/ /**
1367 * @brief swap SPI0 MOSI with MISO
1368 *
1369 * @param newState: ENABLE or DISABLE
1370 *
1371 * @return SUCCESS or ERROR
1372 *
1373 *******************************************************************************/
GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState)1374 BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState)
1375 {
1376 uint32_t tmpVal = 0;
1377
1378 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
1379 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState);
1380 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
1381
1382 return SUCCESS;
1383 }
1384
1385 /****************************************************************************/ /**
1386 * @brief Select SPI_0 act mode
1387 *
1388 * @param mod: SPI work mode
1389 *
1390 * @return SUCCESS or ERROR
1391 *
1392 *******************************************************************************/
GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)1393 BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)
1394 {
1395 uint32_t tmpVal;
1396
1397 CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod));
1398
1399 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
1400 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod);
1401 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
1402
1403 return SUCCESS;
1404 }
1405
1406 /****************************************************************************/ /**
1407 * @brief use internal flash
1408 *
1409 * @param None
1410 *
1411 * @return SUCCESS or ERROR
1412 *
1413 *******************************************************************************/
1414 #ifndef BFLB_USE_ROM_DRIVER
1415 __WEAK
GLB_Select_Internal_Flash(void)1416 BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_Flash(void)
1417 {
1418 uint32_t tmpVal;
1419
1420 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
1421 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH);
1422 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
1423
1424 return SUCCESS;
1425 }
1426 #endif
1427
1428 /****************************************************************************/ /**
1429 * @brief use external flash
1430 *
1431 * @param None
1432 *
1433 * @return SUCCESS or ERROR
1434 *
1435 *******************************************************************************/
1436 #ifndef BFLB_USE_ROM_DRIVER
1437 __WEAK
GLB_Select_External_Flash(void)1438 BL_Err_Type ATTR_TCM_SECTION GLB_Select_External_Flash(void)
1439 {
1440 uint32_t tmpVal;
1441
1442 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
1443 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH);
1444 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
1445
1446 return SUCCESS;
1447 }
1448 #endif
1449
1450 /****************************************************************************/ /**
1451 * @brief Deswap internal flash IO3 and IO0 pin
1452 *
1453 * @param None
1454 *
1455 * @return SUCCESS or ERROR
1456 *
1457 *******************************************************************************/
1458 #ifndef BFLB_USE_ROM_DRIVER
1459 __WEAK
GLB_Deswap_Flash_Pin(void)1460 BL_Err_Type ATTR_TCM_SECTION GLB_Deswap_Flash_Pin(void)
1461 {
1462 uint32_t tmpVal;
1463
1464 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
1465 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);
1466 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
1467
1468 return SUCCESS;
1469 }
1470 #endif
1471
1472 /****************************************************************************/ /**
1473 * @brief Swap internal flash IO3 and IO0 pin
1474 *
1475 * @param None
1476 *
1477 * @return SUCCESS or ERROR
1478 *
1479 *******************************************************************************/
1480 #ifndef BFLB_USE_ROM_DRIVER
1481 __WEAK
GLB_Swap_Flash_Pin(void)1482 BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_Pin(void)
1483 {
1484 uint32_t tmpVal;
1485
1486 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
1487 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);
1488 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
1489
1490 return SUCCESS;
1491 }
1492 #endif
1493
1494 /****************************************************************************/ /**
1495 * @brief set MTimer clock
1496 *
1497 * @param enable: enable or disable MTimer clock
1498 * @param clkSel: clock selection
1499 * @param div: divider
1500 *
1501 * @return SUCCESS or ERROR
1502 *
1503 *******************************************************************************/
GLB_Set_MTimer_CLK(uint8_t enable,GLB_MTIMER_CLK_Type clkSel,uint32_t div)1504 BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div)
1505 {
1506 uint32_t tmpVal;
1507
1508 CHECK_PARAM(IS_GLB_MTIMER_CLK_TYPE(clkSel));
1509 CHECK_PARAM((div <= 0x1FFFF));
1510
1511 /* disable MTimer clock first */
1512 tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
1513 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
1514 BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);
1515
1516 tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
1517 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_SEL, clkSel);
1518 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_DIV, div);
1519 BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);
1520
1521 tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
1522
1523 if (enable) {
1524 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
1525 } else {
1526 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
1527 }
1528
1529 BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);
1530
1531 return SUCCESS;
1532 }
1533
1534 /****************************************************************************/ /**
1535 * @brief set ADC clock
1536 *
1537 * @param enable: enable frequency divider or not
1538 * @param clkSel: ADC clock selection
1539 * @param div: divider
1540 *
1541 * @return SUCCESS or ERROR
1542 *
1543 *******************************************************************************/
GLB_Set_ADC_CLK(uint8_t enable,GLB_ADC_CLK_Type clkSel,uint8_t div)1544 BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div)
1545 {
1546 uint32_t tmpVal;
1547
1548 CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel));
1549
1550 /* disable ADC clock first */
1551 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
1552 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
1553 BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);
1554
1555 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
1556 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div);
1557 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel);
1558 BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);
1559
1560 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
1561
1562 if (enable) {
1563 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
1564 } else {
1565 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
1566 }
1567
1568 BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);
1569
1570 return SUCCESS;
1571 }
1572
1573 /****************************************************************************/ /**
1574 * @brief set DAC clock
1575 *
1576 * @param enable: enable frequency divider or not
1577 * @param clkSel: ADC clock selection
1578 * @param div: src divider
1579 *
1580 * @return SUCCESS or ERROR
1581 *
1582 *******************************************************************************/
GLB_Set_DAC_CLK(uint8_t enable,GLB_DAC_CLK_Type clkSel,uint8_t div)1583 BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div)
1584 {
1585 uint32_t tmpVal;
1586
1587 CHECK_PARAM(IS_GLB_DAC_CLK_TYPE(clkSel));
1588
1589 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
1590 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
1591 BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
1592
1593 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
1594
1595 if (clkSel == GLB_DAC_CLK_32M) {
1596 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_CLK_SRC_SEL);
1597 } else {
1598 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_CLK_SRC_SEL);
1599 }
1600
1601 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);
1602
1603 if (enable) {
1604 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);
1605 } else {
1606 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
1607 }
1608
1609 BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
1610
1611 return SUCCESS;
1612 }
1613
1614 /****************************************************************************/ /**
1615 * @brief platform wakeup will becomes one of pds_wakeup source
1616 *
1617 * @param None
1618 *
1619 * @return SUCCESS or ERROR
1620 *
1621 *******************************************************************************/
GLB_Platform_Wakeup_Enable(void)1622 BL_Err_Type GLB_Platform_Wakeup_Enable(void)
1623 {
1624 uint32_t tmpVal;
1625
1626 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
1627 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP);
1628 BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
1629
1630 return SUCCESS;
1631 }
1632
1633 /****************************************************************************/ /**
1634 * @brief platform wakeup will not becomes one of pds_wakeup source
1635 *
1636 * @param None
1637 *
1638 * @return SUCCESS or ERROR
1639 *
1640 *******************************************************************************/
GLB_Platform_Wakeup_Disable(void)1641 BL_Err_Type GLB_Platform_Wakeup_Disable(void)
1642 {
1643 uint32_t tmpVal;
1644
1645 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
1646 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP);
1647 BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
1648
1649 return SUCCESS;
1650 }
1651
1652 /****************************************************************************/ /**
1653 * @brief select DIG clock source
1654 *
1655 * @param clkSel: DIG clock selection
1656 *
1657 * @return SUCCESS or ERROR
1658 *
1659 *******************************************************************************/
GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel)1660 BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel)
1661 {
1662 uint32_t tmpVal;
1663 uint32_t dig512kEn;
1664 uint32_t dig32kEn;
1665
1666 /* disable DIG512K and DIG32K clock first */
1667 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
1668 dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN);
1669 dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN);
1670 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
1671 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
1672 BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
1673
1674 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
1675 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel);
1676 BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
1677
1678 /* repristinate DIG512K and DIG32K clock */
1679 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
1680 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn);
1681 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn);
1682 BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
1683
1684 return SUCCESS;
1685 }
1686
1687 /****************************************************************************/ /**
1688 * @brief set DIG 512K clock
1689 *
1690 * @param enable: enable or disable DIG 512K clock
1691 * @param compensation: enable or disable DIG 512K clock compensation
1692 * @param div: divider
1693 *
1694 * @return SUCCESS or ERROR
1695 *
1696 *******************************************************************************/
GLB_Set_DIG_512K_CLK(uint8_t enable,uint8_t compensation,uint8_t div)1697 BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div)
1698 {
1699 uint32_t tmpVal;
1700
1701 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
1702
1703 if (compensation) {
1704 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
1705 } else {
1706 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
1707 }
1708
1709 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);
1710 BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
1711
1712 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
1713
1714 if (enable) {
1715 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);
1716 } else {
1717 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
1718 }
1719
1720 BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
1721
1722 return SUCCESS;
1723 }
1724
1725 /****************************************************************************/ /**
1726 * @brief set DIG 32K clock
1727 *
1728 * @param enable: enable or disable DIG 32K clock
1729 * @param compensation: enable or disable DIG 32K clock compensation
1730 * @param div: divider
1731 *
1732 * @return SUCCESS or ERROR
1733 *
1734 *******************************************************************************/
GLB_Set_DIG_32K_CLK(uint8_t enable,uint8_t compensation,uint16_t div)1735 BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint16_t div)
1736 {
1737 uint32_t tmpVal;
1738
1739 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
1740
1741 if (compensation) {
1742 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
1743 } else {
1744 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
1745 }
1746
1747 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div);
1748 BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
1749
1750 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
1751
1752 if (enable) {
1753 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN);
1754 } else {
1755 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
1756 }
1757
1758 BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
1759
1760 return SUCCESS;
1761 }
1762
1763 /****************************************************************************/ /**
1764 * @brief set BT coex signal
1765 *
1766 * @param enable: ENABLE or DISABLE, if enable, the AP JTAG will be replaced by BT Coex Signal
1767 * @param bandWidth: BT Bandwidth
1768 * @param pti: BT Packet Traffic Information
1769 * @param channel: BT Channel
1770 *
1771 * @return SUCCESS or ERROR
1772 *
1773 *******************************************************************************/
GLB_Set_BT_Coex_Signal(uint8_t enable,GLB_BT_BANDWIDTH_Type bandWidth,uint8_t pti,uint8_t channel)1774 BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, uint8_t pti, uint8_t channel)
1775 {
1776 uint32_t tmpVal = 0;
1777
1778 CHECK_PARAM(IS_GLB_BT_BANDWIDTH_TYPE(bandWidth));
1779 CHECK_PARAM((pti <= 0xF));
1780 CHECK_PARAM((channel <= 78));
1781
1782 tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL);
1783 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_BW, bandWidth);
1784 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_PTI, pti);
1785 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_CHANNEL, channel);
1786 BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal);
1787
1788 tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL);
1789
1790 if (enable) {
1791 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 1);
1792 } else {
1793 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 0);
1794 }
1795
1796 BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal);
1797
1798 return SUCCESS;
1799 }
1800
1801 /****************************************************************************/ /**
1802 * @brief Select UART signal function
1803 *
1804 * @param sig: UART signal
1805 * @param fun: UART function
1806 *
1807 * @return SUCCESS or ERROR
1808 *
1809 *******************************************************************************/
GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig,GLB_UART_SIG_FUN_Type fun)1810 BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun)
1811 {
1812 uint32_t sig_pos = 0;
1813 uint32_t tmpVal = 0;
1814
1815 CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig));
1816 CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun));
1817
1818 tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0);
1819 sig_pos = (sig * 4);
1820 /* Clear original val */
1821 tmpVal &= (~(0xf << sig_pos));
1822 /* Set new value */
1823 tmpVal |= (fun << sig_pos);
1824 BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmpVal);
1825
1826 return SUCCESS;
1827 }
1828
1829 /****************************************************************************/ /**
1830 * @brief Select ir rx gpio (gpio11~gpio13)
1831 *
1832 * @param gpio: IR gpio selected
1833 *
1834 * @return SUCCESS or ERROR
1835 *
1836 *******************************************************************************/
GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio)1837 BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio)
1838 {
1839 uint32_t tmpVal = 0;
1840
1841 /* Select gpio between gpio11 and gpio13 */
1842 if (gpio > 10 && gpio < 14) {
1843 tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
1844 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 10);
1845 BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
1846 }
1847
1848 /* Close ir rx */
1849 if (gpio == 0) {
1850 tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
1851 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, 0);
1852 BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
1853 }
1854
1855 return SUCCESS;
1856 }
1857
1858 /****************************************************************************/ /**
1859 * @brief Enable ir led driver
1860 *
1861 * @param None
1862 *
1863 * @return SUCCESS or ERROR
1864 *
1865 *******************************************************************************/
GLB_IR_LED_Driver_Enable(void)1866 BL_Err_Type GLB_IR_LED_Driver_Enable(void)
1867 {
1868 uint32_t tmpVal = 0;
1869
1870 /* Enable led driver */
1871 tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
1872 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV);
1873 BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
1874
1875 return SUCCESS;
1876 }
1877
1878 /****************************************************************************/ /**
1879 * @brief Disable ir led driver
1880 *
1881 * @param None
1882 *
1883 * @return SUCCESS or ERROR
1884 *
1885 *******************************************************************************/
GLB_IR_LED_Driver_Disable(void)1886 BL_Err_Type GLB_IR_LED_Driver_Disable(void)
1887 {
1888 uint32_t tmpVal = 0;
1889
1890 /* Disable led driver */
1891 tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
1892 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV);
1893 BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
1894
1895 return SUCCESS;
1896 }
1897
1898 /****************************************************************************/ /**
1899 * @brief Set ir led driver ibias
1900 *
1901 * @param ibias: Ibias value,0x0:0mA~0xf:120mA,8mA/step
1902 *
1903 * @return SUCCESS or ERROR
1904 *
1905 *******************************************************************************/
GLB_IR_LED_Driver_Ibias(uint8_t ibias)1906 BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias)
1907 {
1908 uint32_t tmpVal = 0;
1909
1910 /* Set driver ibias */
1911 tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
1912 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_IBIAS, ibias & 0xF);
1913 BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
1914
1915 return SUCCESS;
1916 }
1917
1918 /****************************************************************************/ /**
1919 * @brief GPIO initialization
1920 *
1921 * @param cfg: GPIO configuration
1922 *
1923 * @return SUCCESS or ERROR
1924 *
1925 *******************************************************************************/
GLB_GPIO_Init(GLB_GPIO_Cfg_Type * cfg)1926 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
1927 {
1928 uint8_t gpioPin = cfg->gpioPin;
1929 uint32_t *pOut;
1930 uint32_t pos;
1931 uint32_t tmpOut;
1932 uint32_t tmpVal;
1933
1934 /* drive strength(drive) = 0 <=> 8.0mA @ 3.3V */
1935 /* drive strength(drive) = 1 <=> 9.6mA @ 3.3V */
1936 /* drive strength(drive) = 2 <=> 11.2mA @ 3.3V */
1937 /* drive strength(drive) = 3 <=> 12.8mA @ 3.3V */
1938
1939 pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
1940 pos = gpioPin % 32;
1941 tmpOut = *pOut;
1942
1943 /* Disable output anyway*/
1944 tmpOut &= (~(1 << pos));
1945 *pOut = tmpOut;
1946
1947 tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
1948
1949 if (gpioPin % 2 == 0) {
1950 if (cfg->gpioMode != GPIO_MODE_ANALOG) {
1951 /* not analog mode */
1952
1953 /* Set input or output */
1954 if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
1955 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
1956 tmpOut |= (1 << pos);
1957 } else {
1958 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
1959 }
1960
1961 /* Set pull up or down */
1962 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
1963 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
1964
1965 if (cfg->pullType == GPIO_PULL_UP) {
1966 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
1967 } else if (cfg->pullType == GPIO_PULL_DOWN) {
1968 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
1969 }
1970 } else {
1971 /* analog mode */
1972
1973 /* clear ie && oe */
1974 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
1975 tmpOut &= ~(1 << pos);
1976
1977 /* clear pu && pd */
1978 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
1979 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
1980 }
1981
1982 /* set drive && smt && func */
1983 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive);
1984 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl);
1985 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
1986 } else {
1987 if (cfg->gpioMode != GPIO_MODE_ANALOG) {
1988 /* not analog mode */
1989
1990 /* Set input or output */
1991 if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
1992 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
1993 tmpOut |= (1 << pos);
1994 } else {
1995 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
1996 }
1997
1998 /* Set pull up or down */
1999 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
2000 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
2001
2002 if (cfg->pullType == GPIO_PULL_UP) {
2003 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
2004 } else if (cfg->pullType == GPIO_PULL_DOWN) {
2005 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
2006 }
2007 } else {
2008 /* analog mode */
2009
2010 /* clear ie && oe */
2011 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
2012 tmpOut &= ~(1 << pos);
2013
2014 /* clear pu && pd */
2015 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
2016 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
2017 }
2018
2019 /* set drive && smt && func */
2020 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_DRV, cfg->drive);
2021 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_SMT, cfg->smtCtrl);
2022 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun);
2023 }
2024
2025 BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
2026
2027 *pOut = tmpOut;
2028
2029 return SUCCESS;
2030 }
2031
2032 /****************************************************************************/ /**
2033 * @brief init GPIO function in pin list
2034 *
2035 * @param gpioFun: GPIO pin function
2036 * @param pinList: GPIO pin list
2037 * @param cnt: GPIO pin count
2038 *
2039 * @return SUCCESS or ERROR
2040 *
2041 *******************************************************************************/
GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun,GLB_GPIO_Type * pinList,uint8_t cnt)2042 BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt)
2043 {
2044 GLB_GPIO_Cfg_Type gpioCfg = {
2045 .gpioPin = GLB_GPIO_PIN_0,
2046 .gpioFun = (uint8_t)gpioFun,
2047 .gpioMode = GPIO_MODE_AF,
2048 .pullType = GPIO_PULL_UP,
2049 .drive = 1,
2050 .smtCtrl = 1
2051 };
2052
2053 if (gpioFun == GPIO_FUN_ANALOG) {
2054 gpioCfg.gpioMode = GPIO_MODE_ANALOG;
2055 }
2056
2057 for (uint8_t i = 0; i < cnt; i++) {
2058 gpioCfg.gpioPin = pinList[i];
2059 GLB_GPIO_Init(&gpioCfg);
2060 }
2061
2062 return SUCCESS;
2063 }
2064
2065 /****************************************************************************/ /**
2066 * @brief GPIO set input function enable
2067 *
2068 * @param gpioPin: GPIO pin
2069 *
2070 * @return SUCCESS or ERROR
2071 *
2072 *******************************************************************************/
GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin)2073 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin)
2074 {
2075 uint32_t tmpVal;
2076 uint32_t pinOffset;
2077
2078 pinOffset = (gpioPin >> 1) << 2;
2079 tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset);
2080
2081 if (gpioPin % 2 == 0) {
2082 /* [0] is ie */
2083 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
2084 } else {
2085 /* [16] is ie */
2086 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
2087 }
2088
2089 *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal;
2090
2091 return SUCCESS;
2092 }
2093
2094 /****************************************************************************/ /**
2095 * @brief GPIO set input function disable
2096 *
2097 * @param gpioPin: GPIO pin
2098 *
2099 * @return SUCCESS or ERROR
2100 *
2101 *******************************************************************************/
GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin)2102 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin)
2103 {
2104 uint32_t tmpVal;
2105 uint32_t pinOffset;
2106
2107 pinOffset = (gpioPin >> 1) << 2;
2108 tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset);
2109
2110 if (gpioPin % 2 == 0) {
2111 /* [0] is ie */
2112 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
2113 } else {
2114 /* [16] is ie */
2115 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
2116 }
2117
2118 *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal;
2119
2120 return SUCCESS;
2121 }
2122
2123 /****************************************************************************/ /**
2124 * @brief GPIO set output function enable
2125 *
2126 * @param gpioPin: GPIO pin
2127 *
2128 * @return SUCCESS or ERROR
2129 *
2130 *******************************************************************************/
2131 #ifndef BFLB_USE_ROM_DRIVER
2132 __WEAK
GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin)2133 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin)
2134 {
2135 uint32_t tmpVal;
2136
2137 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34);
2138 tmpVal = tmpVal | (1 << gpioPin);
2139 BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal);
2140
2141 return SUCCESS;
2142 }
2143 #endif
2144
2145 /****************************************************************************/ /**
2146 * @brief GPIO set output function disable
2147 *
2148 * @param gpioPin: GPIO pin
2149 *
2150 * @return SUCCESS or ERROR
2151 *
2152 *******************************************************************************/
2153 #ifndef BFLB_USE_ROM_DRIVER
2154 __WEAK
GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin)2155 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin)
2156 {
2157 uint32_t tmpVal;
2158
2159 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34);
2160 tmpVal = tmpVal & ~(1 << gpioPin);
2161 BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal);
2162
2163 return SUCCESS;
2164 }
2165 #endif
2166
2167 /****************************************************************************/ /**
2168 * @brief GPIO set High-Z
2169 *
2170 * @param gpioPin: GPIO pin
2171 *
2172 * @return SUCCESS or ERROR
2173 *
2174 *******************************************************************************/
2175 #ifndef BFLB_USE_ROM_DRIVER
2176 __WEAK
GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)2177 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
2178 {
2179 uint32_t *pOut;
2180 uint32_t pos;
2181 uint32_t tmpOut;
2182 uint32_t tmpVal;
2183
2184 pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
2185 pos = gpioPin % 32;
2186 tmpOut = *pOut;
2187
2188 /* Disable output anyway*/
2189 tmpOut &= (~(1 << pos));
2190 *pOut = tmpOut;
2191
2192 tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
2193
2194 /* select GPIO_FUN_GPIO as FUNC_SEL */
2195 if (gpioPin % 2 == 0) {
2196 tmpVal = (tmpVal & 0xffff0000);
2197 tmpVal |= 0x0B00;
2198 } else {
2199 tmpVal = (tmpVal & 0x0000ffff);
2200 tmpVal |= (0x0B00 << 16);
2201 }
2202
2203 BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
2204
2205 /* Disable output anyway*/
2206 *pOut = tmpOut;
2207
2208 return SUCCESS;
2209 }
2210 #endif
2211
2212 /****************************************************************************/ /**
2213 * @brief GPIO set Pull up
2214 *
2215 * @param gpioPin: GPIO pin
2216 *
2217 * @return SUCCESS or ERROR
2218 *
2219 *******************************************************************************/
2220 __WEAK
GLB_GPIO_Set_PullUp(GLB_GPIO_Type gpioPin)2221 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_PullUp(GLB_GPIO_Type gpioPin)
2222 {
2223 uint32_t tmpVal;
2224
2225 tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
2226
2227 /* Set Pull up */
2228 if (gpioPin % 2 == 0) {
2229 tmpVal &= (~(1 << 5));
2230 tmpVal |= (1 << 4);
2231 } else {
2232 tmpVal &= (~(1 << 21));
2233 tmpVal |= (1 << 20);
2234 }
2235
2236 BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
2237
2238 return SUCCESS;
2239 }
2240
2241 /****************************************************************************/ /**
2242 * @brief GPIO set Pull down
2243 *
2244 * @param gpioPin: GPIO pin
2245 *
2246 * @return SUCCESS or ERROR
2247 *
2248 *******************************************************************************/
2249 __WEAK
GLB_GPIO_Set_PullDown(GLB_GPIO_Type gpioPin)2250 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_PullDown(GLB_GPIO_Type gpioPin)
2251 {
2252 uint32_t tmpVal;
2253
2254 tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
2255
2256 /* Set Pull up */
2257 if (gpioPin % 2 == 0) {
2258 tmpVal &= (~(1 << 4));
2259 tmpVal |= (1 << 5);
2260 } else {
2261 tmpVal &= (~(1 << 20));
2262 tmpVal |= (1 << 21);
2263 }
2264
2265 BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
2266
2267 return SUCCESS;
2268 }
2269
2270 /****************************************************************************/ /**
2271 * @brief Get GPIO function
2272 *
2273 * @param gpioPin: GPIO type
2274 *
2275 * @return GPIO function
2276 *
2277 *******************************************************************************/
2278 #ifndef BFLB_USE_ROM_DRIVER
2279 __WEAK
GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)2280 uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)
2281 {
2282 uint32_t tmpVal;
2283 tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
2284
2285 if (gpioPin % 2 == 0) {
2286 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL);
2287 } else {
2288 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL);
2289 }
2290 }
2291 #endif
2292
2293 /****************************************************************************/ /**
2294 * @brief Get GPIO0-GPIO5 real function
2295 *
2296 * @param gpioPin: GPIO type
2297 *
2298 * @return GPIO real function
2299 *
2300 *******************************************************************************/
GLB_GPIO_Get_Real_Fun(GLB_GPIO_Type gpioPin)2301 GLB_GPIO_REAL_MODE_Type GLB_GPIO_Get_Real_Fun(GLB_GPIO_Type gpioPin)
2302 {
2303 uint32_t tmpVal;
2304
2305 CHECK_PARAM((gpioPin <= GLB_GPIO_PIN_5));
2306
2307 tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
2308
2309 if (gpioPin % 2 == 0) {
2310 return (GLB_GPIO_REAL_MODE_Type)BL_GET_REG_BITS_VAL(tmpVal, GLB_REAL_GPIO_0_FUNC_SEL);
2311 } else {
2312 return (GLB_GPIO_REAL_MODE_Type)BL_GET_REG_BITS_VAL(tmpVal, GLB_REAL_GPIO_1_FUNC_SEL);
2313 }
2314 }
2315
2316 /****************************************************************************/ /**
2317 * @brief Write GPIO
2318 *
2319 * @param gpioPin: GPIO type
2320 * @param val: GPIO value
2321 *
2322 * @return SUCCESS or ERROR
2323 *
2324 *******************************************************************************/
GLB_GPIO_Write(GLB_GPIO_Type gpioPin,uint32_t val)2325 BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val)
2326 {
2327 uint32_t *pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_OFFSET + ((gpioPin >> 5) << 2));
2328 uint32_t pos = gpioPin % 32;
2329 uint32_t tmpOut;
2330
2331 tmpOut = *pOut;
2332
2333 if (val > 0) {
2334 tmpOut |= (1 << pos);
2335 } else {
2336 tmpOut &= (~(1 << pos));
2337 }
2338
2339 *pOut = tmpOut;
2340
2341 return SUCCESS;
2342 }
2343
2344 /****************************************************************************/ /**
2345 * @brief Read GPIO
2346 *
2347 * @param gpioPin: GPIO type
2348 *
2349 * @return GPIO value
2350 *
2351 *******************************************************************************/
GLB_GPIO_Read(GLB_GPIO_Type gpioPin)2352 uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin)
2353 {
2354 uint32_t *p = (uint32_t *)(GLB_BASE + GLB_GPIO_INPUT_OFFSET + ((gpioPin >> 5) << 2));
2355 uint32_t pos = gpioPin % 32;
2356
2357 if ((*p) & (1 << pos)) {
2358 return 1;
2359 } else {
2360 return 0;
2361 }
2362 }
2363
2364 /****************************************************************************/ /**
2365 * @brief Set GLB GPIO interrupt mask
2366 *
2367 * @param gpioPin: GPIO type
2368 * @param intMask: GPIO interrupt MASK or UNMASK
2369 *
2370 * @return SUCCESS or ERROR
2371 *
2372 *******************************************************************************/
GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin,BL_Mask_Type intMask)2373 BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask)
2374 {
2375 uint32_t tmpVal;
2376
2377 if (gpioPin < 32) {
2378 /* GPIO0 ~ GPIO31 */
2379 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1);
2380
2381 if (intMask == MASK) {
2382 tmpVal = tmpVal | (1 << gpioPin);
2383 } else {
2384 tmpVal = tmpVal & ~(1 << gpioPin);
2385 }
2386
2387 BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MASK1, tmpVal);
2388 }
2389
2390 return SUCCESS;
2391 }
2392
2393 /****************************************************************************/ /**
2394 * @brief Set GLB GPIO interrupt mask
2395 *
2396 * @param gpioPin: GPIO type
2397 * @param intClear: GPIO interrupt clear or unclear
2398 *
2399 * @return SUCCESS or ERROR
2400 *
2401 *******************************************************************************/
GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin,BL_Sts_Type intClear)2402 BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear)
2403 {
2404 uint32_t tmpVal;
2405
2406 if (gpioPin < 32) {
2407 /* GPIO0 ~ GPIO31 */
2408 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1);
2409
2410 if (intClear == SET) {
2411 tmpVal = tmpVal | (1 << gpioPin);
2412 } else {
2413 tmpVal = tmpVal & ~(1 << gpioPin);
2414 }
2415
2416 BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal);
2417 }
2418
2419 return SUCCESS;
2420 }
2421
2422 /****************************************************************************/ /**
2423 * @brief Get GLB GPIO interrrupt status
2424 *
2425 * @param gpioPin: GPIO type
2426 *
2427 * @return SET or RESET
2428 *
2429 *******************************************************************************/
GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin)2430 BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
2431 {
2432 uint32_t tmpVal = 0;
2433
2434 if (gpioPin < 32) {
2435 /* GPIO0 ~ GPIO31 */
2436 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_STAT1);
2437 }
2438
2439 return (tmpVal & (1 << gpioPin)) ? SET : RESET;
2440 }
2441
2442 /****************************************************************************/ /**
2443 * @brief Clear GLB GPIO interrrupt status
2444 *
2445 * @param gpioPin: GPIO type
2446 *
2447 * @return SUCCESS or ERROR
2448 *
2449 *******************************************************************************/
GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin)2450 BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
2451 {
2452 uint32_t tmpVal;
2453
2454 if (gpioPin < 32) {
2455 /* GPIO0 ~ GPIO31 */
2456 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1);
2457 tmpVal = tmpVal | (1 << gpioPin);
2458 BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal);
2459 }
2460
2461 return SUCCESS;
2462 }
2463
2464 /****************************************************************************/ /**
2465 * @brief Set GLB GPIO interrupt mode
2466 *
2467 * @param gpioPin: GPIO type
2468 * @param intCtlMod: GPIO interrupt control mode
2469 * @param intTrgMod: GPIO interrupt trigger mode
2470 *
2471 * @return SUCCESS or ERROR
2472 *
2473 *******************************************************************************/
GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin,GLB_GPIO_INT_CONTROL_Type intCtlMod,GLB_GPIO_INT_TRIG_Type intTrgMod)2474 BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, GLB_GPIO_INT_TRIG_Type intTrgMod)
2475 {
2476 uint32_t tmpVal;
2477 uint32_t tmpGpioPin;
2478
2479 CHECK_PARAM(IS_GLB_GPIO_INT_CONTROL_TYPE(intCtlMod));
2480 CHECK_PARAM(IS_GLB_GPIO_INT_TRIG_TYPE(intTrgMod));
2481
2482 if (gpioPin < GLB_GPIO_PIN_10) {
2483 /* GPIO0 ~ GPIO9 */
2484 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1);
2485 tmpGpioPin = gpioPin;
2486 tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
2487 BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1, tmpVal);
2488 } else if (gpioPin < GLB_GPIO_PIN_20) {
2489 /* GPIO10 ~ GPIO19 */
2490 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2);
2491 tmpGpioPin = gpioPin - GLB_GPIO_PIN_10;
2492 tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
2493 BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2, tmpVal);
2494 } else {
2495 /* GPIO20 ~ GPIO29 */
2496 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3);
2497 tmpGpioPin = gpioPin - GLB_GPIO_PIN_20;
2498 tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
2499 BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3, tmpVal);
2500 }
2501
2502 return SUCCESS;
2503 }
2504
2505 /****************************************************************************/ /**
2506 * @brief get GPIO interrupt control mode
2507 *
2508 * @param gpioPin: GPIO pin type
2509 *
2510 * @return SUCCESS or ERROR
2511 *
2512 *******************************************************************************/
GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin)2513 GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin)
2514 {
2515 uint32_t tmpVal;
2516 uint32_t bitVal;
2517
2518 if (gpioPin < GLB_GPIO_PIN_10) {
2519 /* GPIO0 - GPIO9 */
2520 bitVal = gpioPin - 0;
2521 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1);
2522 tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
2523 return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
2524 } else if ((gpioPin > GLB_GPIO_PIN_9) && (gpioPin < GLB_GPIO_PIN_20)) {
2525 /* GPIO10 - GPIO19 */
2526 bitVal = gpioPin - 10;
2527 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2);
2528 tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
2529 return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
2530 } else {
2531 /* GPIO20 - GPIO29 */
2532 bitVal = gpioPin - 20;
2533 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3);
2534 tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
2535 return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
2536 }
2537 }
2538
2539 /****************************************************************************/ /**
2540 * @brief GPIO INT0 IRQHandler install
2541 *
2542 * @param None
2543 *
2544 * @return SUCCESS or ERROR
2545 *
2546 *******************************************************************************/
GLB_GPIO_INT0_IRQHandler_Install(void)2547 BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void)
2548 {
2549 #ifndef BFLB_USE_HAL_DRIVER
2550 Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler);
2551 #endif
2552
2553 return SUCCESS;
2554 }
2555
2556 /****************************************************************************/ /**
2557 * @brief GPIO interrupt IRQ handler callback install
2558 *
2559 * @param gpioPin: GPIO pin type
2560 * @param cbFun: callback function
2561 *
2562 * @return SUCCESS or ERROR
2563 *
2564 *******************************************************************************/
GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin,intCallback_Type * cbFun)2565 BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun)
2566 {
2567 if (gpioPin < 32) {
2568 glbGpioInt0CbfArra[gpioPin] = cbFun;
2569 }
2570
2571 return SUCCESS;
2572 }
2573
2574 /****************************************************************************/ /**
2575 * @brief GPIO interrupt IRQ handler
2576 *
2577 * @param None
2578 *
2579 * @return None
2580 *
2581 *******************************************************************************/
2582 #ifndef BFLB_USE_HAL_DRIVER
GPIO_INT0_IRQHandler(void)2583 void GPIO_INT0_IRQHandler(void)
2584 {
2585 GLB_GPIO_Type gpioPin;
2586 uint32_t timeOut = 0;
2587
2588 for (gpioPin = GLB_GPIO_PIN_0; gpioPin <= GLB_GPIO_PIN_22; gpioPin++) {
2589 if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) {
2590 GLB_GPIO_IntClear(gpioPin, SET);
2591
2592 /* timeout check */
2593 timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
2594
2595 do {
2596 timeOut--;
2597 } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut);
2598
2599 if (!timeOut) {
2600 MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
2601 }
2602
2603 /* if timeOut==0, GPIO interrupt status not cleared */
2604 GLB_GPIO_IntClear(gpioPin, RESET);
2605
2606 if (glbGpioInt0CbfArra[gpioPin] != NULL) {
2607 /* Call the callback function */
2608 glbGpioInt0CbfArra[gpioPin]();
2609 }
2610 }
2611 }
2612 }
2613 #endif
2614
2615 /*@} end of group GLB_Public_Functions */
2616
2617 /*@} end of group GLB */
2618
2619 /*@} end of group BL602_Peripheral_Driver */
2620