1 /**
2 ******************************************************************************
3 * @file bl616_aon.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl616_aon.h"
38 #include "bl616_ef_cfg.h"
39 #include "bl616_ef_ctrl.h"
40 /** @addtogroup BL616_Peripheral_Driver
41 * @{
42 */
43
44 /** @addtogroup AON
45 * @{
46 */
47
48 /** @defgroup AON_Private_Macros
49 * @{
50 */
51 #define AON_CLK_SET_DUMMY_WAIT \
52 { \
53 __NOP(); \
54 __NOP(); \
55 __NOP(); \
56 __NOP(); \
57 __NOP(); \
58 __NOP(); \
59 __NOP(); \
60 __NOP(); \
61 }
62
63 /*@} end of group AON_Private_Macros */
64
65 /** @defgroup AON_Private_Types
66 * @{
67 */
68
69 /*@} end of group AON_Private_Types */
70
71 /** @defgroup AON_Private_Variables
72 * @{
73 */
74
75 /*@} end of group AON_Private_Variables */
76
77 /** @defgroup AON_Global_Variables
78 * @{
79 */
80
81 /*@} end of group AON_Global_Variables */
82
83 /** @defgroup AON_Private_Fun_Declaration
84 * @{
85 */
86
87 /*@} end of group AON_Private_Fun_Declaration */
88
89 /** @defgroup AON_Private_Functions
90 * @{
91 */
92
93 /*@} end of group AON_Private_Functions */
94
95 /** @defgroup AON_Public_Functions
96 * @{
97 */
98
99 /****************************************************************************/ /**
100 * @brief Power on Main band gap
101 *
102 * @param None
103 *
104 * @return SUCCESS or ERROR
105 *
106 *******************************************************************************/
107 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_On_MBG(void)108 BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
109 {
110 uint32_t tmpVal = 0;
111
112 /* Power up RF for PLL to work */
113 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
114 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
115 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
116
117 arch_delay_us(55);
118
119 return SUCCESS;
120 }
121 #endif
122
123 /****************************************************************************/ /**
124 * @brief Power off Main band gap
125 *
126 * @param None
127 *
128 * @return SUCCESS or ERROR
129 *
130 *******************************************************************************/
131 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_Off_MBG(void)132 BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
133 {
134 uint32_t tmpVal = 0;
135
136 /* Power OFF */
137 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
138 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
139 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
140
141 return SUCCESS;
142 }
143 #endif
144
145 /****************************************************************************/ /**
146 * @brief Power on XTAL
147 *
148 * @param None
149 *
150 * @return SUCCESS or ERROR
151 *
152 *******************************************************************************/
153 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_On_XTAL(void)154 BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
155 {
156 uint32_t tmpVal = 0;
157 uint32_t timeOut = 0;
158
159 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
160 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON);
161 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
162 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
163
164 /* Polling for ready */
165 do {
166 arch_delay_us(10);
167 timeOut++;
168 tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
169 } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120);
170
171 if (timeOut >= 120) {
172 return TIMEOUT;
173 }
174
175 return SUCCESS;
176 }
177 #endif
178
179 /****************************************************************************/ /**
180 * @brief Set XTAL cap code
181 *
182 * @param capIn: Cap code in
183 * @param capOut: Cap code out
184 *
185 * @return SUCCESS or ERROR
186 *
187 *******************************************************************************/
188 #ifndef BFLB_USE_ROM_DRIVER
AON_Set_Xtal_CapCode(uint8_t capIn,uint8_t capOut)189 BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
190 {
191 uint32_t tmpVal = 0;
192
193 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
194 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn);
195 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut);
196 BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
197
198 arch_delay_us(100);
199
200 return SUCCESS;
201 }
202 #endif
203
204 /****************************************************************************/ /**
205 * @brief Get XTAL cap code
206 *
207 * @param None
208 *
209 * @return Cap code
210 *
211 *******************************************************************************/
212 #ifndef BFLB_USE_ROM_DRIVER
AON_Get_Xtal_CapCode(void)213 uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
214 {
215 uint32_t tmpVal = 0;
216
217 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
218
219 return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);
220 }
221 #endif
222
223 /****************************************************************************/ /**
224 * @brief Power off XTAL
225 *
226 * @param None
227 *
228 * @return SUCCESS or ERROR
229 *
230 *******************************************************************************/
231 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_Off_XTAL(void)232 BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
233 {
234 uint32_t tmpVal = 0;
235
236 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
237 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON);
238 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
239 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
240
241 return SUCCESS;
242 }
243 #endif
244
245 /****************************************************************************/ /**
246 * @brief Power on bandgap system
247 *
248 * @param None
249 *
250 * @return SUCCESS or ERROR
251 *
252 *******************************************************************************/
253 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_On_BG(void)254 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
255 {
256 uint32_t tmpVal = 0;
257
258 /* power up RF for PLL to work */
259 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
260 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
261 BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
262
263 arch_delay_us(55);
264
265 return SUCCESS;
266 }
267 #endif
268
269 /****************************************************************************/ /**
270 * @brief Power off bandgap system
271 *
272 * @param None
273 *
274 * @return SUCCESS or ERROR
275 *
276 *******************************************************************************/
277 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_Off_BG(void)278 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
279 {
280 uint32_t tmpVal = 0;
281
282 /* power up RF for PLL to work */
283 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
284 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
285 BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
286
287 arch_delay_us(55);
288
289 return SUCCESS;
290 }
291 #endif
292
293 /****************************************************************************/ /**
294 * @brief Power on LDO15_RF
295 *
296 * @param None
297 *
298 * @return SUCCESS or ERROR
299 *
300 *******************************************************************************/
301 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_On_LDO15_RF(void)302 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
303 {
304 uint32_t tmpVal = 0;
305
306 /* ldo15rf power on */
307 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
308 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
309 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
310
311 arch_delay_us(90);
312
313 return SUCCESS;
314 }
315 #endif
316
317 /****************************************************************************/ /**
318 * @brief Power off LDO15_RF
319 *
320 * @param None
321 *
322 * @return SUCCESS or ERROR
323 *
324 *******************************************************************************/
325 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_Off_LDO15_RF(void)326 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
327 {
328 uint32_t tmpVal = 0;
329
330 /* ldo15rf power off */
331 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
332 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
333 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
334
335 return SUCCESS;
336 }
337 #endif
338
339 /****************************************************************************/ /**
340 * @brief LDO15_RF Output Float
341 *
342 * @param None
343 *
344 * @return SUCCESS or ERROR
345 *
346 *******************************************************************************/
AON_Output_Float_LDO15_RF(void)347 BL_Err_Type ATTR_TCM_SECTION AON_Output_Float_LDO15_RF(void)
348 {
349 uint32_t tmpVal=0;
350
351 /* ldo15rf pulldown select by aon */
352 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
353 tmpVal = BL_SET_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_SEL_AON);
354 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
355
356 /* ldo15rf float output */
357 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
358 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_AON);
359 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
360
361 return SUCCESS;
362 }
363
364 /****************************************************************************/ /**
365 * @brief LDO15_RF Pulldown Output to Groud
366 *
367 * @param None
368 *
369 * @return SUCCESS or ERROR
370 *
371 *******************************************************************************/
AON_Output_Pulldown_LDO15_RF(void)372 BL_Err_Type ATTR_TCM_SECTION AON_Output_Pulldown_LDO15_RF(void)
373 {
374 uint32_t tmpVal=0;
375
376 /* ldo15rf pulldown select by aon */
377 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
378 tmpVal = BL_SET_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_SEL_AON);
379 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
380
381 /* ldo15rf pulldown output to ground */
382 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
383 tmpVal = BL_SET_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_AON);
384 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
385
386 return SUCCESS;
387 }
388
389 /****************************************************************************/ /**
390 * @brief LDO15_RF Output Pulldown Controlled by PD Signal
391 *
392 * @param None
393 *
394 * @return SUCCESS or ERROR
395 *
396 *******************************************************************************/
AON_Output_LDO15_RF_Ctrl_by_Pd(void)397 BL_Err_Type ATTR_TCM_SECTION AON_Output_LDO15_RF_Ctrl_by_Pd(void)
398 {
399 uint32_t tmpVal=0;
400
401 /* output ldo15rf pulldown select by pd signal */
402 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
403 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_SEL_AON);
404 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
405
406 return SUCCESS;
407 }
408
409
410 /****************************************************************************/ /**
411 * @brief power on source follow regular
412 *
413 * @param None
414 *
415 * @return SUCCESS or ERROR
416 *
417 *******************************************************************************/
418 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_On_SFReg(void)419 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
420 {
421 uint32_t tmpVal = 0;
422
423 /* power on sfreg */
424 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
425 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
426 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
427
428 arch_delay_us(10);
429
430 return SUCCESS;
431 }
432 #endif
433
434 /****************************************************************************/ /**
435 * @brief power off source follow regular
436 *
437 * @param None
438 *
439 * @return SUCCESS or ERROR
440 *
441 *******************************************************************************/
442 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_Off_SFReg(void)443 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
444 {
445 uint32_t tmpVal = 0;
446
447 /* power off sfreg */
448 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
449 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
450 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
451
452 return SUCCESS;
453 }
454 #endif
455
456 /****************************************************************************/ /**
457 * @brief power on mic bias
458 *
459 * @param None
460 *
461 * @return SUCCESS or ERROR
462 *
463 *******************************************************************************/
AON_Power_On_MicBias(void)464 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_MicBias(void)
465 {
466 uint32_t tmpVal = 0;
467
468 /* power on sfreg */
469 tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
470 tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN);
471 BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
472
473 arch_delay_us(10);
474
475 return SUCCESS;
476 }
477
478 /****************************************************************************/ /**
479 * @brief power off mic bias
480 *
481 * @param None
482 *
483 * @return SUCCESS or ERROR
484 *
485 *******************************************************************************/
AON_Power_Off_MicBias(void)486 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_MicBias(void)
487 {
488 uint32_t tmpVal = 0;
489
490 /* power off sfreg */
491 tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
492 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN);
493 BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
494
495 return SUCCESS;
496 }
497
498 /****************************************************************************/ /**
499 * @brief Power off the power can be shut down in PDS0
500 *
501 * @param None
502 *
503 * @return SUCCESS or ERROR
504 *
505 *******************************************************************************/
AON_LowPower_Enter_PDS0(void)506 BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
507 {
508 uint32_t tmpVal = 0;
509
510 /* power off sfreg */
511 tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
512 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
513 BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
514
515 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
516 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
517 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
518 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
519 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
520
521 /* gating Clock */
522 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
523 tmpVal = tmpVal & (~(1 << 6));
524 tmpVal = tmpVal & (~(1 << 7));
525 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
526
527 return SUCCESS;
528 }
529
530 /****************************************************************************/ /**
531 * @brief Power on the power powered down in PDS0
532 *
533 * @param None
534 *
535 * @return SUCCESS or ERROR
536 *
537 *******************************************************************************/
AON_LowPower_Exit_PDS0(void)538 BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
539 {
540 uint32_t tmpVal = 0;
541
542 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
543
544 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
545 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
546
547 arch_delay_us(20);
548
549 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
550 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
551
552 arch_delay_us(60);
553
554 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
555 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
556
557 arch_delay_us(20);
558
559 /* power on wb */
560 tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
561 tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
562 BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
563
564 /* ungating Clock */
565 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
566 tmpVal = tmpVal | ((1 << 6));
567 tmpVal = tmpVal | ((1 << 7));
568 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
569
570 return SUCCESS;
571 }
572
573 /****************************************************************************/ /**
574 * @brief trim DCDC dis
575 *
576 * @param None
577 *
578 * @return SUCCESS or ERROR
579 *
580 *******************************************************************************/
581 #ifndef BFLB_USE_ROM_DRIVER
AON_Trim_DcdcDis(void)582 BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcDis(void)
583 {
584 Efuse_Ana_DcdcDis_Type trim;
585 int32_t tmpVal = 0;
586
587 EF_Ctrl_Read_DcdcDis_Trim(&trim);
588 if (trim.dcdcDisAonEn) {
589 if (trim.dcdcDisAonParity == EF_Ctrl_Get_Trim_Parity(trim.dcdcDisAon, 1)) {
590 tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0);
591 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC_DIS_AON, trim.dcdcDisAon);
592 BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal);
593 return SUCCESS;
594 }
595 }
596
597 return ERROR;
598 }
599 #endif
600
601 /****************************************************************************/ /**
602 * @brief trim DCDC vout sel
603 *
604 * @param None
605 *
606 * @return SUCCESS or ERROR
607 *
608 *******************************************************************************/
609 #ifndef BFLB_USE_ROM_DRIVER
AON_Trim_DcdcVoutSel(void)610 BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcVoutSel(void)
611 {
612 Efuse_Ana_DcdcVoutSel_Type trim;
613 int32_t tmpVal = 0;
614
615 EF_Ctrl_Read_DcdcVoutSel_Trim(&trim);
616 if (trim.dcdcVoutSelAonEn) {
617 if (trim.dcdcVoutSelAonParity == EF_Ctrl_Get_Trim_Parity(trim.dcdcVoutSelAon, 5)) {
618 tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0);
619 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC_VOUT_SEL_AON, trim.dcdcVoutSelAon);
620 BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal);
621 return SUCCESS;
622 }
623 }
624
625 return ERROR;
626 }
627 #endif
628
629 /****************************************************************************/ /**
630 * @brief trim DCDC vout trim
631 *
632 * @param None
633 *
634 * @return SUCCESS or ERROR
635 *
636 *******************************************************************************/
637 #ifndef BFLB_USE_ROM_DRIVER
AON_Trim_DcdcVoutTrim(void)638 BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcVoutTrim(void)
639 {
640 Efuse_Ana_DcdcVoutTrim_Type trim;
641 int32_t tmpVal = 0;
642
643 EF_Ctrl_Read_DcdcVoutTrim_Trim(&trim);
644 if (trim.dcdcVoutTrimAonEn) {
645 if (trim.dcdcVoutTrimAonParity == EF_Ctrl_Get_Trim_Parity(trim.dcdcVoutTrimAon, 4)) {
646 tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_2);
647 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC_VOUT_TRIM_AON, trim.dcdcVoutTrimAon);
648 BL_WR_REG(AON_BASE, AON_DCDC_TOP_2, tmpVal);
649 return SUCCESS;
650 }
651 }
652
653 return ERROR;
654 }
655 #endif
656
657 /****************************************************************************/ /**
658 * @brief trim LDO11SOC vout
659 *
660 * @param None
661 *
662 * @return SUCCESS or ERROR
663 *
664 *******************************************************************************/
665 #ifndef BFLB_USE_ROM_DRIVER
AON_Trim_Ldo11socVoutTrim(void)666 BL_Err_Type ATTR_TCM_SECTION AON_Trim_Ldo11socVoutTrim(void)
667 {
668 Efuse_Ana_Ldo11socVoutTrim_Type trim;
669 int32_t tmpVal = 0;
670
671 EF_Ctrl_Read_Ldo11socVoutTrim_Trim(&trim);
672 if (trim.ldo11socVoutTrimAonEn) {
673 if (trim.ldo11socVoutTrimAonTrim == EF_Ctrl_Get_Trim_Parity(trim.ldo11socVoutTrimAon, 4)) {
674 tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
675 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_VOUT_TRIM_AON, trim.ldo11socVoutTrimAon);
676 BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
677 return SUCCESS;
678 }
679 }
680
681 return ERROR;
682 }
683 #endif
684
685 /****************************************************************************/ /**
686 * @brief trim USB20 rcal code
687 *
688 * @param None
689 *
690 * @return SUCCESS or ERROR
691 *
692 *******************************************************************************/
693 #ifndef BFLB_USE_ROM_DRIVER
AON_Trim_Usb20RcalCode(void)694 BL_Err_Type ATTR_TCM_SECTION AON_Trim_Usb20RcalCode(void)
695 {
696 Efuse_Ana_Usb20RcalCode_Type trim;
697 int32_t tmpVal = 0;
698
699 EF_Ctrl_Read_Usb20RcalCode_Trim(&trim);
700 if (trim.usb20RcalCodeAonEn) {
701 if (trim.usb20RcalCodeAonParity == EF_Ctrl_Get_Trim_Parity(trim.usb20RcalCodeAon, 6)) {
702 tmpVal = BL_RD_REG(AON_BASE, AON_PSW_MISC);
703 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_USB20_RCAL_CODE_AON, trim.usb20RcalCodeAon);
704 BL_WR_REG(AON_BASE, AON_PSW_MISC, tmpVal);
705 return SUCCESS;
706 }
707 }
708
709 return ERROR;
710 }
711 #endif
712
713 /*@} end of group AON_Public_Functions */
714
715 /*@} end of group AON */
716
717 /*@} end of group BL616_Peripheral_Driver */
718