1 /**
2 ******************************************************************************
3 * @file bl616_clock.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl616_clock.h"
38
39 /** @addtogroup BL616_Peripheral_Driver
40 * @{
41 */
42
43 /** @addtogroup CLOCK
44 * @{
45 */
46
47 /** @defgroup CLOCK_Private_Macros
48 * @{
49 */
50
51 /*@} end of group CLOCK_Private_Macros */
52
53 /** @defgroup CLOCK_Private_Types
54 * @{
55 */
56
57 /*@} end of group CLOCK_Private_Types */
58
59 /** @defgroup CLOCK_Private_Variables
60 * @{
61 */
62
63 /*@} end of group CLOCK_Private_Variables */
64
65 /** @defgroup CLOCK_Global_Variables
66 * @{
67 */
68
69 /*@} end of group CLOCK_Global_Variables */
70
71 /** @defgroup CLOCK_Private_Fun_Declaration
72 * @{
73 */
74
75 /*@} end of group CLOCK_Private_Fun_Declaration */
76
77 /** @defgroup CLOCK_Private_Functions
78 * @{
79 */
80
81 /*@} end of group CLOCK_Private_Functions */
82
83 /** @defgroup CLOCK_Public_Functions
84 * @{
85 */
86
Clock_Get_WIFI_PLL_Output(uint32_t pllOut)87 static inline uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t pllOut)
88 {
89 return pllOut;
90 }
91
Clock_Get_AUPLL_Output(CLOCK_AUPLL_Type clockAupllType)92 static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL_Type clockAupllType)
93 {
94 uint8_t xtalType = 0;
95 uint32_t tmpVal = 0;
96 uint32_t vcoFreq = 0;
97 uint32_t calculationDiv = (1 << 11);
98
99 tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG6), CCI_AUPLL_SDMIN);
100
101 if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
102 switch (xtalType) {
103 /* Calculation method:xtal_freq * 1000 * aupll_sdmin / calculationDiv * 1000 / cpupll_refdiv_ratio */
104 case GLB_XTAL_NONE:
105 return (0);
106 case GLB_XTAL_24M:
107 /* 491519500;451576000;399996000;3840000000 */
108 vcoFreq = 24 * 1000 * tmpVal / calculationDiv * (1000 / 2);
109 break;
110 case GLB_XTAL_32M:
111 /* 491519500;451578000;400000000;3840000000 */
112 vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
113 break;
114 case GLB_XTAL_38P4M:
115 /* 491517000;451579500;399998250;3840000000 */
116 vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4);
117 break;
118 case GLB_XTAL_40M:
119 /* 491518500;451577000;400000000;383999000 */
120 vcoFreq = 40 * 1000 * tmpVal / calculationDiv * (1000 / 4);
121 break;
122 case GLB_XTAL_26M:
123 /* 491518000;451578500;399997500;383995000 */
124 vcoFreq = 26 * 1000 * tmpVal / calculationDiv * (1000 / 2);
125 break;
126 case GLB_XTAL_RC32M:
127 /* 491519500;451578000;400000000;3840000000 */
128 vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
129 break;
130 default:
131 return (0);
132 }
133 } else {
134 return (0);
135 }
136
137 if ((vcoFreq >= 491000000) && (vcoFreq <= 492000000)) {
138 /* vcoFreq:491517000~491519500 */
139 vcoFreq = 491520000;
140 } else if ((vcoFreq >= 451000000) && (vcoFreq <= 452000000)) {
141 /* vcoFreq:451577000~451579500 */
142 vcoFreq = 451580000;
143 } else if ((vcoFreq >= 399000000) && (vcoFreq <= 401000000)) {
144 /* vcoFreq:451577000~451579500 */
145 vcoFreq = 400000000;
146 } else if ((vcoFreq >= 383000000) && (vcoFreq <= 385000000)) {
147 /* vcoFreq:383995000~3840000000 */
148 vcoFreq = 384000000;
149 } else {
150 return (0);
151 }
152
153 switch (clockAupllType) {
154 case CLOCK_AUPLL_DIV1:
155 return (vcoFreq);
156 case CLOCK_AUPLL_DIV2:
157 return (vcoFreq / 2);
158 case CLOCK_AUPLL_DIV2P5:
159 return (vcoFreq * 2 / 5);
160 case CLOCK_AUPLL_DIV3:
161 return (vcoFreq / 3);
162 case CLOCK_AUPLL_DIV4:
163 return (vcoFreq / 4);
164 case CLOCK_AUPLL_DIV5:
165 return (vcoFreq / 5);
166 case CLOCK_AUPLL_DIV6:
167 return (vcoFreq / 6);
168 case CLOCK_AUPLL_DIV10:
169 return (vcoFreq / 10);
170 case CLOCK_AUPLL_DIV15:
171 return (vcoFreq / 15);
172 default:
173 return 0;
174 }
175 }
176
Clock_Get_Audio_PLL_Output()177 static inline uint32_t ATTR_CLOCK_SECTION Clock_Get_Audio_PLL_Output()
178 {
179 uint32_t tmpVal = 0;
180
181 tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG1), CCI_AUPLL_POSTDIV);
182
183 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1) / tmpVal;
184 }
185
Clock_Xtal_Output(void)186 static inline uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void)
187 {
188 uint8_t xtalType = 0;
189
190 if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
191 switch (xtalType) {
192 case GLB_XTAL_NONE:
193 return 0;
194 case GLB_XTAL_24M:
195 return 24 * 1000 * 1000;
196 case GLB_XTAL_32M:
197 return 32 * 1000 * 1000;
198 case GLB_XTAL_38P4M:
199 return 38.4 * 1000 * 1000;
200 case GLB_XTAL_40M:
201 return 40 * 1000 * 1000;
202 case GLB_XTAL_26M:
203 return 26 * 1000 * 1000;
204 case GLB_XTAL_RC32M:
205 return 32 * 1000 * 1000;
206 default:
207 return 0;
208 }
209 } else {
210 return 40 * 1000 * 1000;
211 }
212 }
213
Clock_XClk_Mux_Output(uint8_t sel)214 static inline uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel)
215 {
216 if (sel == 0) {
217 /* rc32m */
218 return (32 * 1000 * 1000);
219 } else if (sel == 1) {
220 /* xtal */
221 return Clock_Xtal_Output();
222 } else {
223 return 0;
224 }
225 }
226
Clock_F32k_Mux_Output(uint8_t sel)227 static inline uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel)
228 {
229 uint32_t tmpVal;
230 uint32_t div = 0;
231
232 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
233 div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV);
234
235 if (sel == 0) {
236 /* src32k */
237 return (32 * 1000);
238 } else if (sel == 1) {
239 /* xtal 32K */
240 return (32 * 1000);
241 } else {
242 return Clock_Xtal_Output() / (div + 1);
243 }
244 }
245
Clock_Get_F32k_Sel_Val(void)246 static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void)
247 {
248 uint32_t tmpVal;
249
250 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
251
252 return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL);
253 }
254
Clock_160M_Clk_Mux_Output(uint8_t sel)255 static inline uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t sel)
256 {
257 if (sel == 0) {
258 /* wifi pll 160m */
259 return Clock_Get_WIFI_PLL_Output(160 * 1000 * 1000);
260 } else if (sel == 1) {
261 /* aupll div3 clk */
262 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV3);
263 } else if (sel == 2) {
264 /* aupll div2 clk */
265 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV2);
266 } else if (sel == 3) {
267 //* aupll div2p5 clk */
268 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV2P5);
269 } else {
270 return 0;
271 }
272 }
273
Clock_Get_Muxpll_160M_Sel_Val(void)274 static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void)
275 {
276 uint32_t tmpVal;
277
278 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
279
280 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL);
281 }
282
Clock_80M_Clk_Mux_Output(uint8_t sel)283 static inline uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t sel)
284 {
285 if (sel == 0) {
286 /* wifi pll 80m */
287 return Clock_Get_WIFI_PLL_Output(80 * 1000 * 1000);
288 } else if (sel == 1) {
289 /* aupll div5 clk */
290 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5);
291 } else if (sel == 2) {
292 /* aupll div6 clk */
293 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV6);
294 } else {
295 return 0;
296 }
297 }
298
Clock_Get_Muxpll_80M_Sel_Val(void)299 static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void)
300 {
301 uint32_t tmpVal;
302
303 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
304
305 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL);
306 }
307
Clock_MCU_Clk_Mux_Output(uint8_t sel)308 static inline uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel)
309 {
310 if (sel == 0) {
311 /* aupll div2 clk */
312 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV2);
313 } else if (sel == 1) {
314 /* aupll div1 clk */
315 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1);
316 } else if (sel == 2) {
317 /* wifi pll 240m */
318 return Clock_Get_WIFI_PLL_Output(240 * 1000 * 1000);
319 } else if (sel == 3) {
320 /* wifi pll 320m */
321 return Clock_Get_WIFI_PLL_Output(320 * 1000 * 1000);
322 } else {
323 return 0;
324 }
325 }
326
Clock_Get_MCU_XClk_Sel_Val(void)327 static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void)
328 {
329 uint32_t tmpVal;
330
331 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
332 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
333
334 return (tmpVal & 0x1);
335 }
336
Clock_Get_MCU_Root_Clk_Sel_Val(void)337 static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void)
338 {
339 uint32_t tmpVal;
340
341 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
342 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
343
344 return ((tmpVal >> 1) & 0x1);
345 }
346
Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)347 static inline uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)
348 {
349 uint32_t tmpVal;
350
351 if (sel == 0) {
352 /* xclk */
353 return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());
354 } else if (sel == 1) {
355 /* pll */
356 tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);
357 sel = BL_GET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL);
358 return Clock_MCU_Clk_Mux_Output(sel);
359 } else {
360 return 0;
361 }
362 }
363
Clock_Get_MCU_HClk_Div_Val(void)364 static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void)
365 {
366 uint32_t tmpVal;
367
368 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
369
370 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
371 }
372
Clock_Get_Peri_BClk_Div_Val(void)373 static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void)
374 {
375 uint32_t tmpVal;
376
377 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
378
379 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
380 }
381
382 /****************************************************************************/ /**
383 * @brief Get System Clock
384 *
385 * @param type: System clock type
386 *
387 * @return System clock value
388 *
389 *******************************************************************************/
Clock_System_Clock_Get(BL_System_Clock_Type type)390 uint32_t ATTR_CLOCK_SECTION Clock_System_Clock_Get(BL_System_Clock_Type type)
391 {
392 uint32_t clock = 0;
393 uint32_t div = 0;
394
395 switch (type) {
396 case BL_SYSTEM_CLOCK_MCU_ROOT_CLK:
397 /*!< mcu root clock */
398 return Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());
399
400 case BL_SYSTEM_CLOCK_MCU_CLK:
401 /*!< mcu fast clock/cpu clock */
402 clock = Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());
403 div = Clock_Get_MCU_HClk_Div_Val();
404 return clock / (div + 1);
405
406 case BL_SYSTEM_CLOCK_MCU_PBCLK:
407 /*!< mcu peri bus clock */
408 clock = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
409 div = Clock_Get_Peri_BClk_Div_Val();
410 return clock / (div + 1);
411
412 case BL_SYSTEM_CLOCK_F32K:
413 /*!< f32k clock */
414 return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
415
416 case BL_SYSTEM_CLOCK_XCLK:
417 /*!< xclk:rc32M or xtal */
418 return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());
419
420 case BL_SYSTEM_CLOCK_XTAL:
421 /*!< xtal clock */
422 return Clock_Xtal_Output();
423
424 default:
425 return 0;
426 }
427 }
428
Clock_PARAMB_Clk_Mux_Output(uint8_t sel)429 static inline uint32_t Clock_PARAMB_Clk_Mux_Output(uint8_t sel)
430 {
431 if (sel == 0) {
432 /* wifi pll 320m */
433 return Clock_Get_WIFI_PLL_Output(320 * 1000 * 1000);
434 } else if (sel == 1) {
435 /* aupll div1 clk */
436 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1);
437 } else {
438 return 0;
439 }
440 }
441
Clock_Get_PSRAMB_Clk_Div_Val(void)442 static inline uint8_t Clock_Get_PSRAMB_Clk_Div_Val(void)
443 {
444 uint32_t tmpVal;
445
446 tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
447
448 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV);
449 }
450
Clock_Get_PSRAMB_Clk_Sel_Val(void)451 static inline uint8_t Clock_Get_PSRAMB_Clk_Sel_Val(void)
452 {
453 uint32_t tmpVal;
454
455 tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
456
457 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL);
458 }
459
Clock_Get_PSRAMB_Clk(void)460 uint32_t Clock_Get_PSRAMB_Clk(void)
461 {
462 uint32_t div = 0;
463
464 div = Clock_Get_PSRAMB_Clk_Div_Val();
465
466 return Clock_PARAMB_Clk_Mux_Output(Clock_Get_PSRAMB_Clk_Sel_Val()) / (div + 1);
467 }
468
Clock_ISP_Clk_Mux_Output(uint8_t sel)469 static inline uint32_t Clock_ISP_Clk_Mux_Output(uint8_t sel)
470 {
471 if (sel == 0) {
472 /* wifi pll 80m */
473 return Clock_Get_WIFI_PLL_Output(80 * 1000 * 1000);
474 } else if (sel == 1) {
475 /* aupll div5 clk */
476 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5);
477 } else if (sel == 2 || sel == 3) {
478 /* aupll div6 clk */
479 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV6);
480 } else {
481 return 0;
482 }
483 }
484
Clock_Get_ISP_Clk_Sel_Val(void)485 static inline uint8_t Clock_Get_ISP_Clk_Sel_Val(void)
486 {
487 uint32_t tmpVal;
488
489 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
490
491 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_ISP_MUXPLL_80M_SEL);
492 }
493
Clock_Get_ISP_Clk(void)494 uint32_t Clock_Get_ISP_Clk(void)
495 {
496 return Clock_ISP_Clk_Mux_Output(Clock_Get_ISP_Clk_Sel_Val());
497 }
498
Clock_UART_Clk_Mux_Output(uint8_t sel)499 static inline uint32_t Clock_UART_Clk_Mux_Output(uint8_t sel)
500 {
501 if (sel == 0) {
502 /* mcu bclk */
503 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
504 } else if (sel == 1) {
505 /* mux 160Mkz */
506 return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());
507 } else {
508 /* xclk */
509 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
510 }
511 }
512
Clock_Get_UART_Clk_Sel_Val(void)513 static inline uint8_t Clock_Get_UART_Clk_Sel_Val(void)
514 {
515 uint32_t tmpVal;
516
517 tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
518
519 return ((BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL2) << 1) | BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL));
520 }
521
Clock_Get_UART_Div_Val(void)522 static inline uint8_t Clock_Get_UART_Div_Val(void)
523 {
524 uint32_t tmpVal;
525
526 tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
527
528 return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV);
529 }
530
Clock_PKA_Clk_Mux_Output(uint8_t sel)531 static inline uint32_t Clock_PKA_Clk_Mux_Output(uint8_t sel)
532 {
533 if (sel == 0) {
534 /* mcu pbclk */
535 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
536 } else if (sel == 1) {
537 /* mux 160m */
538 return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());
539 } else {
540 return 0;
541 }
542 }
543
Clock_Get_PKA_Clk_Sel_Val(void)544 static inline uint8_t Clock_Get_PKA_Clk_Sel_Val(void)
545 {
546 uint32_t tmpVal;
547
548 tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
549
550 return BL_GET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL);
551 }
552
Clock_IR_Clk_Mux_Output(void)553 static inline uint32_t Clock_IR_Clk_Mux_Output(void)
554 {
555 /* xclk */
556 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
557 }
558
Clock_Get_IR_Div_Val(void)559 static inline uint8_t Clock_Get_IR_Div_Val(void)
560 {
561 uint32_t tmpVal;
562
563 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);
564
565 return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV);
566 }
567
Clock_Get_SF_Clk_Sel2_Val(void)568 static inline uint8_t Clock_Get_SF_Clk_Sel2_Val(void)
569 {
570 uint32_t tmpVal;
571
572 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
573
574 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2);
575 }
576
Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)577 static inline uint32_t Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)
578 {
579 if (sel == 0) {
580 /* wifi pll 120m */
581 return Clock_Get_WIFI_PLL_Output(120 * 1000 * 1000);
582 } else if (sel == 1) {
583 /* xtal */
584 return Clock_Xtal_Output();
585 } else if (sel == 2) {
586 /* wifi pll 120m */
587 return Clock_Get_WIFI_PLL_Output(120 * 1000 * 1000);
588 } else {
589 /* aupll div5 clk */
590 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5);
591 }
592 }
593
Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)594 static inline uint32_t Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)
595 {
596 if (sel == 0) {
597 /* sf sel2 */
598 return Clock_SF_SEL2_Clk_Mux_Output(Clock_Get_SF_Clk_Sel2_Val());
599 } else if (sel == 1) {
600 /* mux 80m */
601 return Clock_80M_Clk_Mux_Output(Clock_Get_Muxpll_80M_Sel_Val());
602 } else if (sel == 2) {
603 /* mcu pbclk */
604 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
605 } else {
606 /* wifi 96m */
607 return Clock_Get_WIFI_PLL_Output(96 * 1000 * 1000);
608 }
609 }
610
Clock_Get_SF_Clk_Sel_Val(void)611 static inline uint8_t Clock_Get_SF_Clk_Sel_Val(void)
612 {
613 uint32_t tmpVal;
614
615 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
616
617 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL);
618 }
619
Clock_Get_SF_Div_Val(void)620 static inline uint8_t Clock_Get_SF_Div_Val(void)
621 {
622 uint32_t tmpVal;
623
624 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
625
626 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV);
627 }
628
Clock_SPI_Clk_Mux_Output(uint8_t sel)629 static inline uint32_t Clock_SPI_Clk_Mux_Output(uint8_t sel)
630 {
631 if (sel == 0) {
632 /* mux 160Mkz */
633 return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());
634 } else {
635 /* xclk */
636 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
637 }
638 }
639
Clock_Get_SPI_Clk_Sel_Val(void)640 static inline uint8_t Clock_Get_SPI_Clk_Sel_Val(void)
641 {
642 uint32_t tmpVal;
643
644 tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
645
646 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL);
647 }
648
Clock_Get_SPI_Div_Val(void)649 static inline uint8_t Clock_Get_SPI_Div_Val(void)
650 {
651 uint32_t tmpVal;
652
653 tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
654
655 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);
656 }
657
Clock_DBI_Clk_Mux_Output(uint8_t sel)658 static inline uint32_t Clock_DBI_Clk_Mux_Output(uint8_t sel)
659 {
660 if (sel == 0) {
661 /* mux 160Mkz */
662 return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());
663 } else {
664 /* xclk */
665 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
666 }
667 }
668
Clock_Get_DBI_Clk_Sel_Val(void)669 static inline uint8_t Clock_Get_DBI_Clk_Sel_Val(void)
670 {
671 uint32_t tmpVal;
672
673 tmpVal = BL_RD_REG(GLB_BASE, GLB_DBI_CFG0);
674
675 return BL_GET_REG_BITS_VAL(tmpVal, GLB_DBI_CLK_SEL);
676 }
677
Clock_Get_DBI_Div_Val(void)678 static inline uint8_t Clock_Get_DBI_Div_Val(void)
679 {
680 uint32_t tmpVal;
681
682 tmpVal = BL_RD_REG(GLB_BASE, GLB_DBI_CFG0);
683
684 return BL_GET_REG_BITS_VAL(tmpVal, GLB_DBI_CLK_DIV);
685 }
686
Clock_I2C_Clk_Mux_Output(uint8_t sel)687 static inline uint32_t Clock_I2C_Clk_Mux_Output(uint8_t sel)
688 {
689 if (sel == 0) {
690 /* mcu pblck */
691 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
692 } else if (sel == 1) {
693 /* xclk */
694 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
695 } else {
696 return 0;
697 }
698 }
699
Clock_Get_I2C_Clk_Sel_Val(void)700 static inline uint8_t Clock_Get_I2C_Clk_Sel_Val(void)
701 {
702 uint32_t tmpVal;
703
704 tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
705
706 return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL);
707 }
708
Clock_Get_I2C_Div_Val(void)709 static inline uint8_t Clock_Get_I2C_Div_Val(void)
710 {
711 uint32_t tmpVal;
712
713 tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
714
715 return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);
716 }
717
Clock_GPADC_Clk_Output(uint8_t sel)718 static inline uint32_t Clock_GPADC_Clk_Output(uint8_t sel)
719 {
720 if (sel == 0) {
721 /* audio pll clk */
722 return Clock_Get_Audio_PLL_Output();
723 } else {
724 /* xclk */
725 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
726 }
727 }
728
Clock_Get_GPADC_32M_Clk_Sel_Val(void)729 static inline uint8_t Clock_Get_GPADC_32M_Clk_Sel_Val(void)
730 {
731 uint32_t tmpVal;
732
733 tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
734
735 return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL);
736 }
737
Clock_Get_GPADC_Div_Val(void)738 static inline uint8_t Clock_Get_GPADC_Div_Val(void)
739 {
740 uint32_t tmpVal;
741
742 tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
743
744 return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
745 }
746
Clock_GPADC_Clk_Mux_Output(uint8_t sel)747 static inline uint32_t Clock_GPADC_Clk_Mux_Output(uint8_t sel)
748 {
749 uint32_t div = 0;
750
751 if (sel == 1) {
752 /* f32k bclk */
753 return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
754 } else {
755 div = Clock_Get_GPADC_Div_Val();
756 return Clock_GPADC_Clk_Output(Clock_Get_GPADC_32M_Clk_Sel_Val()) / (div + 1);
757 }
758 }
759
Clock_I2S_Clk_Mux_Output(void)760 static inline uint32_t Clock_I2S_Clk_Mux_Output(void)
761 {
762 /* audio pll clk */
763 return Clock_Get_Audio_PLL_Output();
764 }
765
Clock_Get_I2S_Div_Val(void)766 static inline uint8_t Clock_Get_I2S_Div_Val(void)
767 {
768 uint32_t tmpVal;
769
770 tmpVal = BL_RD_REG(GLB_BASE, GLB_I2S_CFG0);
771
772 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV);
773 }
774
Clock_ADC_Clk_Mux_Output(void)775 static inline uint32_t Clock_ADC_Clk_Mux_Output(void)
776 {
777 /* audio pll clk */
778 return Clock_Get_Audio_PLL_Output();
779 }
780
Clock_Get_ADC_Div_Val(void)781 static inline uint8_t Clock_Get_ADC_Div_Val(void)
782 {
783 uint32_t tmpVal;
784
785 tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);
786
787 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_SOLO_CLK_DIV);
788 }
789
Clock_Get_GPADC_Clk_Sel_Val(void)790 static inline uint8_t Clock_Get_GPADC_Clk_Sel_Val(void)
791 {
792 uint32_t tmpVal;
793
794 tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
795
796 return BL_GET_REG_BITS_VAL(tmpVal, HBN_GPADC_CS);
797 }
798
Clock_GPDAC_Clk_Mux_Output(uint8_t sel)799 static inline uint32_t Clock_GPDAC_Clk_Mux_Output(uint8_t sel)
800 {
801 if (sel == 0) {
802 /* wifi pll 32m */
803 return Clock_Get_WIFI_PLL_Output(32 * 1000 * 1000);
804 } else if (sel == 1) {
805 /* xclk */
806 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
807 } else {
808 /* audio pll clk */
809 return Clock_Get_Audio_PLL_Output();
810 }
811 }
812
Clock_Get_GPDAC_Div_Val(void)813 static inline uint8_t Clock_Get_GPDAC_Div_Val(void)
814 {
815 uint32_t tmpVal;
816
817 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
818
819 return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
820 }
821
Clock_Get_GPDAC_Clk_Sel_Val(void)822 static inline uint8_t Clock_Get_GPDAC_Clk_Sel_Val(void)
823 {
824 uint32_t tmpVal;
825
826 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
827
828 return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL);
829 }
830
Clock_SDH_Clk_Mux_Output(uint8_t sel)831 static inline uint32_t Clock_SDH_Clk_Mux_Output(uint8_t sel)
832 {
833 if (sel == 0) {
834 /* wifi pll 96m */
835 return Clock_Get_WIFI_PLL_Output(96 * 1000 * 1000);
836 } else {
837 /* aupll div5 clk */
838 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5);
839 }
840 }
841
Clock_Get_SDH_Clk_Sel_Val(void)842 static inline uint8_t Clock_Get_SDH_Clk_Sel_Val(void)
843 {
844 uint32_t tmpVal;
845
846 tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
847
848 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL);
849 }
850
Clock_Get_SDH_Div_Val(void)851 static inline uint8_t Clock_Get_SDH_Div_Val(void)
852 {
853 uint32_t tmpVal;
854
855 tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
856
857 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV);
858 }
859
Clock_CAM_Clk_Mux_Output(uint8_t sel)860 static inline uint32_t Clock_CAM_Clk_Mux_Output(uint8_t sel)
861 {
862 if (sel == 0) {
863 /* xclk */
864 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
865 } else if (sel == 1) {
866 /* wifi pull 96m */
867 return Clock_Get_WIFI_PLL_Output(96 * 1000 * 1000);
868 } else if (sel == 2 || sel == 3) {
869 /* aupll div5 clk */
870 return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5);
871 } else {
872 return 0;
873 }
874 }
875
Clock_Get_CAM_Clk_Sel_Val(void)876 static inline uint8_t Clock_Get_CAM_Clk_Sel_Val(void)
877 {
878 uint32_t tmpVal;
879
880 tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
881
882 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL);
883 }
884
Clock_Get_CAM_Div_Val(void)885 static inline uint8_t Clock_Get_CAM_Div_Val(void)
886 {
887 uint32_t tmpVal;
888
889 tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
890
891 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);
892 }
893
894 /****************************************************************************/ /**
895
896 * @brief Get Audio ADC Clock
897 *
898 * @return Audio ADC clock value
899 *
900 *******************************************************************************/
Clock_Audio_ADC_Clock_Get(void)901 uint32_t Clock_Audio_ADC_Clock_Get(void)
902 {
903 uint32_t clock = 0;
904 uint32_t div = 0;
905
906 clock = Clock_ADC_Clk_Mux_Output();
907 div = Clock_Get_ADC_Div_Val();
908
909 return clock / (div + 1);
910 }
911
912 /****************************************************************************/ /**
913
914 * @brief Get Peripheral1 Clock
915 *
916 * @param type: Peripheral1 clock type
917 *
918 * @return Peripheral1 clock value
919 *
920 *******************************************************************************/
Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)921 uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)
922 {
923 uint32_t clock = 0;
924 uint32_t div = 0;
925
926 switch (type) {
927 /*!< uart0 clock */
928 case BL_PERIPHERAL_CLOCK_UART0:
929 ATTR_FALLTHROUGH();
930
931 /*!< uart1 clock */
932 case BL_PERIPHERAL_CLOCK_UART1:
933 ATTR_FALLTHROUGH();
934
935 /*!< uart2 clock */
936 case BL_PERIPHERAL_CLOCK_UART2:
937 clock = Clock_UART_Clk_Mux_Output(Clock_Get_UART_Clk_Sel_Val());
938 div = Clock_Get_UART_Div_Val();
939 return clock / (div + 1);
940
941 /*!< spi clock */
942 case BL_PERIPHERAL_CLOCK_SPI:
943 clock = Clock_SPI_Clk_Mux_Output(Clock_Get_SPI_Clk_Sel_Val());
944 div = Clock_Get_SPI_Div_Val();
945 return clock / (div + 1);
946
947 /*!< dbi clock */
948 case BL_PERIPHERAL_CLOCK_DBI:
949 clock = Clock_DBI_Clk_Mux_Output(Clock_Get_DBI_Clk_Sel_Val());
950 div = Clock_Get_DBI_Div_Val();
951 return clock / (div + 1);
952
953 /*!< i2c0 clock */
954 case BL_PERIPHERAL_CLOCK_I2C0:
955 ATTR_FALLTHROUGH();
956
957 /*!< i2c1 clock */
958 case BL_PERIPHERAL_CLOCK_I2C1:
959 clock = Clock_I2C_Clk_Mux_Output(Clock_Get_I2C_Clk_Sel_Val());
960 div = Clock_Get_I2C_Div_Val();
961 return clock / (div + 1);
962
963 /*!< PSRAMB clock */
964 case BL_PERIPHERAL_CLOCK_PSRAMB:
965 return Clock_Get_PSRAMB_Clk();
966
967 /*!< emi clock */
968 case BL_PERIPHERAL_CLOCK_EMI:
969 /* mcu pblck */
970 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
971
972 /*!< isp clock */
973 case BL_PERIPHERAL_CLOCK_ISP:
974 return Clock_Get_ISP_Clk();
975
976 /*!< FLASH clock */
977 case BL_PERIPHERAL_CLOCK_FLASH:
978 clock = Clock_SF_SEL_Clk_Mux_Output(Clock_Get_SF_Clk_Sel_Val());
979 div = Clock_Get_SF_Div_Val();
980 return clock / (div + 1);
981
982 /*!< I2S clock */
983 case BL_PERIPHERAL_CLOCK_I2S:
984 clock = Clock_I2S_Clk_Mux_Output();
985 div = Clock_Get_I2S_Div_Val();
986 return clock / (div + 1);
987
988 /*!< IR clock */
989 case BL_PERIPHERAL_CLOCK_IR:
990 clock = Clock_IR_Clk_Mux_Output();
991 div = Clock_Get_IR_Div_Val();
992 return clock / (div + 1);
993
994 /*!< ADC clock */
995 case BL_PERIPHERAL_CLOCK_ADC:
996 return Clock_Audio_ADC_Clock_Get();
997
998 /*!< GPADC clock */
999 case BL_PERIPHERAL_CLOCK_GPADC:
1000 return Clock_GPADC_Clk_Mux_Output(Clock_Get_GPADC_Clk_Sel_Val());
1001
1002 /*!< GPDAC clock */
1003 case BL_PERIPHERAL_CLOCK_GPDAC:
1004 clock = Clock_GPDAC_Clk_Mux_Output(Clock_Get_GPDAC_Clk_Sel_Val());
1005 div = Clock_Get_GPDAC_Div_Val();
1006 return clock / (div + 1);
1007
1008 /*!< CAM clock */
1009 case BL_PERIPHERAL_CLOCK_CAM:
1010 clock = Clock_CAM_Clk_Mux_Output(Clock_Get_CAM_Clk_Sel_Val());
1011 div = Clock_Get_CAM_Div_Val();
1012 return clock / (div + 1);
1013
1014 /*!< SDH clock */
1015 case BL_PERIPHERAL_CLOCK_SDH:
1016 clock = Clock_SDH_Clk_Mux_Output(Clock_Get_SDH_Clk_Sel_Val());
1017 div = Clock_Get_SDH_Div_Val();
1018 return clock / (div + 1);
1019
1020 /*!< PKA clock */
1021 case BL_PERIPHERAL_CLOCK_PKA:
1022 return Clock_PKA_Clk_Mux_Output(Clock_Get_PKA_Clk_Sel_Val());
1023
1024 default:
1025 return 0;
1026 }
1027 }
1028
1029 /****************************************************************************/ /**
1030 * @brief get system core clock
1031 *
1032 * @param None
1033 *
1034 * @return system core clock value
1035 *
1036 *******************************************************************************/
SystemCoreClockGet(void)1037 uint32_t ATTR_CLOCK_SECTION SystemCoreClockGet(void)
1038 {
1039 uint32_t clockVal = 0;
1040
1041 switch (GLB_Get_Core_Type()) {
1042 case GLB_CORE_ID_M0:
1043 clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
1044 break;
1045 default:
1046 clockVal = 0;
1047 break;
1048 }
1049 clockVal = clockVal ? clockVal : (32 * 1000 * 1000);
1050
1051 return clockVal;
1052 }
1053
1054 /****************************************************************************/ /**
1055 * @brief mcu rtc reset
1056 *
1057 * @param rstEn: hold reset or not
1058 *
1059 * @return SUCCESS or ERROR
1060 *
1061 *******************************************************************************/
CPU_Set_MTimer_RST(uint8_t rstEn)1062 BL_Err_Type ATTR_CLOCK_SECTION CPU_Set_MTimer_RST(uint8_t rstEn)
1063 {
1064 uint32_t tmpVal = 0;
1065 uint32_t address = 0;
1066
1067 switch (GLB_Get_Core_Type()) {
1068 case GLB_CORE_ID_M0:
1069 address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
1070 break;
1071 default:
1072 address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
1073 break;
1074 }
1075
1076 /* set reset */
1077 /* MCU RTC_RST is [30] */
1078 /* DSP RTC_RST is [30] */
1079 /* LP RTC_RST is [30] */
1080 tmpVal = BL_RD_WORD(address);
1081 if (rstEn) {
1082 tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);
1083 } else {
1084 tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);
1085 }
1086 BL_WR_WORD(address, tmpVal);
1087
1088 return SUCCESS;
1089 }
1090
1091 /****************************************************************************/ /**
1092 * @brief mcu rtc reset
1093 *
1094 * @param None
1095 *
1096 * @return SUCCESS or ERROR
1097 *
1098 *******************************************************************************/
CPU_Reset_MTimer(void)1099 BL_Err_Type ATTR_CLOCK_SECTION CPU_Reset_MTimer(void)
1100 {
1101 CPU_Set_MTimer_RST(1);
1102 CPU_Set_MTimer_RST(0);
1103
1104 return SUCCESS;
1105 }
1106
1107 /****************************************************************************/ /**
1108 * @brief set mcu rtc clock
1109 *
1110 * @param enable: ENABLE or DISABLE
1111 * @param mTimerSourceClockType: Souce Clock Type
1112 * @param div: divider
1113 *
1114 * @return SUCCESS or ERROR
1115 *
1116 *******************************************************************************/
CPU_Set_MTimer_CLK(uint8_t enable,BL_MTimer_Source_Clock_Type mTimerSourceClockType,uint16_t div)1117 BL_Err_Type ATTR_CLOCK_SECTION CPU_Set_MTimer_CLK(uint8_t enable, BL_MTimer_Source_Clock_Type mTimerSourceClockType, uint16_t div)
1118 {
1119 uint32_t tmpVal = 0;
1120 uint32_t address = 0;
1121
1122 CHECK_PARAM((div <= 0x3FF));
1123
1124 address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
1125
1126 /* Set MTimer Source Clock */
1127 tmpVal = BL_RD_WORD(address);
1128 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_CLK_SEL, mTimerSourceClockType);
1129 BL_WR_WORD(address, tmpVal);
1130
1131 /* disable rtc first */
1132 /* MCU RTC_EN is [31] */
1133 /* DSP RTC_EN is [31] */
1134 /* LP RTC_EN is [31] */
1135 tmpVal = BL_RD_WORD(address);
1136 tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);
1137 BL_WR_WORD(address, tmpVal);
1138
1139 /* set div */
1140 /* MCU RTC_DIV is [9:0] */
1141 /* DSP RTC_DIV is [9:0] */
1142 /* LP RTC_DIV is [9:0] */
1143 tmpVal = BL_RD_WORD(address);
1144 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_DIV, div);
1145 BL_WR_WORD(address, tmpVal);
1146
1147 /* enable or not */
1148 /* MCU RTC_EN is [31] */
1149 /* DSP RTC_EN is [31] */
1150 /* LP RTC_EN is [31] */
1151 tmpVal = BL_RD_WORD(address);
1152 if (enable) {
1153 tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);
1154 } else {
1155 tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);
1156 }
1157 BL_WR_WORD(address, tmpVal);
1158
1159 return SUCCESS;
1160 }
1161
1162 /****************************************************************************/ /**
1163 * @brief get cpu rtc source clock
1164 *
1165 * @param None
1166 *
1167 * @return cpu rtc source clock
1168 *
1169 *******************************************************************************/
CPU_Get_MTimer_Source_Clock(void)1170 uint32_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Source_Clock(void)
1171 {
1172 uint32_t coreFreq = 0;
1173 uint32_t tmpVal = 0;
1174
1175 tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);
1176 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_CLK_SEL);
1177
1178 /* get cpu core clock */
1179 switch (GLB_Get_Core_Type()) {
1180 case GLB_CORE_ID_M0:
1181 if (tmpVal == BL_MTIMER_SOURCE_CLOCK_MCU_XCLK) {
1182 coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
1183 } else {
1184 coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
1185 }
1186 break;
1187 default:
1188 coreFreq = 0;
1189 break;
1190 }
1191 coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);
1192
1193 return coreFreq;
1194 }
1195
1196 /****************************************************************************/ /**
1197 * @brief get mcu rtc clock
1198 *
1199 * @param None
1200 *
1201 * @return mcu rtc counter clock
1202 *
1203 *******************************************************************************/
CPU_Get_MTimer_Clock(void)1204 uint32_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Clock(void)
1205 {
1206 uint32_t coreFreq = 0;
1207 uint32_t address = 0;
1208 uint32_t div = 0;
1209 uint32_t tmpVal = 0;
1210
1211 address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
1212
1213 tmpVal = BL_RD_WORD(address);
1214 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_CLK_SEL);
1215
1216 /* get cpu core clock */
1217 /* get mtimer clock div */
1218 switch (GLB_Get_Core_Type()) {
1219 case GLB_CORE_ID_M0:
1220 if (tmpVal == BL_MTIMER_SOURCE_CLOCK_MCU_XCLK) {
1221 coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
1222 } else {
1223 coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
1224 }
1225 break;
1226 default:
1227 coreFreq = 0;
1228 break;
1229 }
1230 /* MCU RTC_DIV is [9:0] */
1231 /* DSP RTC_DIV is [9:0] */
1232 /* LP RTC_DIV is [9:0] */
1233 div = BL_GET_REG_BITS_VAL(BL_RD_WORD(address), MCU_MISC_REG_MCU_RTC_DIV);
1234 div += 1;
1235 coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);
1236 coreFreq = coreFreq / div; /* mtimer clock = cpu clock / mtimer div */
1237
1238 return coreFreq;
1239 }
1240
1241 /****************************************************************************/ /**
1242 * @brief get mcu rtc counter
1243 *
1244 * @param None
1245 *
1246 * @return mcu rtc counter
1247 *
1248 *******************************************************************************/
CPU_Get_MTimer_Counter(void)1249 uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Counter(void)
1250 {
1251 volatile uint64_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1;
1252 uint8_t cnt = 0;
1253
1254 do {
1255 tmpValHigh = (uint64_t)csi_coret_get_valueh();
1256 tmpValLow = (uint64_t)csi_coret_get_value();
1257 tmpValLow1 = (uint64_t)csi_coret_get_value();
1258 tmpValHigh1 = (uint64_t)csi_coret_get_valueh();
1259 cnt++;
1260 if (cnt > 4) {
1261 break;
1262 }
1263 } while (tmpValLow > tmpValLow1 || tmpValHigh != tmpValHigh1);
1264
1265 return (uint64_t)((tmpValHigh1 << 32) + tmpValLow1);
1266 }
1267
1268 /****************************************************************************/ /**
1269 * @brief get mcu cycle
1270 *
1271 * @param None
1272 *
1273 * @return mcu cycle
1274 *
1275 *******************************************************************************/
CPU_Get_CPU_Cycle(void)1276 uint64_t ATTR_CLOCK_SECTION CPU_Get_CPU_Cycle(void)
1277 {
1278 #if (__riscv_xlen == 64)
1279 return (uint64_t)__get_MCYCLE();
1280 #else
1281 volatile uint64_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1;
1282 uint8_t cnt = 0;
1283
1284 do {
1285 tmpValHigh = (uint64_t)__get_MCYCLEH();
1286 tmpValLow = (uint64_t)__get_MCYCLE();
1287 tmpValLow1 = (uint64_t)__get_MCYCLE();
1288 tmpValHigh1 = (uint64_t)__get_MCYCLEH();
1289 cnt++;
1290 if (cnt > 4) {
1291 break;
1292 }
1293 } while (tmpValLow > tmpValLow1 || tmpValHigh != tmpValHigh1);
1294
1295 return (uint64_t)((tmpValHigh1 << 32) + tmpValLow1);
1296 #endif
1297 }
1298
1299 /****************************************************************************/ /**
1300 * @brief get mcu rtc counter in us
1301 *
1302 * @param None
1303 *
1304 * @return mcu rtc counter in us
1305 *
1306 *******************************************************************************/
CPU_Get_MTimer_US(void)1307 uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_US(void)
1308 {
1309 uint32_t clk = CPU_Get_MTimer_Clock();
1310 uint64_t mtimer_counter = CPU_Get_MTimer_Counter();
1311 if (mtimer_counter == 0) {
1312 mtimer_counter = CPU_Get_CPU_Cycle();
1313 clk = SystemCoreClockGet();
1314 }
1315
1316 if (clk < 1000 * 1000) {
1317 return mtimer_counter * 1000 / (clk / 1000);
1318 } else {
1319 return mtimer_counter / (clk / 1000 / 1000);
1320 }
1321 }
1322
1323 /****************************************************************************/ /**
1324 * @brief get mcu rtc counter in ms
1325 *
1326 * @param None
1327 *
1328 * @return mcu rtc counter in ms
1329 *
1330 *******************************************************************************/
CPU_Get_MTimer_MS(void)1331 uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_MS(void)
1332 {
1333 uint32_t clk = CPU_Get_MTimer_Clock();
1334 uint64_t mtimer_counter = CPU_Get_MTimer_Counter();
1335 if (mtimer_counter == 0) {
1336 mtimer_counter = CPU_Get_CPU_Cycle();
1337 clk = SystemCoreClockGet();
1338 }
1339
1340 return mtimer_counter / (clk / 1000);
1341 }
1342
1343 /****************************************************************************/ /**
1344 * @brief mcu timer delay us
1345 *
1346 * @param cnt: us
1347 *
1348 * @return SUCCESS or ERROR
1349 *
1350 *******************************************************************************/
CPU_MTimer_Delay_US(uint32_t cnt)1351 BL_Err_Type ATTR_CLOCK_SECTION CPU_MTimer_Delay_US(uint32_t cnt)
1352 {
1353 volatile uint64_t us1 = 0;
1354 volatile uint64_t us2 = 0;
1355
1356 us1 = CPU_Get_MTimer_US();
1357 do {
1358 us2 = CPU_Get_MTimer_US();
1359 } while (((us2 - us1) < (uint64_t)(cnt)));
1360
1361 return SUCCESS;
1362 }
1363
1364 /****************************************************************************/ /**
1365 * @brief mcu timer delay ms
1366 *
1367 * @param cnt: ms
1368 *
1369 * @return SUCCESS or ERROR
1370 *
1371 *******************************************************************************/
CPU_MTimer_Delay_MS(uint32_t cnt)1372 BL_Err_Type ATTR_CLOCK_SECTION CPU_MTimer_Delay_MS(uint32_t cnt)
1373 {
1374 volatile uint64_t ms1 = 0;
1375 volatile uint64_t ms2 = 0;
1376
1377 ms1 = CPU_Get_MTimer_MS();
1378 do {
1379 ms2 = CPU_Get_MTimer_MS();
1380 } while (((ms2 - ms1) < (uint64_t)(cnt)));
1381
1382 return SUCCESS;
1383 }
1384
1385 /*@} end of group CLOCK_Public_Functions */
1386
1387 /*@} end of group CLOCK */
1388
1389 /*@} end of group BL616_Peripheral_Driver */
1390