1 /**
2 ******************************************************************************
3 * @file bl616_l1c.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl616_l1c.h"
38 #include "bl616_common.h"
39 // #include "bl616_glb.h"
40
41 /** @addtogroup BL616_Peripheral_Driver
42 * @{
43 */
44
45 /** @addtogroup L1C
46 * @{
47 */
48
49 /** @defgroup L1C_Private_Macros
50 * @{
51 */
52
53 /*@} end of group L1C_Private_Macros */
54
55 /** @defgroup L1C_Private_Types
56 * @{
57 */
58
59 /*@} end of group L1C_Private_Types */
60
61 /** @defgroup L1C_Private_Variables
62 * @{
63 */
64
65 /*@} end of group L1C_Private_Variables */
66
67 /** @defgroup L1C_Global_Variables
68 * @{
69 */
70
71 /*@} end of group L1C_Global_Variables */
72
73 /** @defgroup L1C_Private_Fun_Declaration
74 * @{
75 */
76
77 /*@} end of group L1C_Private_Fun_Declaration */
78
79 /** @defgroup L1C_Private_Functions
80 * @{
81 */
82
83 /*@} end of group L1C_Private_Functions */
84
85 /** @defgroup L1C_Public_Functions
86 * @{
87 */
88
89 /****************************************************************************/ /**
90 * @brief Enable I-Cache
91 *
92 * @param wayDsiable: cache way disable config
93 *
94 * @return SUCCESS or ERROR
95 *
96 *******************************************************************************/
97 __WEAK
L1C_ICache_Enable(uint8_t wayDsiable)98 BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Enable(uint8_t wayDsiable)
99 {
100 #ifndef __riscv_32e
101 csi_icache_enable();
102 #endif
103 return SUCCESS;
104 }
105
106 /****************************************************************************/ /**
107 * @brief Enable D-Cache
108 *
109 * @param wayDsiable: cache way disable config
110 *
111 * @return SUCCESS or ERROR
112 *
113 *******************************************************************************/
114 __WEAK
L1C_DCache_Enable(uint8_t wayDsiable)115 BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Enable(uint8_t wayDsiable)
116 {
117 #ifndef __riscv_32e
118 csi_dcache_enable();
119 #endif
120 return SUCCESS;
121 }
122
123 /****************************************************************************/ /**
124 * @brief Disable I-Cache
125 *
126 * @param None
127 *
128 * @return SUCCESS or ERROR
129 *
130 *******************************************************************************/
131 __WEAK
L1C_ICache_Disable(void)132 BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Disable(void)
133 {
134 #ifndef __riscv_32e
135 csi_icache_disable();
136 #endif
137 return SUCCESS;
138 }
139
140 /****************************************************************************/ /**
141 * @brief Disable D-Cache
142 *
143 * @param None
144 *
145 * @return SUCCESS or ERROR
146 *
147 *******************************************************************************/
148 __WEAK
L1C_DCache_Disable(void)149 BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Disable(void)
150 {
151 #ifndef __riscv_32e
152 csi_dcache_disable();
153 #endif
154 return SUCCESS;
155 }
156
157 /****************************************************************************/ /**
158 * @brief L1C D-Cache write set
159 *
160 * @param wtEn: L1C write through enable
161 * @param wbEn: L1C write back enable
162 * @param waEn: L1C write allocate enable
163 *
164 * @return None
165 *
166 *******************************************************************************/
167 __WEAK
L1C_DCache_Write_Set(BL_Fun_Type wtEn,BL_Fun_Type wbEn,BL_Fun_Type waEn)168 void ATTR_TCM_SECTION L1C_DCache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)
169 {
170 return;
171 }
172
173 /****************************************************************************/ /**
174 * @brief Clean all D_Cache
175 *
176 * @param None
177 *
178 * @return SUCCESS or ERROR
179 *
180 *******************************************************************************/
181 __WEAK
L1C_DCache_Clean_All(void)182 BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_All(void)
183 {
184 #ifndef __riscv_32e
185 csi_dcache_clean();
186 #endif
187 return SUCCESS;
188 }
189
190 /****************************************************************************/ /**
191 * @brief Clean and invalid all D_Cache
192 *
193 * @param None
194 *
195 * @return SUCCESS or ERROR
196 *
197 *******************************************************************************/
198 __WEAK
L1C_DCache_Clean_Invalid_All(void)199 BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_Invalid_All(void)
200 {
201 #ifndef __riscv_32e
202 csi_dcache_clean_invalid();
203 #endif
204 return SUCCESS;
205 }
206
207 /****************************************************************************/ /**
208 * @brief Invalid all I-Cache
209 *
210 * @param None
211 *
212 * @return SUCCESS or ERROR
213 *
214 *******************************************************************************/
215 __WEAK
L1C_ICache_Invalid_All(void)216 BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Invalid_All(void)
217 {
218 #ifndef __riscv_32e
219 csi_icache_invalid();
220 #endif
221 return SUCCESS;
222 }
223
224 /****************************************************************************/ /**
225 * @brief Invalid all D_Cache
226 *
227 * @param None
228 *
229 * @return SUCCESS or ERROR
230 *
231 *******************************************************************************/
232 __WEAK
L1C_DCache_Invalid_All(void)233 BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Invalid_All(void)
234 {
235 #ifndef __riscv_32e
236 csi_dcache_invalid();
237 #endif
238 return SUCCESS;
239 }
240
241 /****************************************************************************/ /**
242 * @brief Clean D-Cache according to address
243 *
244 * @param addr: Address to clean
245 * @param len: Length to clean
246 *
247 * @return SUCCESS or ERROR
248 *
249 *******************************************************************************/
250 __WEAK
L1C_DCache_Clean_By_Addr(uintptr_t addr,uint32_t len)251 BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_By_Addr(uintptr_t addr, uint32_t len)
252 {
253 #ifndef __riscv_32e
254 #ifdef CPU_D0
255 csi_dcache_clean_range((uintptr_t *)addr, len);
256 #else
257 csi_dcache_clean_range((uint32_t *)(uintptr_t *)addr, len);
258 #endif
259 #endif
260 return SUCCESS;
261 }
262
263 /****************************************************************************/ /**
264 * @brief Clean and invalid D-Cache according to address
265 *
266 * @param addr: Address to clean
267 * @param len: Length to clean
268 *
269 * @return SUCCESS or ERROR
270 *
271 *******************************************************************************/
272 __WEAK
L1C_DCache_Clean_Invalid_By_Addr(uintptr_t addr,uint32_t len)273 BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_Invalid_By_Addr(uintptr_t addr, uint32_t len)
274 {
275 #ifndef __riscv_32e
276 #ifdef CPU_D0
277 csi_dcache_clean_invalid_range((uintptr_t *)addr, len);
278 #else
279 csi_dcache_clean_invalid_range((uint32_t *)(uintptr_t *)addr, len);
280 #endif
281 #endif
282 return SUCCESS;
283 }
284
285 /****************************************************************************/ /**
286 * @brief Invalid I-Cache according to address
287 *
288 * @param addr: Address to clean
289 * @param len: Length to clean
290 *
291 * @return SUCCESS or ERROR
292 *
293 *******************************************************************************/
294 __WEAK
L1C_ICache_Invalid_By_Addr(uintptr_t addr,uint32_t len)295 BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Invalid_By_Addr(uintptr_t addr, uint32_t len)
296 {
297 L1C_ICache_Invalid_All();
298
299 return SUCCESS;
300 }
301
302 /****************************************************************************/ /**
303 * @brief Invalid D-Cache according to address
304 *
305 * @param addr: Address to clean
306 * @param len: Length to clean
307 *
308 * @return SUCCESS or ERROR
309 *
310 *******************************************************************************/
311 __WEAK
L1C_DCache_Invalid_By_Addr(uintptr_t addr,uint32_t len)312 BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Invalid_By_Addr(uintptr_t addr, uint32_t len)
313 {
314 #ifndef __riscv_32e
315 #ifdef CPU_D0
316 csi_dcache_invalid_range((uintptr_t *)addr, len);
317 #else
318 csi_dcache_invalid_range((uint32_t *)(uintptr_t *)addr, len);
319 #endif
320 #endif
321 return SUCCESS;
322 }
323
324 /****************************************************************************/ /**
325 * @brief cache wrap
326 *
327 * @param en: wrap enable or disable
328 *
329 * @return SUCCESS or ERROR
330 *
331 *******************************************************************************/
L1C_Set_Wrap(uint8_t en)332 BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(uint8_t en)
333 {
334 return SUCCESS;
335 }
336
337 /****************************************************************************/ /**
338 * @brief cache wrap
339 *
340 * @param core: cpu core
341 * @param cacheSetting: cache setting
342 *
343 * @return SUCCESS or ERROR
344 *
345 *******************************************************************************/
L1C_Set_Cache_Setting_By_ID(uint8_t core,L1C_CACHE_Cfg_Type * cacheSetting)346 BL_Err_Type ATTR_TCM_SECTION L1C_Set_Cache_Setting_By_ID(uint8_t core, L1C_CACHE_Cfg_Type *cacheSetting)
347 {
348 (void)core;
349 (void)cacheSetting;
350
351 return SUCCESS;
352 }
353
354 /****************************************************************************/ /**
355 * @brief Judge addr is in cache range
356 *
357 * @param addr: phyical addr
358 *
359 * @return 1 for addr is in cache range and 0 for not in cache range
360 *
361 *******************************************************************************/
L1C_Is_DCache_Range(uintptr_t addr)362 int ATTR_TCM_SECTION L1C_Is_DCache_Range(uintptr_t addr)
363 {
364 if(((addr>>16)&0xffff)>=0x62FC){
365 return 1;
366 }else{
367 return 0;
368 }
369 }
370
371 /****************************************************************************/ /**
372 * @brief Get None Cache address according to Cache address
373 *
374 * @param addr: cache addr
375 *
376 * @return none cache addr
377 *
378 *******************************************************************************/
L1C_Get_None_Cache_Addr(uintptr_t addr)379 int ATTR_TCM_SECTION L1C_Get_None_Cache_Addr(uintptr_t addr)
380 {
381 return (addr&0x0FFFFFFF)|0x20000000;
382 }
383
384 /*@} end of group L1C_Public_Functions */
385
386 /*@} end of group L1C */
387
388 /*@} end of group BL616_Peripheral_Driver */
389