1 /**
2 ******************************************************************************
3 * @file bl702_aon.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl702_aon.h"
38
39 /** @addtogroup BL702_Peripheral_Driver
40 * @{
41 */
42
43 /** @addtogroup AON
44 * @{
45 */
46
47 /** @defgroup AON_Private_Macros
48 * @{
49 */
50 #define AON_CLK_SET_DUMMY_WAIT \
51 { \
52 __NOP(); \
53 __NOP(); \
54 __NOP(); \
55 __NOP(); \
56 __NOP(); \
57 __NOP(); \
58 __NOP(); \
59 __NOP(); \
60 }
61
62 /*@} end of group AON_Private_Macros */
63
64 /** @defgroup AON_Private_Types
65 * @{
66 */
67
68 /*@} end of group AON_Private_Types */
69
70 /** @defgroup AON_Private_Variables
71 * @{
72 */
73
74 /*@} end of group AON_Private_Variables */
75
76 /** @defgroup AON_Global_Variables
77 * @{
78 */
79
80 /*@} end of group AON_Global_Variables */
81
82 /** @defgroup AON_Private_Fun_Declaration
83 * @{
84 */
85
86 /*@} end of group AON_Private_Fun_Declaration */
87
88 /** @defgroup AON_Private_Functions
89 * @{
90 */
91
92 /*@} end of group AON_Private_Functions */
93
94 /** @defgroup AON_Public_Functions
95 * @{
96 */
97
98 /****************************************************************************/ /**
99 * @brief Power on MXX band gap
100 *
101 * @param None
102 *
103 * @return SUCCESS or ERROR
104 *
105 *******************************************************************************/
106 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_On_MBG(void)107 __WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
108 {
109 uint32_t tmpVal = 0;
110
111 /* Power up RF for PLL to work */
112 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
113 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
114 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
115
116 BL702_Delay_US(55);
117
118 return SUCCESS;
119 }
120 #endif
121
122 /****************************************************************************/ /**
123 * @brief Power off MXX band gap
124 *
125 * @param None
126 *
127 * @return SUCCESS or ERROR
128 *
129 *******************************************************************************/
130 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_Off_MBG(void)131 __WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
132 {
133 uint32_t tmpVal = 0;
134
135 /* Power OFF */
136 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
137 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
138 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
139
140 return SUCCESS;
141 }
142 #endif
143
144 /****************************************************************************/ /**
145 * @brief Power on XTAL
146 *
147 * @param None
148 *
149 * @return SUCCESS or ERROR
150 *
151 *******************************************************************************/
152 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_On_XTAL(void)153 __WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
154 {
155 uint32_t tmpVal = 0;
156 uint32_t timeOut = 0;
157
158 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
159 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON);
160 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
161 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
162
163 /* Polling for ready */
164 do {
165 BL702_Delay_US(10);
166 timeOut++;
167 tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
168 } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120);
169
170 if (timeOut >= 120) {
171 return TIMEOUT;
172 }
173
174 return SUCCESS;
175 }
176 #endif
177
178 /****************************************************************************/ /**
179 * @brief Set XTAL cap code
180 *
181 * @param capIn: Cap code in
182 * @param capOut: Cap code out
183 *
184 * @return SUCCESS or ERROR
185 *
186 *******************************************************************************/
187 #ifndef BFLB_USE_ROM_DRIVER
AON_Set_Xtal_CapCode(uint8_t capIn,uint8_t capOut)188 __WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
189 {
190 uint32_t tmpVal = 0;
191
192 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
193 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn);
194 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut);
195 BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
196
197 BL702_Delay_US(100);
198
199 return SUCCESS;
200 }
201 #endif
202
203 /****************************************************************************/ /**
204 * @brief Get XTAL cap code
205 *
206 * @param None
207 *
208 * @return Cap code
209 *
210 *******************************************************************************/
AON_Get_Xtal_CapCode(void)211 uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
212 {
213 uint32_t tmpVal = 0;
214
215 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
216
217 return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);
218 }
219
220 /****************************************************************************/ /**
221 * @brief Set XTAL cap code
222 *
223 * @param extra: cap cpde extra aon
224 *
225 * @return SUCCESS or ERROR
226 *
227 *******************************************************************************/
AON_Set_Xtal_CapCode_Extra(uint8_t extra)228 BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode_Extra(uint8_t extra)
229 {
230 uint32_t tmpVal = 0;
231
232 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
233 if (extra) {
234 tmpVal = BL_SET_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
235 } else {
236 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
237 }
238 BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
239
240 return SUCCESS;
241 }
242
243 /****************************************************************************/ /**
244 * @brief Power off XTAL
245 *
246 * @param None
247 *
248 * @return SUCCESS or ERROR
249 *
250 *******************************************************************************/
251 #ifndef BFLB_USE_ROM_DRIVER
AON_Power_Off_XTAL(void)252 __WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
253 {
254 uint32_t tmpVal = 0;
255
256 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
257 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON);
258 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
259 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
260
261 return SUCCESS;
262 }
263 #endif
264
265 /****************************************************************************/ /**
266 * @brief Power on bandgap system
267 *
268 * @param None
269 *
270 * @return SUCCESS or ERROR
271 *
272 *******************************************************************************/
AON_Power_On_BG(void)273 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
274 {
275 uint32_t tmpVal = 0;
276
277 /* power up RF for PLL to work */
278 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
279 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
280 BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
281
282 BL702_Delay_US(55);
283
284 return SUCCESS;
285 }
286
287 /****************************************************************************/ /**
288 * @brief Power off bandgap system
289 *
290 * @param None
291 *
292 * @return SUCCESS or ERROR
293 *
294 *******************************************************************************/
AON_Power_Off_BG(void)295 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
296 {
297 uint32_t tmpVal = 0;
298
299 /* power up RF for PLL to work */
300 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
301 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
302 BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
303
304 BL702_Delay_US(55);
305
306 return SUCCESS;
307 }
308
309 /****************************************************************************/ /**
310 * @brief Power on LDO11
311 *
312 * @param None
313 *
314 * @return SUCCESS or ERROR
315 *
316 *******************************************************************************/
AON_Power_On_LDO11_SOC(void)317 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void)
318 {
319 uint32_t tmpVal = 0;
320
321 tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
322 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
323 BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
324
325 BL702_Delay_US(55);
326
327 return SUCCESS;
328 }
329
330 /****************************************************************************/ /**
331 * @brief Power off LDO11
332 *
333 * @param None
334 *
335 * @return SUCCESS or ERROR
336 *
337 *******************************************************************************/
AON_Power_Off_LDO11_SOC(void)338 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void)
339 {
340 uint32_t tmpVal = 0;
341
342 tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
343 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
344 BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
345
346 BL702_Delay_US(55);
347
348 return SUCCESS;
349 }
350
351 /****************************************************************************/ /**
352 * @brief Power on LDO15_RF
353 *
354 * @param None
355 *
356 * @return SUCCESS or ERROR
357 *
358 *******************************************************************************/
AON_Power_On_LDO15_RF(void)359 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
360 {
361 uint32_t tmpVal = 0;
362
363 /* ldo15rf power on */
364 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
365 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
366 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
367
368 BL702_Delay_US(90);
369
370 return SUCCESS;
371 }
372
373 /****************************************************************************/ /**
374 * @brief Power off LDO15_RF
375 *
376 * @param None
377 *
378 * @return SUCCESS or ERROR
379 *
380 *******************************************************************************/
AON_Power_Off_LDO15_RF(void)381 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
382 {
383 uint32_t tmpVal = 0;
384
385 /* ldo15rf power off */
386 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
387 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
388 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
389
390 return SUCCESS;
391 }
392
393 /****************************************************************************/ /**
394 * @brief power on source follow regular
395 *
396 * @param None
397 *
398 * @return SUCCESS or ERROR
399 *
400 *******************************************************************************/
AON_Power_On_SFReg(void)401 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
402 {
403 uint32_t tmpVal = 0;
404
405 /* power on sfreg */
406 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
407 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
408 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
409
410 BL702_Delay_US(10);
411
412 return SUCCESS;
413 }
414
415 /****************************************************************************/ /**
416 * @brief power off source follow regular
417 *
418 * @param None
419 *
420 * @return SUCCESS or ERROR
421 *
422 *******************************************************************************/
AON_Power_Off_SFReg(void)423 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
424 {
425 uint32_t tmpVal = 0;
426
427 /* power off sfreg */
428 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
429 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
430 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
431
432 return SUCCESS;
433 }
434
435 /****************************************************************************/ /**
436 * @brief Power off the power can be shut down in PDS0
437 *
438 * @param None
439 *
440 * @return SUCCESS or ERROR
441 *
442 *******************************************************************************/
AON_LowPower_Enter_PDS0(void)443 BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
444 {
445 uint32_t tmpVal = 0;
446
447 /* power off bz */
448 tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
449 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_BZ_EN_AON);
450 BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
451
452 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
453 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
454 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
455 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
456 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
457
458 /* gating Clock, no more use */
459 //tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0);
460 //tmpVal=tmpVal&(~(1<<6));
461 //tmpVal=tmpVal&(~(1<<7));
462 //BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal);
463
464 return SUCCESS;
465 }
466
467 /****************************************************************************/ /**
468 * @brief Power on the power powered down in PDS0
469 *
470 * @param None
471 *
472 * @return SUCCESS or ERROR
473 *
474 *******************************************************************************/
AON_LowPower_Exit_PDS0(void)475 BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
476 {
477 uint32_t tmpVal = 0;
478
479 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
480
481 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
482 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
483
484 BL702_Delay_US(20);
485
486 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
487 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
488
489 BL702_Delay_US(60);
490
491 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
492 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
493
494 BL702_Delay_US(20);
495
496 /* power on bz */
497 tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
498 tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_BZ_EN_AON);
499 BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
500
501 /* ungating Clock, no more use */
502 //tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0);
503 //tmpVal=tmpVal|((1<<6));
504 //tmpVal=tmpVal|((1<<7));
505 //BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal);
506
507 return SUCCESS;
508 }
509
510 /****************************************************************************/ /**
511 * @brief Power on the power powered down in PDS0
512 *
513 * @param delay: None
514 *
515 * @return SUCCESS or ERROR
516 *
517 *******************************************************************************/
AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay)518 BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay)
519 {
520 uint32_t tmpVal = 0;
521
522 CHECK_PARAM((delay <= 0x3));
523
524 /* config ldo11soc_sstart_delay_aon */
525 tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
526 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_SSTART_DELAY_AON, delay);
527 BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
528
529 return SUCCESS;
530 }
531
532 /****************************************************************************/ /**
533 * @brief
534 *
535 * @param
536 *
537 * @return
538 *
539 *******************************************************************************/
AON_Set_DCDC18_Top_0(uint8_t voutSel,uint8_t vpfm)540 BL_Err_Type AON_Set_DCDC18_Top_0(uint8_t voutSel, uint8_t vpfm)
541 {
542 uint32_t tmpVal = 0;
543
544 tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_0);
545 //dcdc18_vout_sel_aon, 1.425V*1.05=1.5V
546 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VOUT_SEL_AON, voutSel);
547 //dcdc18_vpfm_aon
548 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VPFM_AON, vpfm);
549 BL_WR_REG(AON_BASE, AON_DCDC18_TOP_0, tmpVal);
550
551 return SUCCESS;
552 }
553
554 /****************************************************************************/ /**
555 * @brief
556 *
557 * @param
558 *
559 * @return
560 *
561 *******************************************************************************/
AON_Set_Xtal_Cfg(uint8_t gmBoost,uint8_t ampCtrl,uint8_t fastStartup)562 BL_Err_Type AON_Set_Xtal_Cfg(uint8_t gmBoost, uint8_t ampCtrl, uint8_t fastStartup)
563 {
564 uint32_t tmpVal = 0;
565
566 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
567 //xtal_gm_boost
568 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_GM_BOOST_AON, gmBoost);
569 //xtal_amp_ctrl
570 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_AMP_CTRL_AON, ampCtrl);
571 //xtal_fast_startup
572 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_FAST_STARTUP_AON, fastStartup);
573 BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
574
575 return SUCCESS;
576 }
577
578 /*@} end of group AON_Public_Functions */
579
580 /*@} end of group AON */
581
582 /*@} end of group BL702_Peripheral_Driver */
583