1 /**
2 ******************************************************************************
3 * @file bl702_clock.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl702_clock.h"
38
39 /** @addtogroup BL702_Peripheral_Driver
40 * @{
41 */
42
43 /** @addtogroup CLOCK
44 * @{
45 */
46
47 /** @defgroup CLOCK_Private_Macros
48 * @{
49 */
50
51 /*@} end of group CLOCK_Private_Macros */
52
53 /** @defgroup CLOCK_Private_Types
54 * @{
55 */
56
57 /*@} end of group CLOCK_Private_Types */
58
59 /** @defgroup CLOCK_Private_Variables
60 * @{
61 */
62
63 /*@} end of group CLOCK_Private_Variables */
64
65 /** @defgroup CLOCK_Global_Variables
66 * @{
67 */
68
69 /*@} end of group CLOCK_Global_Variables */
70
71 /** @defgroup CLOCK_Private_Fun_Declaration
72 * @{
73 */
74
75 /*@} end of group CLOCK_Private_Fun_Declaration */
76
77 /** @defgroup CLOCK_Private_Functions
78 * @{
79 */
80
81 /*@} end of group CLOCK_Private_Functions */
82
83 /** @defgroup CLOCK_Public_Functions
84 * @{
85 */
86
Clock_Xtal_Output(void)87 static inline uint32_t Clock_Xtal_Output(void)
88 {
89 /* 32m */
90 return (32 * 1000 * 1000);
91 }
92
Clock_XClk_Mux_Output(uint8_t sel)93 static inline uint32_t Clock_XClk_Mux_Output(uint8_t sel)
94 {
95 if (sel == 0) {
96 /* rc32m */
97 return (32 * 1000 * 1000);
98 } else {
99 /* xtal */
100 return Clock_Xtal_Output();
101 }
102 }
103
Clock_Get_MCU_XClk_Sel_Val(void)104 static inline uint8_t Clock_Get_MCU_XClk_Sel_Val(void)
105 {
106 uint32_t tmpVal = 0;
107
108 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
109 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL);
110
111 return (tmpVal & 0x1);
112 }
113
Clock_Get_MCU_Root_Clk_Sel_Val(void)114 static inline uint8_t Clock_Get_MCU_Root_Clk_Sel_Val(void)
115 {
116 uint32_t tmpVal;
117
118 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
119 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL);
120
121 return ((tmpVal >> 1) & 0x1);
122 }
123
Clock_MCU_Clk_Mux_Output(uint8_t sel)124 static inline uint32_t Clock_MCU_Clk_Mux_Output(uint8_t sel)
125 {
126 if (sel == 0) {
127 /* pll 57.6m */
128 return (576 * 100 * 1000);
129 } else if (sel == 1) {
130 /* pll 96m */
131 return (96 * 1000 * 1000);
132 } else if (sel == 2) {
133 /* pll 144m */
134 return (144 * 1000 * 1000);
135 } else if (sel == 3) {
136 /* pll 120m */
137 return (120 * 1000 * 1000);
138 } else {
139 return 0;
140 }
141 }
142
Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)143 static inline uint32_t Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)
144 {
145 uint32_t tmpVal;
146
147 if (sel == 0) {
148 /* xclk */
149 return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());
150 } else if (sel == 1) {
151 /* pll */
152 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
153 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL);
154 return Clock_MCU_Clk_Mux_Output(tmpVal);
155 } else {
156 return 0;
157 }
158 }
159
Clock_Get_MCU_HClk_Div_Val(void)160 static inline uint8_t Clock_Get_MCU_HClk_Div_Val(void)
161 {
162 uint32_t tmpVal;
163
164 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
165
166 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
167 }
168
Clock_Get_Peri_BClk_Div_Val(void)169 static inline uint8_t Clock_Get_Peri_BClk_Div_Val(void)
170 {
171 uint32_t tmpVal;
172
173 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
174
175 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
176 }
177
Clock_F32k_Mux_Output(uint8_t sel)178 static inline uint32_t Clock_F32k_Mux_Output(uint8_t sel)
179 {
180 uint32_t tmpVal;
181 uint32_t div = 0;
182
183 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
184 div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV);
185
186 if (sel == 0) {
187 /* src32K */
188 return (32 * 1000);
189 } else if (sel == 1) {
190 /* xtal 32K */
191 return (32 * 1000);
192 } else {
193 return Clock_Xtal_Output() / (div + 1);
194 }
195 }
196
Clock_Get_F32k_Sel_Val(void)197 static inline uint8_t Clock_Get_F32k_Sel_Val(void)
198 {
199 uint32_t tmpVal;
200
201 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
202
203 return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL);
204 }
205
Clock_Get_AUPLL_Output()206 static inline uint32_t Clock_Get_AUPLL_Output()
207 {
208 uint32_t tmpVal = 0;
209
210 tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM), PDS_CLKPLL_SDMIN);
211
212 if (tmpVal == 0x374BC6) {
213 /* aupll 12288000 */
214 return (12288000);
215 } else if (tmpVal == 0x32CCED) {
216 if (BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL), PDS_CLKPLL_POSTDIV) == 36) {
217 /* aupll 11289600 */
218 return (11289600);
219 } else {
220 /* aupll 5644800 */
221 return (5644800);
222 }
223 } else if (tmpVal == 0x6E978D) {
224 /* aupll 24576000 */
225 return (24576000);
226 } else if (tmpVal == 0x6C0000) {
227 /* aupll 24000000 */
228 return (24000000);
229 } else {
230 return 0;
231 }
232 }
233
234 /****************************************************************************/ /**
235 * @brief Get System Clock
236 *
237 * @param type: System clock type
238 *
239 * @return System clock value
240 *
241 *******************************************************************************/
Clock_System_Clock_Get(BL_System_Clock_Type type)242 uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type)
243 {
244 uint32_t clock = 0;
245 uint32_t div = 0;
246
247 switch (type) {
248 case BL_SYSTEM_CLOCK_XCLK:
249 /*!< mcu xclk clock */
250 return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());
251
252 case BL_SYSTEM_CLOCK_ROOT:
253 /*!< mcu root clock */
254 return Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());
255
256 case BL_SYSTEM_CLOCK_FCLK:
257 /*!< mcu fast clock/cpu clock */
258 clock = Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());
259 div = Clock_Get_MCU_HClk_Div_Val();
260 return clock / (div + 1);
261
262 case BL_SYSTEM_CLOCK_BCLK:
263 /*!< mcu peri bus clock */
264 clock = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_FCLK);
265 div = Clock_Get_Peri_BClk_Div_Val();
266 return clock / (div + 1);
267
268 case BL_SYSTEM_CLOCK_XTAL:
269 /*!< xtal clock */
270 return Clock_Xtal_Output();
271
272 case BL_SYSTEM_CLOCK_F32K:
273 /*!< f32k clock */
274 return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
275
276 default:
277 return 0;
278 }
279 }
280
Clock_UART_Clk_Mux_Output(uint8_t sel)281 static inline uint32_t Clock_UART_Clk_Mux_Output(uint8_t sel)
282 {
283 if (sel == 0) {
284 /* fclk */
285 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_FCLK);
286 } else {
287 /* 96m */
288 return (96 * 1000 * 1000);
289 }
290 }
291
Clock_Get_UART_Clk_Sel_Val(void)292 static inline uint8_t Clock_Get_UART_Clk_Sel_Val(void)
293 {
294 uint32_t tmpVal;
295
296 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
297
298 return BL_GET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL);
299 }
300
Clock_Get_UART_Div_Val(void)301 static inline uint8_t Clock_Get_UART_Div_Val(void)
302 {
303 uint32_t tmpVal;
304
305 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
306
307 return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV);
308 }
309
Clock_SPI_Clk_Mux_Output(void)310 static inline uint32_t Clock_SPI_Clk_Mux_Output(void)
311 {
312 /* pbclk */
313 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
314 }
315
Clock_Get_SPI_Div_Val(void)316 static inline uint8_t Clock_Get_SPI_Div_Val(void)
317 {
318 uint32_t tmpVal;
319
320 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
321
322 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);
323 }
324
Clock_I2C_Clk_Mux_Output()325 static inline uint32_t Clock_I2C_Clk_Mux_Output()
326 {
327 /* pbclk */
328 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
329 }
330
Clock_Get_I2C_Div_Val(void)331 static inline uint8_t Clock_Get_I2C_Div_Val(void)
332 {
333 uint32_t tmpVal;
334
335 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
336
337 return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);
338 }
339
Clock_I2S_Clk_Mux_Output(void)340 static inline uint32_t Clock_I2S_Clk_Mux_Output(void)
341 {
342 /* aupll clk */
343 return Clock_Get_AUPLL_Output();
344 }
345
Clock_Get_GPADC_Div_Val(void)346 static inline uint8_t Clock_Get_GPADC_Div_Val(void)
347 {
348 uint32_t tmpVal;
349
350 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
351
352 return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
353 }
354
Clock_GPADC_Clk_Output(uint8_t sel)355 static inline uint32_t Clock_GPADC_Clk_Output(uint8_t sel)
356 {
357 if (sel == 0) {
358 /* aupll clk */
359 return Clock_Get_AUPLL_Output();
360 } else {
361 /* xclk */
362 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
363 }
364 }
365
Clock_Get_GPADC_32M_Clk_Sel_Val(void)366 static inline uint8_t Clock_Get_GPADC_32M_Clk_Sel_Val(void)
367 {
368 uint32_t tmpVal;
369
370 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
371
372 return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL);
373 }
374
Clock_GPADC_Clk_Mux_Output(uint8_t sel)375 static inline uint32_t Clock_GPADC_Clk_Mux_Output(uint8_t sel)
376 {
377 uint32_t div = 0;
378
379 if (sel == 1) {
380 /* f32k clk */
381 return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
382 } else {
383 div = Clock_Get_GPADC_Div_Val();
384 return Clock_GPADC_Clk_Output(Clock_Get_GPADC_32M_Clk_Sel_Val()) / (div + 1);
385 }
386 }
387
Clock_Get_GPADC_Clk_Sel_Val(void)388 static inline uint8_t Clock_Get_GPADC_Clk_Sel_Val(void)
389 {
390 uint32_t tmpVal;
391
392 tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
393
394 return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_EN);
395 }
396
Clock_GPDAC_Clk_Mux_Output(uint8_t sel)397 static inline uint32_t Clock_GPDAC_Clk_Mux_Output(uint8_t sel)
398 {
399 if (sel == 0) {
400 /* pll 32m */
401 return (32 * 1000 * 1000);
402 } else if (sel == 1) {
403 /* xclk */
404 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
405 } else {
406 /* aupll clk */
407 return Clock_Get_AUPLL_Output();
408 }
409 }
410
Clock_Get_GPDAC_Div_Val(void)411 static inline uint8_t Clock_Get_GPDAC_Div_Val(void)
412 {
413 uint32_t tmpVal;
414
415 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
416
417 return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
418 }
419
Clock_Get_GPDAC_Clk_Sel_Val(void)420 static inline uint8_t Clock_Get_GPDAC_Clk_Sel_Val(void)
421 {
422 uint32_t tmpVal;
423
424 tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
425
426 return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL);
427 }
428
429 // static inline uint32_t Clock_PWM_Clk_Mux_Output(uint8_t sel)
430 // {
431 // if (sel == 0) {
432 // /* xclk */
433 // return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
434 // } else if (sel == 1) {
435 // /* pbclk */
436 // return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
437 // } else {
438 // /* f32k clk */
439 // return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
440 // }
441 // }
442
443 // static inline uint8_t Clock_Get_PWM_Div_Val(void)
444 // {
445 // uint32_t tmpVal;
446
447 // tmpVal = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);
448
449 // return tmpVal;
450 // }
451
452 // static inline uint8_t Clock_Get_PWM_Clk_Sel_Val(void)
453 // {
454 // uint32_t tmpVal;
455
456 // tmpVal = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CONFIG);
457
458 // return BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL);
459 // }
460
Clock_IR_Clk_Mux_Output(void)461 static inline uint32_t Clock_IR_Clk_Mux_Output(void)
462 {
463 /* xclk */
464 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
465 }
466
Clock_Get_IR_Div_Val(void)467 static inline uint8_t Clock_Get_IR_Div_Val(void)
468 {
469 uint32_t tmpVal;
470
471 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
472
473 return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV);
474 }
475
Clock_CAM_Clk_Mux_Output(uint8_t sel)476 static inline uint32_t Clock_CAM_Clk_Mux_Output(uint8_t sel)
477 {
478 if (sel == 0) {
479 /* xclk */
480 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
481 } else {
482 /* 96m */
483 return (96 * 1000 * 1000);
484 }
485 }
486
Clock_Get_CAM_Clk_Sel_Val(void)487 static inline uint8_t Clock_Get_CAM_Clk_Sel_Val(void)
488 {
489 uint32_t tmpVal;
490
491 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
492
493 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL);
494 }
495
Clock_Get_CAM_Div_Val(void)496 static inline uint8_t Clock_Get_CAM_Div_Val(void)
497 {
498 uint32_t tmpVal;
499
500 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
501
502 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);
503 }
504
Clock_Get_SF_Clk_Sel2_Val(void)505 static inline uint8_t Clock_Get_SF_Clk_Sel2_Val(void)
506 {
507 uint32_t tmpVal;
508
509 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
510
511 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2);
512 }
513
Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)514 static inline uint32_t Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)
515 {
516 if (sel == 0) {
517 /* 144m */
518 return (144 * 1000 * 1000);
519 } else if (sel == 1) {
520 /* xclk */
521 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
522 } else {
523 /* 57.6m */
524 return (576 * 100 * 1000);
525 }
526 }
527
Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)528 static inline uint32_t Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)
529 {
530 if (sel == 0) {
531 /* sf sel2 */
532 return Clock_SF_SEL2_Clk_Mux_Output(Clock_Get_SF_Clk_Sel2_Val());
533 } else if (sel == 1) {
534 /* 72m */
535 return (72 * 1000 * 1000);
536 } else if (sel == 2) {
537 /* pbclk */
538 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
539 } else {
540 /* 96m */
541 return (96 * 1000 * 1000);
542 }
543 }
544
Clock_Get_SF_Clk_Sel_Val(void)545 static inline uint8_t Clock_Get_SF_Clk_Sel_Val(void)
546 {
547 uint32_t tmpVal;
548
549 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
550
551 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL);
552 }
553
Clock_Get_SF_Div_Val(void)554 static inline uint8_t Clock_Get_SF_Div_Val(void)
555 {
556 uint32_t tmpVal;
557
558 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
559
560 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV);
561 }
562
Clock_QDEC_Clk_Mux_Output(uint8_t sel)563 static inline uint32_t Clock_QDEC_Clk_Mux_Output(uint8_t sel)
564 {
565 if (sel == 0) {
566 /* xclk */
567 return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
568 } else {
569 /* f32k clk */
570 return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
571 }
572 }
573
Clock_Get_QDEC_Clk_Sel_Val(void)574 static inline uint8_t Clock_Get_QDEC_Clk_Sel_Val(void)
575 {
576 uint32_t tmpVal;
577
578 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
579
580 return BL_GET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_SEL);
581 }
582
Clock_Get_QDEC_Div_Val(void)583 static inline uint8_t Clock_Get_QDEC_Div_Val(void)
584 {
585 uint32_t tmpVal;
586
587 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
588
589 return BL_GET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_DIV);
590 }
591
592 // static inline uint32_t Clock_TIMER_Clk_Mux_Output(uint8_t sel)
593 // {
594 // if (sel == 0) {
595 // /* fclk */
596 // return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_FCLK);
597 // } else if (sel == 1) {
598 // /* f32k clk */
599 // return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
600 // } else if (sel == 2) {
601 // /* 1k */
602 // return (1000);
603 // } else {
604 // /* 32m */
605 // return (32 * 1000 * 1000);
606 // }
607 // }
608
609 // static inline uint8_t Clock_Get_TIMER0_Clk_Sel_Val(void)
610 // {
611 // uint32_t tmpVal;
612
613 // tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
614
615 // return BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_1);
616 // }
617
618 // static inline uint8_t Clock_Get_TIMER1_Clk_Sel_Val(void)
619 // {
620 // uint32_t tmpVal;
621
622 // tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
623
624 // return BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_2);
625 // }
626
627 // static inline uint8_t Clock_Get_WDT_Clk_Sel_Val(void)
628 // {
629 // uint32_t tmpVal;
630
631 // tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
632
633 // return BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT);
634 // }
635
636 /****************************************************************************/ /**
637 * @brief Get Peripheral Clock
638 *
639 * @param type: Peripheral clock type
640 *
641 * @return Peripheral clock value
642 *
643 *******************************************************************************/
Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)644 uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)
645 {
646 uint32_t clock = 0;
647 uint32_t div = 0;
648
649 switch (type) {
650 /*!< uart0 clock */
651 case BL_PERIPHERAL_CLOCK_UART0:
652 ATTR_FALLTHROUGH();
653
654 /*!< uart1 clock */
655 case BL_PERIPHERAL_CLOCK_UART1:
656 clock = Clock_UART_Clk_Mux_Output(Clock_Get_UART_Clk_Sel_Val());
657 div = Clock_Get_UART_Div_Val();
658 return clock / (div + 1);
659
660 /*!< FLASH clock */
661 case BL_PERIPHERAL_CLOCK_FLASH:
662 clock = Clock_SF_SEL_Clk_Mux_Output(Clock_Get_SF_Clk_Sel_Val());
663 div = Clock_Get_SF_Div_Val();
664 return clock / (div + 1);
665
666 /*!< spi0 clock */
667 case BL_PERIPHERAL_CLOCK_SPI0:
668 clock = Clock_SPI_Clk_Mux_Output();
669 div = Clock_Get_SPI_Div_Val();
670 return clock / (div + 1);
671
672 /*!< i2c0 clock */
673 case BL_PERIPHERAL_CLOCK_I2C0:
674 clock = Clock_I2C_Clk_Mux_Output();
675 div = Clock_Get_I2C_Div_Val();
676 return clock / (div + 1);
677
678 /*!< I2S clock */
679 case BL_PERIPHERAL_CLOCK_I2S:
680 clock = Clock_I2S_Clk_Mux_Output();
681 return clock;
682
683 /*!< GPADC clock */
684 case BL_PERIPHERAL_CLOCK_GPADC:
685 return Clock_GPADC_Clk_Mux_Output(Clock_Get_GPADC_Clk_Sel_Val());
686
687 /*!< GPDAC clock */
688 case BL_PERIPHERAL_CLOCK_GPDAC:
689 clock = Clock_GPDAC_Clk_Mux_Output(Clock_Get_GPDAC_Clk_Sel_Val());
690 div = Clock_Get_GPDAC_Div_Val();
691 return clock / (div + 1);
692
693 /*!< PWM clock */
694 // case BL_PERIPHERAL_CLOCK_PWM:
695 // clock = Clock_PWM_Clk_Mux_Output(Clock_Get_PWM_Clk_Sel_Val());
696 // div = Clock_Get_PWM_Div_Val();
697 // return clock / div;
698
699 /*!< IR clock */
700 case BL_PERIPHERAL_CLOCK_IR:
701 clock = Clock_IR_Clk_Mux_Output();
702 div = Clock_Get_IR_Div_Val();
703 return clock / (div + 1);
704
705 /*!< CAM clock */
706 case BL_PERIPHERAL_CLOCK_CAM:
707 clock = Clock_CAM_Clk_Mux_Output(Clock_Get_CAM_Clk_Sel_Val());
708 div = Clock_Get_CAM_Div_Val();
709 return clock / (div + 1);
710
711 /*!< QDEC clock */
712 case BL_PERIPHERAL_CLOCK_QDEC:
713 clock = Clock_QDEC_Clk_Mux_Output(Clock_Get_QDEC_Clk_Sel_Val());
714 div = Clock_Get_QDEC_Div_Val();
715 return clock / (div + 1);
716
717 /*!< TIMER0 clock */
718 // case BL_PERIPHERAL_CLOCK_TIMER0:
719 // return Clock_TIMER_Clk_Mux_Output(Clock_Get_TIMER0_Clk_Sel_Val());
720
721 // /*!< TIMER1 clock */
722 // case BL_PERIPHERAL_CLOCK_TIMER1:
723 // return Clock_TIMER_Clk_Mux_Output(Clock_Get_TIMER1_Clk_Sel_Val());
724
725 // /*!< WDT clock */
726 // case BL_PERIPHERAL_CLOCK_WDT:
727 // return Clock_TIMER_Clk_Mux_Output(Clock_Get_WDT_Clk_Sel_Val());
728
729 default:
730 return 0;
731 }
732 }
733
734 /*@} end of group CLOCK_Public_Functions */
735
736 /*@} end of group CLOCK */
737
738 /*@} end of group BL702_Peripheral_Driver */
739