1 /**
2 ******************************************************************************
3 * @file bl702_l1c.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl702_l1c.h"
38 #include "bl702_common.h"
39
40 /** @addtogroup BL702_Peripheral_Driver
41 * @{
42 */
43
44 /** @addtogroup L1C
45 * @{
46 */
47
48 /** @defgroup L1C_Private_Macros
49 * @{
50 */
51
52 /*@} end of group L1C_Private_Macros */
53
54 /** @defgroup L1C_Private_Types
55 * @{
56 */
57
58 /*@} end of group L1C_Private_Types */
59
60 /** @defgroup L1C_Private_Variables
61 * @{
62 */
63 static intCallback_Type *l1cBmxErrIntCbfArra[L1C_BMX_ERR_INT_ALL] = { NULL };
64 static intCallback_Type *l1cBmxToIntCbfArra[L1C_BMX_TO_INT_ALL] = { NULL };
65
66 /*@} end of group L1C_Private_Variables */
67
68 /** @defgroup L1C_Global_Variables
69 * @{
70 */
71
72 /*@} end of group L1C_Global_Variables */
73
74 /** @defgroup L1C_Private_Fun_Declaration
75 * @{
76 */
77
78 /*@} end of group L1C_Private_Fun_Declaration */
79
80 /** @defgroup L1C_Private_Functions
81 * @{
82 */
83
84 /*@} end of group L1C_Private_Functions */
85
86 /** @defgroup L1C_Public_Functions
87 * @{
88 */
89
90 /****************************************************************************/ /**
91 * @brief Enable cache
92 *
93 * @param wayDisable: cache way disable config
94 *
95 * @return SUCCESS or ERROR
96 *
97 *******************************************************************************/
98 #ifndef BFLB_USE_ROM_DRIVER
99 __WEAK
L1C_Cache_Enable_Set(uint8_t wayDisable)100 BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Enable_Set(uint8_t wayDisable)
101 {
102 uint32_t tmpVal;
103 uint32_t cnt = 0;
104 uint8_t finWayDisable = 0;
105
106 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
107 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
108 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS);
109 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS);
110 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CNT_EN);
111 finWayDisable = BL_GET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS);
112 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
113
114 /*Set Tag RAM to zero */
115 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_INVALID_EN);
116 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
117 /* Left space for hardware change status*/
118 __NOP();
119 __NOP();
120 __NOP();
121 __NOP();
122 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_INVALID_EN);
123 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
124 /* Left space for hardware change status*/
125 __NOP();
126 __NOP();
127 __NOP();
128 __NOP();
129
130 /* Polling for invalid done */
131 do {
132 BL702_Delay_US(1);
133 cnt++;
134 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
135 } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_INVALID_DONE) && cnt < 100);
136
137 /* data flush */
138 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN);
139 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
140 /* Left space for hardware change status*/
141 __NOP();
142 __NOP();
143 __NOP();
144 __NOP();
145 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_FLUSH_EN);
146 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
147 /* Left space for hardware change status*/
148 __NOP();
149 __NOP();
150 __NOP();
151 __NOP();
152
153 /* Polling for flush done */
154 do {
155 BL702_Delay_US(1);
156 cnt++;
157 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
158 } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_FLUSH_DONE) && cnt < 100);
159
160 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN);
161 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
162
163 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS);
164 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
165
166 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BYPASS);
167 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CNT_EN);
168 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
169
170 if (wayDisable != 0xff) {
171 finWayDisable = wayDisable;
172 }
173
174 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
175 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS);
176 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
177
178 tmpVal |= (finWayDisable << L1C_WAY_DIS_POS);
179
180 /* If way disable is 0x0f, cacheable can't be set */
181 if (finWayDisable != 0x0f) {
182 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
183 } else {
184 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
185 }
186
187 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
188
189 return SUCCESS;
190 }
191 #endif
192
193 /****************************************************************************/ /**
194 * @brief L1C cache write set
195 *
196 * @param wtEn: L1C write through enable
197 * @param wbEn: L1C write back enable
198 * @param waEn: L1C write allocate enable
199 *
200 * @return None
201 *
202 *******************************************************************************/
203 #ifndef BFLB_USE_ROM_DRIVER
204 __WEAK
L1C_Cache_Write_Set(BL_Fun_Type wtEn,BL_Fun_Type wbEn,BL_Fun_Type waEn)205 void ATTR_TCM_SECTION L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)
206 {
207 uint32_t tmpVal;
208
209 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
210
211 if (wtEn) {
212 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WT_EN);
213 } else {
214 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WT_EN);
215 }
216
217 if (wbEn) {
218 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WB_EN);
219 } else {
220 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WB_EN);
221 }
222
223 if (waEn) {
224 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WA_EN);
225 } else {
226 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WA_EN);
227 }
228
229 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
230 }
231 #endif
232
233 /****************************************************************************/ /**
234 * @brief Flush cache external api
235 *
236 * @param None
237 *
238 * @return SUCCESS or ERROR
239 *
240 *******************************************************************************/
L1C_Cache_Flush(void)241 BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush(void)
242 {
243 uint32_t tmpVal;
244
245 /* Disable early respone */
246 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
247 L1C_Cache_Enable_Set((tmpVal >> L1C_WAY_DIS_POS) & 0xf);
248 __NOP();
249 __NOP();
250 __NOP();
251 __NOP();
252 __NOP();
253
254 return SUCCESS;
255 }
256
257 /****************************************************************************/ /**
258 * @brief Get cache hit count
259 *
260 * @param hitCountLow: hit count low 32 bits pointer
261 * @param hitCountHigh: hit count high 32 bits pointer
262 *
263 * @return None
264 *
265 *******************************************************************************/
266 #ifndef BFLB_USE_ROM_DRIVER
267 __WEAK
L1C_Cache_Hit_Count_Get(uint32_t * hitCountLow,uint32_t * hitCountHigh)268 void ATTR_TCM_SECTION L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh)
269 {
270 *hitCountLow = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_LSB);
271 *hitCountHigh = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_MSB);
272 }
273 #endif
274
275 /****************************************************************************/ /**
276 * @brief Get cache miss count
277 *
278 * @param None
279 *
280 * @return Cache miss count
281 *
282 *******************************************************************************/
283 #ifndef BFLB_USE_ROM_DRIVER
284 __WEAK
L1C_Cache_Miss_Count_Get(void)285 uint32_t ATTR_TCM_SECTION L1C_Cache_Miss_Count_Get(void)
286 {
287 return BL_RD_REG(L1C_BASE, L1C_MISS_CNT);
288 }
289 #endif
290
291 /****************************************************************************/ /**
292 * @brief Disable read from flash or psram with cache
293 *
294 * @param None
295 *
296 * @return None
297 *
298 *******************************************************************************/
299 #ifndef BFLB_USE_ROM_DRIVER
300 __WEAK
L1C_Cache_Read_Disable(void)301 void ATTR_TCM_SECTION L1C_Cache_Read_Disable(void)
302 {
303 uint32_t tmpVal;
304
305 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
306 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
307 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
308 }
309 #endif
310
311 /****************************************************************************/ /**
312 * @brief wrap set
313 *
314 * @param wrap: ENABLE or DISABLE
315 *
316 * @return SUCCESS or ERROR
317 *
318 *******************************************************************************/
319 #ifndef BFLB_USE_ROM_DRIVER
320 __WEAK
L1C_Set_Wrap(BL_Fun_Type wrap)321 BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap)
322 {
323 uint32_t tmpVal = 0;
324 uint8_t cacheEn = 0;
325
326 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
327 cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE);
328
329 if (cacheEn != 0) {
330 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
331 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
332 }
333
334 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
335
336 if (wrap == ENABLE) {
337 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WRAP_DIS);
338 } else {
339 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WRAP_DIS);
340 }
341
342 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
343
344 if (cacheEn != 0) {
345 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
346 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
347 }
348
349 return SUCCESS;
350 }
351 #endif
352
353 /****************************************************************************/ /**
354 * @brief cache way disable set
355 *
356 * @param disableVal: cache way disable value
357 *
358 * @return SUCCESS or ERROR
359 *
360 *******************************************************************************/
361 #ifndef BFLB_USE_ROM_DRIVER
362 __WEAK
L1C_Set_Way_Disable(uint8_t disableVal)363 BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal)
364 {
365 uint32_t tmpVal = 0;
366
367 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
368 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
369 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
370
371 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
372 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS, disableVal);
373 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
374
375 if (disableVal != 0x0f) {
376 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
377 } else {
378 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
379 }
380
381 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
382
383 return SUCCESS;
384 }
385 #endif
386
387 /****************************************************************************/ /**
388 * @brief Set for ROM 2T access if CPU freq >120MHz
389 *
390 * @param enable: ENABLE or DISABLE
391 *
392 * @return SUCCESS or ERROR
393 *
394 *******************************************************************************/
395 #ifndef BFLB_USE_ROM_DRIVER
396 __WEAK
L1C_IROM_2T_Access_Set(uint8_t enable)397 BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable)
398 {
399 uint32_t tmpVal = 0;
400
401 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
402
403 if (enable) {
404 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS);
405 } else {
406 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS);
407 }
408
409 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
410
411 return SUCCESS;
412 }
413 #endif
414
415 /****************************************************************************/ /**
416 * @brief L1C BMX init
417 *
418 * @param l1cBmxCfg: L1C BMX config
419 *
420 * @return SUCCESS or ERROR
421 *
422 *******************************************************************************/
L1C_BMX_Init(L1C_BMX_Cfg_Type * l1cBmxCfg)423 BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg)
424 {
425 uint32_t tmpVal = 0;
426
427 CHECK_PARAM((l1cBmxCfg->timeoutEn) <= 0xF);
428
429 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
430 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_TIMEOUT_EN, l1cBmxCfg->timeoutEn);
431 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_EN, l1cBmxCfg->errEn);
432 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ARB_MODE, l1cBmxCfg->arbMod);
433 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
434
435 #ifndef BFLB_USE_HAL_DRIVER
436 Interrupt_Handler_Register(L1C_BMX_ERR_IRQn, L1C_BMX_ERR_IRQHandler);
437 Interrupt_Handler_Register(L1C_BMX_TO_IRQn, L1C_BMX_TO_IRQHandler);
438 #endif
439
440 return SUCCESS;
441 }
442
443 /****************************************************************************/ /**
444 * @brief L1C BMX address monitor enable
445 *
446 * @param None
447 *
448 * @return SUCCESS or ERROR
449 *
450 *******************************************************************************/
L1C_BMX_Addr_Monitor_Enable(void)451 BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void)
452 {
453 uint32_t tmpVal = 0;
454
455 tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
456 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS);
457 BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal);
458
459 return SUCCESS;
460 }
461
462 /****************************************************************************/ /**
463 * @brief L1C BMX address monitor disable
464 *
465 * @param None
466 *
467 * @return SUCCESS or ERROR
468 *
469 *******************************************************************************/
L1C_BMX_Addr_Monitor_Disable(void)470 BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void)
471 {
472 uint32_t tmpVal = 0;
473
474 tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
475 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS);
476 BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal);
477
478 return SUCCESS;
479 }
480
481 /****************************************************************************/ /**
482 * @brief L1C BMX bus error response enable
483 *
484 * @param None
485 *
486 * @return SUCCESS or ERROR
487 *
488 *******************************************************************************/
L1C_BMX_BusErrResponse_Enable(void)489 BL_Err_Type L1C_BMX_BusErrResponse_Enable(void)
490 {
491 uint32_t tmpVal = 0;
492
493 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
494 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_EN);
495 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
496
497 return SUCCESS;
498 }
499
500 /****************************************************************************/ /**
501 * @brief L1C BMX bus error response disable
502 *
503 * @param None
504 *
505 * @return SUCCESS or ERROR
506 *
507 *******************************************************************************/
L1C_BMX_BusErrResponse_Disable(void)508 BL_Err_Type L1C_BMX_BusErrResponse_Disable(void)
509 {
510 uint32_t tmpVal = 0;
511
512 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
513 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_EN);
514 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
515
516 return SUCCESS;
517 }
518
519 /****************************************************************************/ /**
520 * @brief Get L1C BMX error status
521 *
522 * @param errType: L1C BMX error status type
523 *
524 * @return SET or RESET
525 *
526 *******************************************************************************/
L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType)527 BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType)
528 {
529 uint32_t tmpVal = 0;
530
531 CHECK_PARAM(IS_L1C_BMX_BUS_ERR_TYPE(errType));
532
533 tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
534
535 if (errType == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) {
536 return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_TZ) ? SET : RESET;
537 } else {
538 return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_DEC) ? SET : RESET;
539 }
540 }
541
542 /****************************************************************************/ /**
543 * @brief Get L1C BMX error address
544 *
545 * @param None
546 *
547 * @return NP L1C BMX error address
548 *
549 *******************************************************************************/
L1C_BMX_Get_Err_Addr(void)550 uint32_t L1C_BMX_Get_Err_Addr(void)
551 {
552 return BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR);
553 }
554
555 /****************************************************************************/ /**
556 * @brief L1C BMX error interrupt callback install
557 *
558 * @param intType: L1C BMX error interrupt type
559 * @param cbFun: callback
560 *
561 * @return SUCCESS or ERROR
562 *
563 *******************************************************************************/
L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType,intCallback_Type * cbFun)564 BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun)
565 {
566 CHECK_PARAM(IS_L1C_BMX_ERR_INT_TYPE(intType));
567
568 l1cBmxErrIntCbfArra[intType] = cbFun;
569
570 return SUCCESS;
571 }
572
573 /****************************************************************************/ /**
574 * @brief L1C BMX ERR interrupt IRQ handler
575 *
576 * @param None
577 *
578 * @return None
579 *
580 *******************************************************************************/
581 #ifndef BFLB_USE_HAL_DRIVER
L1C_BMX_ERR_IRQHandler(void)582 void L1C_BMX_ERR_IRQHandler(void)
583 {
584 L1C_BMX_ERR_INT_Type intType;
585
586 for (intType = L1C_BMX_ERR_INT_ERR; intType < L1C_BMX_ERR_INT_ALL; intType++) {
587 if (l1cBmxErrIntCbfArra[intType] != NULL) {
588 l1cBmxErrIntCbfArra[intType]();
589 }
590 }
591
592 while (1) {
593 //MSG("L1C_BMX_ERR_IRQHandler\r\n");
594 BL702_Delay_MS(1000);
595 }
596 }
597 #endif
598
599 /****************************************************************************/ /**
600 * @brief L1C BMX timeout interrupt callback install
601 *
602 * @param intType: L1C BMX timeout interrupt type
603 * @param cbFun: callback
604 *
605 * @return SUCCESS or ERROR
606 *
607 *******************************************************************************/
L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType,intCallback_Type * cbFun)608 BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, intCallback_Type *cbFun)
609 {
610 CHECK_PARAM(IS_L1C_BMX_TO_INT_TYPE(intType));
611
612 l1cBmxToIntCbfArra[intType] = cbFun;
613
614 return SUCCESS;
615 }
616
617 /****************************************************************************/ /**
618 * @brief L1C BMX Time Out interrupt IRQ handler
619 *
620 * @param None
621 *
622 * @return None
623 *
624 *******************************************************************************/
625 #ifndef BFLB_USE_HAL_DRIVER
L1C_BMX_TO_IRQHandler(void)626 void L1C_BMX_TO_IRQHandler(void)
627 {
628 L1C_BMX_TO_INT_Type intType;
629
630 for (intType = L1C_BMX_TO_INT_TIMEOUT; intType < L1C_BMX_TO_INT_ALL; intType++) {
631 if (l1cBmxToIntCbfArra[intType] != NULL) {
632 l1cBmxToIntCbfArra[intType]();
633 }
634 }
635
636 while (1) {
637 //MSG("L1C_BMX_TO_IRQHandler\r\n");
638 BL702_Delay_MS(1000);
639 }
640 }
641 #endif
642
643 /*@} end of group L1C_Public_Functions */
644
645 /*@} end of group L1C */
646
647 /*@} end of group BL702_Peripheral_Driver */
648