1 /**
2 ******************************************************************************
3 * @file bl808_aon.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl808_aon.h"
38
39 /** @addtogroup BL808_Peripheral_Driver
40 * @{
41 */
42
43 /** @addtogroup AON
44 * @{
45 */
46
47 /** @defgroup AON_Private_Macros
48 * @{
49 */
50 #define AON_CLK_SET_DUMMY_WAIT \
51 { \
52 __NOP(); \
53 __NOP(); \
54 __NOP(); \
55 __NOP(); \
56 __NOP(); \
57 __NOP(); \
58 __NOP(); \
59 __NOP(); \
60 }
61
62 /*@} end of group AON_Private_Macros */
63
64 /** @defgroup AON_Private_Types
65 * @{
66 */
67
68 /*@} end of group AON_Private_Types */
69
70 /** @defgroup AON_Private_Variables
71 * @{
72 */
73
74 /*@} end of group AON_Private_Variables */
75
76 /** @defgroup AON_Global_Variables
77 * @{
78 */
79
80 /*@} end of group AON_Global_Variables */
81
82 /** @defgroup AON_Private_Fun_Declaration
83 * @{
84 */
85
86 /*@} end of group AON_Private_Fun_Declaration */
87
88 /** @defgroup AON_Private_Functions
89 * @{
90 */
91
92 /*@} end of group AON_Private_Functions */
93
94 /** @defgroup AON_Public_Functions
95 * @{
96 */
97
98 /****************************************************************************/ /**
99 * @brief Power on MXX band gap
100 *
101 * @param None
102 *
103 * @return SUCCESS or ERROR
104 *
105 *******************************************************************************/
AON_Power_On_MBG(void)106 BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
107 {
108 uint32_t tmpVal = 0;
109
110 /* Power up RF for PLL to work */
111 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
112 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
113 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
114
115 arch_delay_us(55);
116
117 return SUCCESS;
118 }
119
120 /****************************************************************************/ /**
121 * @brief Power off MXX band gap
122 *
123 * @param None
124 *
125 * @return SUCCESS or ERROR
126 *
127 *******************************************************************************/
AON_Power_Off_MBG(void)128 BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
129 {
130 uint32_t tmpVal = 0;
131
132 /* Power OFF */
133 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
134 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
135 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
136
137 return SUCCESS;
138 }
139
140 /****************************************************************************/ /**
141 * @brief Power on XTAL
142 *
143 * @param None
144 *
145 * @return SUCCESS or ERROR
146 *
147 *******************************************************************************/
AON_Power_On_XTAL(void)148 BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
149 {
150 uint32_t tmpVal = 0;
151 uint32_t timeOut = 0;
152
153 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
154 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON);
155 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
156 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
157
158 /* Polling for ready */
159 do {
160 arch_delay_us(10);
161 timeOut++;
162 tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
163 } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120);
164
165 if (timeOut >= 120) {
166 return TIMEOUT;
167 }
168
169 return SUCCESS;
170 }
171
172 /****************************************************************************/ /**
173 * @brief Set XTAL cap code
174 *
175 * @param capIn: Cap code in
176 * @param capOut: Cap code out
177 *
178 * @return SUCCESS or ERROR
179 *
180 *******************************************************************************/
AON_Set_Xtal_CapCode(uint8_t capIn,uint8_t capOut)181 BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
182 {
183 uint32_t tmpVal = 0;
184
185 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
186 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn);
187 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut);
188 BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
189
190 arch_delay_us(100);
191
192 return SUCCESS;
193 }
194
195 /****************************************************************************/ /**
196 * @brief Get XTAL cap code
197 *
198 * @param None
199 *
200 * @return Cap code
201 *
202 *******************************************************************************/
AON_Get_Xtal_CapCode(void)203 uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
204 {
205 uint32_t tmpVal = 0;
206
207 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
208
209 return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);
210 }
211
212 /****************************************************************************/ /**
213 * @brief Power off XTAL
214 *
215 * @param None
216 *
217 * @return SUCCESS or ERROR
218 *
219 *******************************************************************************/
AON_Power_Off_XTAL(void)220 BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
221 {
222 uint32_t tmpVal = 0;
223
224 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
225 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON);
226 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
227 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
228
229 return SUCCESS;
230 }
231
232 /****************************************************************************/ /**
233 * @brief Power on bandgap system
234 *
235 * @param None
236 *
237 * @return SUCCESS or ERROR
238 *
239 *******************************************************************************/
AON_Power_On_BG(void)240 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
241 {
242 uint32_t tmpVal = 0;
243
244 /* power up RF for PLL to work */
245 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
246 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
247 BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
248
249 arch_delay_us(55);
250
251 return SUCCESS;
252 }
253
254 /****************************************************************************/ /**
255 * @brief Power off bandgap system
256 *
257 * @param None
258 *
259 * @return SUCCESS or ERROR
260 *
261 *******************************************************************************/
AON_Power_Off_BG(void)262 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
263 {
264 uint32_t tmpVal = 0;
265
266 /* power up RF for PLL to work */
267 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
268 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
269 BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
270
271 arch_delay_us(55);
272
273 return SUCCESS;
274 }
275
276 /****************************************************************************/ /**
277 * @brief trim dcdc11 vout
278 *
279 * @param None
280 *
281 * @return SUCCESS or ERROR
282 *
283 *******************************************************************************/
AON_Trim_DCDC11_Vout(void)284 BL_Err_Type ATTR_CLOCK_SECTION AON_Trim_DCDC11_Vout(void)
285 {
286 Efuse_Ana_DCDC11_Trim_Type trim;
287 uint32_t tmpVal = 0;
288
289 EF_Ctrl_Read_DCDC11_Trim(&trim);
290 if (trim.trimDcdc11VoutAonEn) {
291 if (trim.trimDcdc11VoutAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimDcdc11VoutAon, 4)) {
292 tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0);
293 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC11_VOUT_TRIM_AON, trim.trimDcdc11VoutAon);
294 BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal);
295 return SUCCESS;
296 }
297 }
298
299 return ERROR;
300 }
301
302 /****************************************************************************/ /**
303 * @brief trim dcdc18 vout
304 *
305 * @param None
306 *
307 * @return SUCCESS or ERROR
308 *
309 *******************************************************************************/
AON_Trim_DCDC18_Vout(void)310 BL_Err_Type ATTR_CLOCK_SECTION AON_Trim_DCDC18_Vout(void)
311 {
312 Efuse_Ana_DCDC18_Trim_Type trim;
313 uint32_t tmpVal = 0;
314
315 EF_Ctrl_Read_DCDC18_Trim(&trim);
316 if (trim.trimDcdc18VoutAonEn) {
317 if (trim.trimDcdc18VoutAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimDcdc18VoutAon, 4)) {
318 tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_0);
319 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VOUT_TRIM_AON, trim.trimDcdc18VoutAon);
320 BL_WR_REG(AON_BASE, AON_DCDC18_TOP_0, tmpVal);
321 return SUCCESS;
322 }
323 }
324
325 return ERROR;
326 }
327
328 /****************************************************************************/ /**
329 * @brief trim usb20 rcal vout
330 *
331 * @param None
332 *
333 * @return SUCCESS or ERROR
334 *
335 *******************************************************************************/
AON_Trim_USB20_RCAL(void)336 BL_Err_Type ATTR_CLOCK_SECTION AON_Trim_USB20_RCAL(void)
337 {
338 Efuse_Ana_USB20RCAL_Trim_Type trim;
339 uint32_t tmpVal = 0;
340
341 //EF_Ctrl_Read_USB20RCAL_Trim(&trim); //FixZc
342 if (trim.trimUsb20rcalAonEn) {
343 if (trim.trimUsb20rcalAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimUsb20rcalAon, 6)) {
344 tmpVal = BL_RD_REG(AON_BASE, AON_PSW_IRRCV);
345 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_USB20_RCAL_CODE_AON, trim.trimUsb20rcalAon);
346 BL_WR_REG(AON_BASE, AON_PSW_IRRCV, tmpVal);
347 return SUCCESS;
348 }
349 }
350
351 return ERROR;
352 }
353
354 /****************************************************************************/ /**
355 * @brief Power on LDO15_RF
356 *
357 * @param None
358 *
359 * @return SUCCESS or ERROR
360 *
361 *******************************************************************************/
AON_Power_On_LDO15_RF(void)362 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
363 {
364 uint32_t tmpVal = 0;
365
366 /* ldo15rf power on */
367 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
368 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
369 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
370
371 arch_delay_us(90);
372
373 return SUCCESS;
374 }
375
376 /****************************************************************************/ /**
377 * @brief Power off LDO15_RF
378 *
379 * @param None
380 *
381 * @return SUCCESS or ERROR
382 *
383 *******************************************************************************/
AON_Power_Off_LDO15_RF(void)384 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
385 {
386 uint32_t tmpVal = 0;
387
388 /* ldo15rf power off */
389 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
390 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
391 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
392
393 return SUCCESS;
394 }
395
396 /****************************************************************************/ /**
397 * @brief power on source follow regular
398 *
399 * @param None
400 *
401 * @return SUCCESS or ERROR
402 *
403 *******************************************************************************/
AON_Power_On_SFReg(void)404 BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
405 {
406 uint32_t tmpVal = 0;
407
408 /* power on sfreg */
409 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
410 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
411 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
412
413 arch_delay_us(10);
414
415 return SUCCESS;
416 }
417
418 /****************************************************************************/ /**
419 * @brief power off source follow regular
420 *
421 * @param None
422 *
423 * @return SUCCESS or ERROR
424 *
425 *******************************************************************************/
AON_Power_Off_SFReg(void)426 BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
427 {
428 uint32_t tmpVal = 0;
429
430 /* power off sfreg */
431 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
432 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
433 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
434
435 return SUCCESS;
436 }
437
438 /****************************************************************************/ /**
439 * @brief Power off the power can be shut down in PDS0
440 *
441 * @param None
442 *
443 * @return SUCCESS or ERROR
444 *
445 *******************************************************************************/
AON_LowPower_Enter_PDS0(void)446 BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
447 {
448 uint32_t tmpVal = 0;
449
450 /* power off sfreg */
451 tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
452 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
453 BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
454
455 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
456 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
457 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
458 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
459 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
460
461 /* gating Clock */
462 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
463 tmpVal = tmpVal & (~(1 << 6));
464 tmpVal = tmpVal & (~(1 << 7));
465 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
466
467 return SUCCESS;
468 }
469
470 /****************************************************************************/ /**
471 * @brief Power on the power powered down in PDS0
472 *
473 * @param None
474 *
475 * @return SUCCESS or ERROR
476 *
477 *******************************************************************************/
AON_LowPower_Exit_PDS0(void)478 BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
479 {
480 uint32_t tmpVal = 0;
481
482 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
483
484 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
485 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
486
487 arch_delay_us(20);
488
489 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
490 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
491
492 arch_delay_us(60);
493
494 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
495 BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
496
497 arch_delay_us(20);
498
499 /* power on wb */
500 tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
501 tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
502 BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
503
504 /* ungating Clock */
505 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
506 tmpVal = tmpVal | ((1 << 6));
507 tmpVal = tmpVal | ((1 << 7));
508 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
509
510 return SUCCESS;
511 }
512
513 /****************************************************************************/ /**
514 * @brief AON set DCDC11_Top voltage out
515 *
516 * @param dcdcLevel: DCDC11_Top volatge level
517 *
518 * @return SUCCESS or ERROR
519 *
520 *******************************************************************************/
AON_Set_DCDC11_Top_Vout(AON_DCDC_LEVEL_Type dcdcLevel)521 BL_Err_Type ATTR_TCM_SECTION AON_Set_DCDC11_Top_Vout(AON_DCDC_LEVEL_Type dcdcLevel)
522 {
523 uint32_t tmpVal;
524
525 CHECK_PARAM(IS_AON_DCDC_LEVEL_TYPE(dcdcLevel));
526
527 tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0);
528 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC11_VOUT_SEL_AON, dcdcLevel);
529 BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal);
530
531 return SUCCESS;
532 }
533 /*@} end of group AON_Public_Functions */
534
535 /*@} end of group AON */
536
537 /*@} end of group BL808_Peripheral_Driver */
538