1 #include "bl808_common.h"
2 #include "bl808_glb.h"
3 #include "bl808_clock.h"
4
5 /** @addtogroup BL808_Periph_Driver
6 * @{
7 */
8
9 /** @defgroup DRIVER_COMMON DRIVER_COMMON
10 * @brief Digger driver common functions
11 * @{
12 */
13
14 /** @defgroup DRIVER_Private_Type
15 * @{
16 */
17
18 /*@} end of group DRIVER_Private_Type*/
19
20 /** @defgroup DRIVER_Private_Defines
21 * @{
22 */
23
24 /*@} end of group DRIVER_Private_Defines */
25
26 /** @defgroup DRIVER_Private_Variables
27 * @{
28 */
29
30 /*@} end of group DRIVER_Private_Variables */
31
32 /** @defgroup DRIVER_Global_Variables
33 * @{
34 */
35
36 /*@} end of group DRIVER_Global_Variables */
37
38 /** @defgroup DRIVER_Private_FunctionDeclaration
39 * @{
40 */
41
42 /*@} end of group DRIVER_Private_FunctionDeclaration */
43
44 /** @defgroup DRIVER_Private_Functions
45 * @{
46 */
47
48 /*@} end of group DRIVER_Private_Functions */
49
50 /** @defgroup DRIVER_Public_Functions
51 * @{
52 */
53
54 /****************************************************************************/ /**
55 * @brief delay us
56 *
57 * @param[in] core: systemcoreclock
58 *
59 * @param[in] cnt: delay cnt us
60 *
61 * @return none
62 *
63 *******************************************************************************/
64 #ifndef BFLB_USE_ROM_DRIVER
65 #ifdef ARCH_RISCV
66 __WEAK
ASM_Delay_Us(uint32_t core,uint32_t cnt,uint32_t loopT)67 void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT)
68 {
69 volatile uint32_t divVal = loopT;
70 volatile uint32_t speed = 0;
71 volatile uint32_t cycNum = 0;
72
73 /* 1M=100K*10, so multiple is 10 */
74 /* loop function take 4 instructions, so instructionNum is 4 */
75 /* divVal = multiple*instructionNum */
76
77 if (core >= 1 * 1000 * 1000) {
78 /* CPU clock >= 1MHz */
79 speed = core / (100 * 1000);
80 cycNum = speed * cnt;
81 cycNum = cycNum / 10;
82 cycNum = cycNum / divVal;
83 /* cycNum >= 0 */
84 } else {
85 /* CPU clock < 1MHz */
86 speed = core / 1000;
87 cycNum = speed * cnt;
88 cycNum = cycNum / 1000;
89 cycNum = cycNum / divVal;
90 /* cycNum >= 0 */
91 }
92
93 if (!cycNum) {
94 return;
95 }
96
97 __asm__ __volatile__(
98 "mv a4,%0\n\t"
99 "li a5,0x0\n\t"
100 "nop\n\t"
101 "nop\n\t"
102 "nop\n\t"
103 ".align 4\n\t"
104 "1 :\n"
105 "beq a5,a4,2f\n\t"
106 "addi a5,a5,0x1\n\t"
107 "lui a3,0xF0000\n\t"
108 "lw a3,0(a3)\n\t"
109 "j 1b\n\t"
110 "nop\n\t"
111 "nop\n\t"
112 "2 :\n\t"
113 "nop\n"
114 : /* output */
115 : "r"(cycNum) /* input */
116 : "a3", "a4", "a5" /* destruct description */
117 );
118 }
119 #endif
120 #endif
121
122 /****************************************************************************/ /**
123 * @brief delay us
124 *
125 * @param[in] cnt: delay cnt us
126 *
127 * @return none
128 *
129 *******************************************************************************/
130 #ifndef BFLB_USE_ROM_DRIVER
131 const uint32_t ATTR_TCM_CONST_SECTION m0Cyc00[] = {46,46,66,69};
132 const uint32_t ATTR_TCM_CONST_SECTION m0Cyc10[] = {10,10,66,69};
133 const uint32_t ATTR_TCM_CONST_SECTION m0Cyc11[] = {10,10,66,69};
134 const uint32_t ATTR_TCM_CONST_SECTION d0Cyc00[] = { 5, 5,62,34};
135 const uint32_t ATTR_TCM_CONST_SECTION d0Cyc11[] = { 5, 5,13,13};
136 const uint32_t ATTR_TCM_CONST_SECTION lpCyc00[] = { 6, 6,55,85};
137 __WEAK
arch_delay_us(uint32_t cnt)138 void ATTR_TCM_SECTION arch_delay_us(uint32_t cnt)
139 {
140 GLB_CORE_ID_Type coreID;
141 uint32_t coreFreq;
142 uint32_t loopTick = 5;
143 const uint32_t *pCyc = NULL;
144 uint32_t iCacheEn = 1;
145 uint32_t dCacheEn = 1;
146
147 /* requirement: icache enable && dcache enable */
148 /* otherwise the latency depends on the code address */
149
150 coreID = GLB_Get_Core_Type();
151
152 if(GLB_CORE_ID_M0 == coreID){
153 coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
154 #ifdef __RV32
155 iCacheEn = (__get_MHCR() & CLIC_INTIE_IE_Msk) >> CLIC_INTIE_IE_Pos;
156 dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos;
157 #endif
158 if(iCacheEn && dCacheEn){
159 pCyc = m0Cyc11;
160 }else if(iCacheEn && !dCacheEn){
161 pCyc = m0Cyc10;
162 }else if(!iCacheEn && !dCacheEn){
163 pCyc = m0Cyc00;
164 }else{
165 pCyc = m0Cyc11;
166 }
167 }else if(GLB_CORE_ID_D0 == coreID){
168 coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK);
169 #ifdef __RV64
170 iCacheEn = (__get_MHCR() & CACHE_MHCR_IE_Msk) >> CACHE_MHCR_IE_Pos;
171 dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos;
172 #endif
173 if(iCacheEn && dCacheEn){
174 pCyc = d0Cyc11;
175 }else if(!iCacheEn && !dCacheEn){
176 pCyc = d0Cyc00;
177 }else{
178 pCyc = d0Cyc11;
179 }
180 }else if(GLB_CORE_ID_LP == coreID){
181 coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK);
182 pCyc = lpCyc00;
183 }else{
184 coreFreq = 32 * 1000 * 1000;
185 pCyc = lpCyc00;
186 }
187
188 switch(((uint32_t)(uintptr_t)&ASM_Delay_Us)>>24){
189 case 0x22:
190 loopTick = pCyc[0];
191 break;
192 case 0x62:
193 loopTick = pCyc[0];
194 break;
195 case 0x3F:
196 loopTick = pCyc[2];
197 break;
198 case 0x3E:
199 loopTick = pCyc[3];
200 break;
201 default :
202 break;
203 }
204
205 coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);
206
207 ASM_Delay_Us(coreFreq, cnt, loopTick);
208 }
209 #endif
210
211 /****************************************************************************/ /**
212 * @brief delay ms
213 *
214 * @param[in] cnt: delay cnt ms
215 *
216 * @return none
217 *
218 *******************************************************************************/
219 #ifndef BFLB_USE_ROM_DRIVER
220 __WEAK
arch_delay_ms(uint32_t cnt)221 void ATTR_TCM_SECTION arch_delay_ms(uint32_t cnt)
222 {
223 uint32_t i = 0;
224 uint32_t count = 0;
225
226 if (cnt >= 1024) {
227 /* delay (n*1024) ms */
228 for (i = 0; i < (cnt / 1024); i++) {
229 arch_delay_us(1024 * 1000);
230 }
231 }
232
233 count = cnt & 0x3FF;
234
235 if (count) {
236 /* delay (1-1023)ms */
237 arch_delay_us(count * 1000);
238 }
239 }
240 #endif
241
242 #ifdef DEBUG
243 /*******************************************************************************
244 * @brief Reports the name of the source file and the source line number
245 * where the CHECK_PARAM error has occurred.
246
247 * @param file: Pointer to the source file name
248 * @param line: assert_param error line source number
249
250 * @return None
251 *******************************************************************************/
check_failed(uint8_t * file,uint32_t line)252 void ATTR_TCM_SECTION check_failed(uint8_t *file, uint32_t line)
253 {
254 /* Infinite loop */
255 while (1)
256 ;
257 }
258 #endif /* DEBUG */
259
260 /****************************************************************************/ /**
261 * @brief MM_Sys All interrupt handler
262 *
263 * @param None
264 *
265 * @return None
266 *
267 *******************************************************************************/
268 #if defined(CPU_M0) || defined(CPU_LP)
269 #ifndef BFLB_USE_HAL_DRIVER
270 void AWB2_IRQHandler(void);
271 void UART4_IRQHandler(void);
272 void UART3_IRQHandler(void);
273 void I2C2_IRQHandler(void);
274 void I2C3_IRQHandler(void);
275 void SPI1_IRQHandler(void);
276 void AE_IRQHandler(void);
277 void AWB0_IRQHandler(void);
278 void SEOF0_IRQHandler(void);
279 void SEOF1_IRQHandler(void);
280 void SEOF2_IRQHandler(void);
281 void CAM0_IRQHandler(void);
282 void CAM1_IRQHandler(void);
283 void CAM2_IRQHandler(void);
284 void CAM3_IRQHandler(void);
285 void MJPEG_IRQHandler(void);
286 void DMA2_INT0_IRQHandler(void);
287 void DMA2_INT1_IRQHandler(void);
288 void DMA2_INT2_IRQHandler(void);
289 void DMA2_INT3_IRQHandler(void);
290 void DMA2_INT4_IRQHandler(void);
291 void DMA2_INT5_IRQHandler(void);
292 void DMA2_INT6_IRQHandler(void);
293 void DMA2_INT7_IRQHandler(void);
294 void IPC_D0_IRQHandler(void);
295 void MJDEC_IRQHandler(void);
296 void CAM4_IRQHandler(void);
297 void CAM5_IRQHandler(void);
298 void CAM6_IRQHandler(void);
299 void CAM7_IRQHandler(void);
300 void DMA2D_INT0_IRQHandler(void);
301 void DMA2D_INT1_IRQHandler(void);
302 void Display_IRQHandler(void);
303 void PWM_IRQHandler(void);
304 void SEOF3_IRQHandler(void);
305 void DBI_IRQHandler(void);
306 void WDR_IRQHandler(void);
307 void OSD_PB_IRQHandler(void);
308 void AWB1_IRQHandler(void);
309 void DSI_IRQHandler(void);
310 void AE_HIST_IRQHandler(void);
311 void TIMER1_CH0_IRQHandler(void);
312 void TIMER1_CH1_IRQHandler(void);
313 void TIMER1_WDT_IRQHandler(void);
314 void AUDIO_IRQHandler(void);
315
316
317
C906_ALL_IRQHandler(void)318 void C906_ALL_IRQHandler(void)
319 {
320 AWB2_IRQHandler();
321 UART4_IRQHandler();
322 UART3_IRQHandler();
323 I2C2_IRQHandler();
324 I2C3_IRQHandler();
325 SPI1_IRQHandler();
326 AE_IRQHandler();
327 AWB0_IRQHandler();
328 SEOF0_IRQHandler();
329 SEOF1_IRQHandler();
330 SEOF2_IRQHandler();
331 CAM0_IRQHandler();
332 CAM1_IRQHandler();
333 CAM2_IRQHandler();
334 CAM3_IRQHandler();
335 MJPEG_IRQHandler();
336 DMA2_INT0_IRQHandler();
337 DMA2_INT1_IRQHandler();
338 DMA2_INT2_IRQHandler();
339 DMA2_INT3_IRQHandler();
340 DMA2_INT4_IRQHandler();
341 DMA2_INT5_IRQHandler();
342 DMA2_INT6_IRQHandler();
343 DMA2_INT7_IRQHandler();
344 IPC_D0_IRQHandler();
345 MJDEC_IRQHandler();
346 CAM4_IRQHandler();
347 CAM5_IRQHandler();
348 CAM6_IRQHandler();
349 CAM7_IRQHandler();
350 DMA2D_INT0_IRQHandler();
351 DMA2D_INT1_IRQHandler();
352 Display_IRQHandler();
353 PWM_IRQHandler();
354 SEOF3_IRQHandler();
355 DBI_IRQHandler();
356 WDR_IRQHandler();
357 OSD_PB_IRQHandler();
358 AWB1_IRQHandler();
359 DSI_IRQHandler();
360 AE_HIST_IRQHandler();
361 TIMER1_CH0_IRQHandler();
362 TIMER1_CH1_IRQHandler();
363 TIMER1_WDT_IRQHandler();
364 AUDIO_IRQHandler();
365 }
366 #endif
367 #endif
368
369 /****************************************************************************/ /**
370 * @brief Enable MM_Sys All interrupt
371 *
372 * @param None
373 *
374 * @return None
375 *
376 *******************************************************************************/
377 #if defined(CPU_M0) || defined(CPU_LP)
C906_All_Int_Enable(void)378 void C906_All_Int_Enable(void)
379 {
380 #ifndef BFLB_USE_HAL_DRIVER
381 Interrupt_Handler_Register(MM_ALL_IRQn, C906_ALL_IRQHandler);
382 #endif
383 CPU_Interrupt_Enable(MM_ALL_IRQn);
384 }
385 #endif
386
387 /****************************************************************************/ /**
388 * @brief Dsiable MM_Sys All interrupt
389 *
390 * @param None
391 *
392 * @return None
393 *
394 *******************************************************************************/
395 #if defined(CPU_M0) || defined(CPU_LP)
C906_All_Int_Disable(void)396 void C906_All_Int_Disable(void)
397 {
398 CPU_Interrupt_Disable(MM_ALL_IRQn);
399 }
400 #endif
401
402 /*@} end of group DRIVER_Public_Functions */
403
404 /*@} end of group DRIVER_COMMON */
405
406 /*@} end of group BL808_Periph_Driver */
407