1 /**
2 ******************************************************************************
3 * @file bl808_glb_gpio.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl808_clock.h"
38 #include "bl808_glb.h"
39 #include "bl808_hbn.h"
40 #include "bl808_pds.h"
41 #include "bl808_glb_gpio.h"
42
43 /** @addtogroup BL808_Peripheral_Driver
44 * @{
45 */
46
47 /** @addtogroup GLB_GPIO
48 * @{
49 */
50
51 /** @defgroup GLB_GPIO_Private_Macros
52 * @{
53 */
54 #define GLB_GPIO_INT0_NUM (GLB_GPIO_PIN_MAX)
55 #define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)
56
57 /*@} end of group GLB_GPIO_Private_Macros */
58 #define GLB_GPIO_TIMEOUT_COUNT (320 * 1000)
59 /** @defgroup GLB_GPIO_Private_Types
60 * @{
61 */
62
63 /*@} end of group GLB_GPIO_Private_Types */
64
65 /** @defgroup GLB_GPIO_Private_Variables
66 * @{
67 */
68
69 #ifndef BFLB_USE_HAL_DRIVER
70 static intCallback_Type *ATTR_TCM_CONST_SECTION glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL };
71
72 static intCallback_Type *ATTR_TCM_CONST_SECTION glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_ALL] = { NULL };
73 #endif
74
75 /*@} end of group GLB_GPIO_Private_Variables */
76
77 /** @defgroup GLB_GPIO_Global_Variables
78 * @{
79 */
80
81 /*@} end of group GLB_GPIO_Global_Variables */
82
83 /** @defgroup GLB_GPIO_Private_Fun_Declaration
84 * @{
85 */
86
87 /*@} end of group GLB_GPIO_Private_Fun_Declaration */
88
89 /** @defgroup GLB_GPIO_Private_Functions
90 * @{
91 */
92
93 /*@} end of group GLB_GPIO_Private_Functions */
94
95 /** @defgroup GLB_GPIO_Public_Functions
96 * @{
97 */
98
99 /****************************************************************************/ /**
100 * @brief GPIO initialization
101 *
102 * @param cfg: GPIO configuration
103 *
104 * @return SUCCESS or ERROR
105 *
106 *******************************************************************************/
GLB_GPIO_Init(GLB_GPIO_Cfg_Type * cfg)107 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
108 {
109 uint8_t gpioPin = cfg->gpioPin;
110 uint32_t gpioCfgAddress;
111 uint32_t tmpVal;
112
113 /* drive strength(drive) = 0 <=> 8.0mA @ 3.3V */
114 /* drive strength(drive) = 1 <=> 9.6mA @ 3.3V */
115 /* drive strength(drive) = 2 <=> 11.2mA @ 3.3V */
116 /* drive strength(drive) = 3 <=> 12.8mA @ 3.3V */
117
118 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
119
120 /* Disable output anyway*/
121 tmpVal = BL_RD_WORD(gpioCfgAddress);
122 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
123 BL_WR_WORD(gpioCfgAddress, tmpVal);
124
125 /* input/output, pull up/down, drive, smt, function */
126 tmpVal = BL_RD_WORD(gpioCfgAddress);
127
128 if (cfg->gpioMode != GPIO_MODE_ANALOG) {
129 /* not analog mode */
130
131 if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
132 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
133 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
134 } else {
135 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
136 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
137 }
138
139 if (cfg->pullType == GPIO_PULL_UP) {
140 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
141 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
142 } else if (cfg->pullType == GPIO_PULL_DOWN) {
143 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
144 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
145 } else {
146 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
147 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
148 }
149 if (gpioPin == GLB_GPIO_PIN_40) {
150 *(uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0_OFFSET) &= ~(1 << 27);
151 } else if (gpioPin == GLB_GPIO_PIN_41) {
152 *(uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0_OFFSET) &= ~(1 << 28);
153 }
154 } else {
155 /* analog mode */
156
157 /* clear ie && oe */
158 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
159 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
160
161 /* clear pu && pd */
162 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
163 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
164 }
165
166 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive);
167 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl);
168 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
169 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_MODE, cfg->outputMode);
170 BL_WR_WORD(gpioCfgAddress, tmpVal);
171
172 return SUCCESS;
173 }
174
175 /****************************************************************************/ /**
176 * @brief init GPIO function in pin list
177 *
178 * @param gpioFun: GPIO pin function
179 * @param pinList: GPIO pin list
180 * @param cnt: GPIO pin count
181 *
182 * @return SUCCESS or ERROR
183 *
184 *******************************************************************************/
GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun,GLB_GPIO_Type * pinList,uint8_t cnt)185 BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt)
186 {
187 GLB_GPIO_Cfg_Type gpioCfg = {
188 .gpioPin = GLB_GPIO_PIN_0,
189 .gpioFun = (uint8_t)gpioFun,
190 .gpioMode = GPIO_MODE_AF,
191 .pullType = GPIO_PULL_UP,
192 .drive = 1,
193 .smtCtrl = 1
194 };
195
196 if (gpioFun == GPIO_FUN_ANALOG) {
197 gpioCfg.gpioMode = GPIO_MODE_ANALOG;
198 }
199
200 for (uint8_t i = 0; i < cnt; i++) {
201 gpioCfg.gpioPin = pinList[i];
202 GLB_GPIO_Init(&gpioCfg);
203 }
204
205 return SUCCESS;
206 }
207
208 /****************************************************************************/ /**
209 * @brief GPIO set input function enable
210 *
211 * @param gpioPin: GPIO pin
212 *
213 * @return SUCCESS or ERROR
214 *
215 *******************************************************************************/
GLB_GPIO_Input_Enable(GLB_GPIO_Type gpioPin)216 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Input_Enable(GLB_GPIO_Type gpioPin)
217 {
218 uint32_t gpioCfgAddress;
219 uint32_t tmpVal;
220
221 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
222
223 tmpVal = BL_RD_WORD(gpioCfgAddress);
224 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
225 BL_WR_WORD(gpioCfgAddress, tmpVal);
226
227 return SUCCESS;
228 }
229
230 /****************************************************************************/ /**
231 * @brief Embedded flash set input function enable
232 *
233 * @param gpioPin: GPIO pin
234 *
235 * @return SUCCESS or ERROR
236 *
237 *******************************************************************************/
GLB_Embedded_Flash_Pad_Enable(void)238 BL_Err_Type ATTR_TCM_SECTION GLB_Embedded_Flash_Pad_Enable(void)
239 {
240 uint32_t gpioCfgAddress;
241 uint32_t tmpVal;
242 uint32_t gpioPin;
243
244 for (gpioPin = 48; gpioPin < 52; gpioPin++) {
245 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
246 tmpVal = BL_RD_WORD(gpioCfgAddress);
247 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
248 BL_WR_WORD(gpioCfgAddress, tmpVal);
249 }
250
251 return SUCCESS;
252 }
253
254 /****************************************************************************/ /**
255 * @brief GPIO set input function disable
256 *
257 * @param gpioPin: GPIO pin
258 *
259 * @return SUCCESS or ERROR
260 *
261 *******************************************************************************/
GLB_GPIO_Input_Disable(GLB_GPIO_Type gpioPin)262 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Input_Disable(GLB_GPIO_Type gpioPin)
263 {
264 uint32_t gpioCfgAddress;
265 uint32_t tmpVal;
266
267 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
268
269 tmpVal = BL_RD_WORD(gpioCfgAddress);
270 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
271 BL_WR_WORD(gpioCfgAddress, tmpVal);
272
273 return SUCCESS;
274 }
275
276 /****************************************************************************/ /**
277 * @brief GPIO set output function enable
278 *
279 * @param gpioPin: GPIO pin
280 *
281 * @return SUCCESS or ERROR
282 *
283 *******************************************************************************/
GLB_GPIO_Output_Enable(GLB_GPIO_Type gpioPin)284 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Output_Enable(GLB_GPIO_Type gpioPin)
285 {
286 uint32_t gpioCfgAddress;
287 uint32_t tmpVal;
288
289 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
290
291 tmpVal = BL_RD_WORD(gpioCfgAddress);
292 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
293 BL_WR_WORD(gpioCfgAddress, tmpVal);
294
295 return SUCCESS;
296 }
297
298 /****************************************************************************/ /**
299 * @brief GPIO set output function disable
300 *
301 * @param gpioPin: GPIO pin
302 *
303 * @return SUCCESS or ERROR
304 *
305 *******************************************************************************/
GLB_GPIO_Output_Disable(GLB_GPIO_Type gpioPin)306 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Output_Disable(GLB_GPIO_Type gpioPin)
307 {
308 uint32_t gpioCfgAddress;
309 uint32_t tmpVal;
310
311 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
312
313 tmpVal = BL_RD_WORD(gpioCfgAddress);
314 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
315 BL_WR_WORD(gpioCfgAddress, tmpVal);
316
317 return SUCCESS;
318 }
319
320 /****************************************************************************/ /**
321 * @brief GPIO set High-Z
322 *
323 * @param gpioPin: GPIO pin
324 *
325 * @return SUCCESS or ERROR
326 *
327 *******************************************************************************/
GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)328 BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
329 {
330 uint32_t gpioCfgAddress;
331 uint32_t tmpVal;
332
333 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
334
335 /* Disable output anyway*/
336 tmpVal = BL_RD_WORD(gpioCfgAddress);
337 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
338 BL_WR_WORD(gpioCfgAddress, tmpVal);
339
340 /* ie=0, oe=0, drive=0, smt=0, pu=1 (pull up), pd=0, func=swgpio */
341 tmpVal = BL_RD_WORD(gpioCfgAddress);
342 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
343 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
344 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, 0);
345 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, 0);
346 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); /* pull up */
347 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
348 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, 0xB);
349 BL_WR_WORD(gpioCfgAddress, tmpVal);
350
351 return SUCCESS;
352 }
353
354 /****************************************************************************/ /**
355 * @brief Get GPIO function
356 *
357 * @param gpioPin: GPIO type
358 *
359 * @return GPIO function
360 *
361 *******************************************************************************/
GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)362 uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)
363 {
364 uint32_t gpioCfgAddress;
365 uint32_t tmpVal;
366
367 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
368 tmpVal = BL_RD_WORD(gpioCfgAddress);
369
370 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL);
371 }
372
373 /****************************************************************************/ /**
374 * @brief Read GPIO
375 *
376 * @param gpioPin: GPIO type
377 *
378 * @return GPIO value
379 *
380 *******************************************************************************/
GLB_GPIO_Read(GLB_GPIO_Type gpioPin)381 uint32_t ATTR_TCM_SECTION GLB_GPIO_Read(GLB_GPIO_Type gpioPin)
382 {
383 uint32_t gpioCfgAddress;
384 uint32_t tmpVal;
385
386 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
387 tmpVal = BL_RD_WORD(gpioCfgAddress);
388
389 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_I) ? SET : RESET;
390 }
391
392 /****************************************************************************/ /**
393 * @brief Write GPIO
394 *
395 * @param gpioPin: GPIO type
396 * @param val: GPIO value
397 *
398 * @return SUCCESS or ERROR
399 *
400 *******************************************************************************/
GLB_GPIO_Write(GLB_GPIO_Type gpioPin,uint32_t val)401 BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val)
402 {
403 uint32_t gpioCfgAddress;
404 uint32_t tmpVal;
405
406 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
407 tmpVal = BL_RD_WORD(gpioCfgAddress);
408
409 if (val) {
410 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_O);
411 } else {
412 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_O);
413 }
414
415 BL_WR_WORD(gpioCfgAddress, tmpVal);
416
417 return SUCCESS;
418 }
419
420 /****************************************************************************/ /**
421 * @brief turn GPIO output high
422 *
423 * @param gpioPin: GPIO type
424 *
425 * @return SUCCESS or ERROR
426 *
427 *******************************************************************************/
GLB_GPIO_Set(GLB_GPIO_Type gpioPin)428 BL_Err_Type GLB_GPIO_Set(GLB_GPIO_Type gpioPin)
429 {
430 if (gpioPin < GLB_GPIO_PIN_32) {
431 BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG138_OFFSET, 1 << gpioPin);
432 } else {
433 BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG139_OFFSET, 1 << (gpioPin - GLB_GPIO_PIN_32));
434 }
435
436 return SUCCESS;
437 }
438
439 /****************************************************************************/ /**
440 * @brief turn GPIO output low
441 *
442 * @param gpioPin: GPIO type
443 *
444 * @return SUCCESS or ERROR
445 *
446 *******************************************************************************/
GLB_GPIO_Clr(GLB_GPIO_Type gpioPin)447 BL_Err_Type GLB_GPIO_Clr(GLB_GPIO_Type gpioPin)
448 {
449 if (gpioPin < GLB_GPIO_PIN_32) {
450 BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG140_OFFSET, 1 << gpioPin);
451 } else {
452 BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG141_OFFSET, 1 << (gpioPin - GLB_GPIO_PIN_32));
453 }
454
455 return SUCCESS;
456 }
457
458 /****************************************************************************/ /**
459 * @brief GPIO interrupt initialization
460 *
461 * @param intCfg: GPIO interrupt configuration
462 *
463 * @return SUCCESS or ERROR
464 *
465 *******************************************************************************/
GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type * intCfg)466 BL_Err_Type GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type *intCfg)
467 {
468 uint32_t gpioCfgAddress;
469 uint32_t tmpVal;
470 uint32_t gpioPin = intCfg->gpioPin;
471
472 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
473 tmpVal = BL_RD_WORD(gpioCfgAddress);
474 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MODE_SET, intCfg->trig);
475 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MASK, intCfg->intMask);
476 BL_WR_WORD(gpioCfgAddress, tmpVal);
477
478 return SUCCESS;
479 }
480
481 /****************************************************************************/ /**
482 * @brief Set GLB GPIO interrupt mask
483 *
484 * @param gpioPin: GPIO type
485 * @param intMask: GPIO interrupt MASK or UNMASK
486 *
487 * @return SUCCESS or ERROR
488 *
489 *******************************************************************************/
GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin,BL_Mask_Type intMask)490 BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask)
491 {
492 uint32_t gpioCfgAddress;
493 uint32_t tmpVal;
494
495 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
496 tmpVal = BL_RD_WORD(gpioCfgAddress);
497 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MASK, intMask);
498 BL_WR_WORD(gpioCfgAddress, tmpVal);
499
500 return SUCCESS;
501 }
502
503 /****************************************************************************/ /**
504 * @brief Get GLB GPIO interrupt status
505 *
506 * @param gpioPin: GPIO type
507 *
508 * @return SET or RESET
509 *
510 *******************************************************************************/
GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin)511 BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
512 {
513 uint32_t gpioCfgAddress;
514
515 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
516
517 return BL_GET_REG_BITS_VAL(BL_RD_WORD(gpioCfgAddress), GLB_GPIO_0_INT_STAT) ? SET : RESET;
518 }
519
520 /****************************************************************************/ /**
521 * @brief Clear GLB GPIO interrupt status
522 *
523 * @param gpioPin: GPIO type
524 *
525 * @return SUCCESS or ERROR
526 *
527 *******************************************************************************/
GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin)528 BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
529 {
530 uint32_t gpioCfgAddress;
531 uint32_t tmpVal;
532
533 gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
534
535 /* clr=1 */
536 tmpVal = BL_RD_WORD(gpioCfgAddress);
537 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_INT_CLR);
538 BL_WR_WORD(gpioCfgAddress, tmpVal);
539
540 /* clr=0 */
541 tmpVal = BL_RD_WORD(gpioCfgAddress);
542 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_INT_CLR);
543 BL_WR_WORD(gpioCfgAddress, tmpVal);
544
545 return SUCCESS;
546 }
547
548 #ifndef BFLB_USE_HAL_DRIVER
GPIO_FIFO_IRQHandler(void)549 void GPIO_FIFO_IRQHandler(void)
550 {
551 uint32_t tmpVal;
552
553 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
554
555 if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_END_MASK)) {
556 if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_END] != NULL) {
557 glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_END]();
558 }
559 }
560
561 if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_FER_MASK)) {
562 if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FER] != NULL) {
563 glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FER]();
564 }
565 }
566
567 if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK)) {
568 if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FIFO] != NULL) {
569 glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FIFO]();
570 }
571 }
572 }
573 #endif
574
575 /****************************************************************************/ /**
576 * @brief GPIO INT0 IRQHandler install
577 *
578 * @param None
579 *
580 * @return SUCCESS or ERROR
581 *
582 *******************************************************************************/
GLB_GPIO_INT0_IRQHandler_Install(void)583 BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void)
584 {
585 #ifndef BFLB_USE_HAL_DRIVER
586 Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler);
587 #endif
588
589 return SUCCESS;
590 }
591
GLB_GPIO_FIFO_IRQHandler_Install(void)592 BL_Err_Type GLB_GPIO_FIFO_IRQHandler_Install(void)
593 {
594 #ifndef BFLB_USE_HAL_DRIVER
595 Interrupt_Handler_Register(GPIO_DMA_IRQn, GPIO_FIFO_IRQHandler);
596 #endif
597
598 return SUCCESS;
599 }
600
601 /****************************************************************************/ /**
602 * @brief GPIO interrupt IRQ handler callback install
603 *
604 * @param gpioPin: GPIO pin type
605 * @param cbFun: callback function
606 *
607 * @return SUCCESS or ERROR
608 *
609 *******************************************************************************/
610 #ifndef BFLB_USE_HAL_DRIVER
GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin,intCallback_Type * cbFun)611 BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun)
612 {
613 if (gpioPin < GLB_GPIO_PIN_MAX) {
614 glbGpioInt0CbfArra[gpioPin] = cbFun;
615 }
616
617 return SUCCESS;
618 }
619 #endif
620 #ifndef BFLB_USE_HAL_DRIVER
GLB_GPIO_Fifo_Callback_Install(GLB_GPIO_FIFO_INT_Type intType,intCallback_Type * cbFun)621 BL_Err_Type GLB_GPIO_Fifo_Callback_Install(GLB_GPIO_FIFO_INT_Type intType, intCallback_Type *cbFun)
622 {
623 /* Check the parameters */
624 CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
625
626 glbGpioFifoCbfArra[intType] = cbFun;
627
628 return SUCCESS;
629 }
630 #endif
631
632 /****************************************************************************/ /**
633 * @brief GPIO interrupt IRQ handler
634 *
635 * @param None
636 *
637 * @return None
638 *
639 *******************************************************************************/
640 #ifndef BFLB_USE_HAL_DRIVER
GPIO_INT0_IRQHandler(void)641 void GPIO_INT0_IRQHandler(void)
642 {
643 GLB_GPIO_Type gpioPin;
644 uint32_t timeOut = 0;
645
646 for (gpioPin = GLB_GPIO_PIN_0; gpioPin < GLB_GPIO_PIN_MAX; gpioPin++) {
647 if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) {
648 GLB_Clr_GPIO_IntStatus(gpioPin);
649
650 /* timeout check */
651 timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
652
653 do {
654 timeOut--;
655 } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut);
656
657 if (!timeOut) {
658 //MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
659 }
660
661 if (glbGpioInt0CbfArra[gpioPin] != NULL) {
662 /* Call the callback function */
663 glbGpioInt0CbfArra[gpioPin]();
664 }
665 }
666 }
667 }
668 #endif
669
670 /****************************************************************************/ /**
671 * @brief GPIO fifo function initialization
672 *
673 * @param cfg: GPIO fifo configuration
674 *
675 * @return SUCCESS or ERROR
676 *
677 *******************************************************************************/
GLB_GPIO_Fifo_Init(GLB_GPIO_FIFO_CFG_Type * cfg)678 BL_Err_Type GLB_GPIO_Fifo_Init(GLB_GPIO_FIFO_CFG_Type *cfg)
679 {
680 uint32_t tmpVal;
681
682 /* Check the parameters */
683 CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->code0Phase));
684 CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->code1Phase));
685 CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->latch));
686
687 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
688 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_TX_EN, cfg->fifoDmaEnable);
689 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_TX_FIFO_TH, cfg->fifoDmaThreshold);
690 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_OUT_SEL_LATCH, cfg->latch);
691 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_PARK_VALUE, cfg->idle);
692 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
693 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);
694 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);
695
696 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);
697 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE0_HIGH_TIME, cfg->code0FirstTime);
698 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE1_HIGH_TIME, cfg->code1FirstTime);
699 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE_TOTAL_TIME, cfg->codeTotalTime);
700 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_INVERT_CODE0_HIGH, cfg->code0Phase);
701 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_INVERT_CODE1_HIGH, cfg->code1Phase);
702 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);
703 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);
704
705 GLB_GPIO_FIFO_IRQHandler_Install();
706
707 return SUCCESS;
708 }
709
710 /****************************************************************************/ /**
711 * @brief Push data to GPIO fifo
712 *
713 * @param data: the pointer of data buffer
714 * @param len: the len of data buffer
715 *
716 * @return SUCCESS or ERROR
717 *
718 *******************************************************************************/
GLB_GPIO_Fifo_Push(uint16_t * data,uint16_t len)719 BL_Err_Type GLB_GPIO_Fifo_Push(uint16_t *data, uint16_t len)
720 {
721 uint32_t txLen = 0;
722 uint32_t timeoutCnt = GLB_GPIO_TIMEOUT_COUNT;
723
724 while (txLen < len) {
725 if (GLB_GPIO_Fifo_GetCount() > 0) {
726 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG144, data[txLen++]);
727 timeoutCnt = GLB_GPIO_TIMEOUT_COUNT;
728 } else {
729 timeoutCnt--;
730
731 if (timeoutCnt == 0) {
732 return TIMEOUT;
733 }
734 }
735 }
736
737 return SUCCESS;
738 }
739
740 /****************************************************************************/ /**
741 * @brief Get GPIO fifo available count
742 *
743 * @param None
744 *
745 * @return The count of available count
746 *
747 *******************************************************************************/
GLB_GPIO_Fifo_GetCount(void)748 uint32_t GLB_GPIO_Fifo_GetCount(void)
749 {
750 return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO_TX_FIFO_CNT);
751 }
752
753 /****************************************************************************/ /**
754 * @brief Clear GPIO fifo
755 *
756 * @param None
757 *
758 * @return SUCCESS
759 *
760 *******************************************************************************/
GLB_GPIO_Fifo_Clear(void)761 BL_Err_Type GLB_GPIO_Fifo_Clear(void)
762 {
763 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, BL_SET_REG_BIT(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO_TX_FIFO_CLR));
764
765 return SUCCESS;
766 }
767
768 /****************************************************************************/ /**
769 * @brief Mask or Unmask GPIO FIFO Interrupt
770 *
771 * @param intType: interrupt type
772 * @param intMask: MASK or UNMASK
773 *
774 * @return SUCCESS or ERROR
775 *
776 *******************************************************************************/
GLB_GPIO_Fifo_IntMask(GLB_GPIO_FIFO_INT_Type intType,BL_Mask_Type intMask)777 BL_Err_Type GLB_GPIO_Fifo_IntMask(GLB_GPIO_FIFO_INT_Type intType, BL_Mask_Type intMask)
778 {
779 uint32_t tmpVal;
780
781 /* Check the parameters */
782 CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
783 CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
784
785 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
786
787 /* Mask or unmask certain or all interrupt */
788 if (MASK == intMask) {
789 switch (intType) {
790 case GLB_GPIO_FIFO_INT_FER:
791 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
792 break;
793
794 case GLB_GPIO_FIFO_INT_FIFO:
795 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
796 break;
797
798 case GLB_GPIO_FIFO_INT_END:
799 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
800 break;
801
802 case GLB_GPIO_FIFO_INT_ALL:
803 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
804 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
805 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
806 break;
807
808 default:
809 break;
810 }
811 } else {
812 switch (intType) {
813 case GLB_GPIO_FIFO_INT_FER:
814 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
815 break;
816
817 case GLB_GPIO_FIFO_INT_FIFO:
818 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
819 break;
820
821 case GLB_GPIO_FIFO_INT_END:
822 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
823 break;
824
825 case GLB_GPIO_FIFO_INT_ALL:
826 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
827 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
828 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
829 break;
830
831 default:
832 break;
833 }
834 }
835
836 /* Write back */
837 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);
838
839 return SUCCESS;
840 }
841
842 /****************************************************************************/ /**
843 * @brief Clear GPIO fifo interrupt
844 *
845 * @param intType: interrupt type
846 *
847 * @return SUCCESS or ERROR
848 *
849 *******************************************************************************/
GLB_GPIO_Fifo_IntClear(GLB_GPIO_FIFO_INT_Type intType)850 BL_Err_Type GLB_GPIO_Fifo_IntClear(GLB_GPIO_FIFO_INT_Type intType)
851 {
852 uint32_t tmpVal;
853
854 /* Check the parameters */
855 CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
856
857 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
858
859 /* Clear certain or all interrupt */
860 switch (intType) {
861 case GLB_GPIO_FIFO_INT_FER:
862 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
863 break;
864
865 case GLB_GPIO_FIFO_INT_FIFO:
866 //tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
867 break;
868
869 case GLB_GPIO_FIFO_INT_END:
870 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);
871 break;
872
873 case GLB_GPIO_FIFO_INT_ALL:
874 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
875 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);
876 break;
877
878 default:
879 break;
880 }
881
882 /* Write back */
883 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);
884
885 return SUCCESS;
886 }
887
888 /****************************************************************************/ /**
889 * @brief Get GPIO fifo interrupt status
890 *
891 * @param intType: interrupt type
892 *
893 * @return SUCCESS or ERROR
894 *
895 *******************************************************************************/
GLB_GPIO_Fifo_GetIntStatus(GLB_GPIO_FIFO_INT_Type intType)896 BL_Sts_Type GLB_GPIO_Fifo_GetIntStatus(GLB_GPIO_FIFO_INT_Type intType)
897 {
898 uint32_t tmpVal;
899
900 /* Check the parameters */
901 CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
902
903 /* Get certain or all interrupt status */
904 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
905
906 if (GLB_GPIO_FIFO_INT_ALL == intType) {
907 if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) ||
908 BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) ||
909 BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT)) {
910 return SET;
911 } else {
912 return RESET;
913 }
914 } else {
915 switch (intType) {
916 case GLB_GPIO_FIFO_INT_FER:
917 return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT);
918
919 case GLB_GPIO_FIFO_INT_FIFO:
920 return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT);
921
922 case GLB_GPIO_FIFO_INT_END:
923 return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT);
924
925 default:
926 return RESET;
927 }
928 }
929 }
GLB_GPIO_Fifo_Enable(void)930 BL_Sts_Type GLB_GPIO_Fifo_Enable(void)
931 {
932 uint32_t tmpVal;
933
934 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);
935 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);
936 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);
937
938 return SUCCESS;
939 }
GLB_GPIO_Fifo_Disable(void)940 BL_Sts_Type GLB_GPIO_Fifo_Disable(void)
941 {
942 uint32_t tmpVal;
943
944 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);
945 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);
946 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);
947
948 return SUCCESS;
949 }
950
951 /*@} end of group GLB_GPIO_Public_Functions */
952
953 /*@} end of group GLB_GPIO */
954
955 /*@} end of group BL808_Peripheral_Driver */
956