1/*
2 * Copyright (C) 2017-2019 Alibaba Group Holding Limited
3 */
4 /******************************************************************************
5 * @file     vectors.S
6 * @brief    define default vector handlers. Should use with
7 *           GCC for CSKY Embedded Processors
8 * @version  V1.0
9 * @date     28. Nove 2017
10 ******************************************************************************/
11#define __ASSEMBLY__
12#include "irq_ctx.h"
13
14/* Enable interrupts when returning from the handler */
15#define MSTATUS_PRV1 0x1880
16
17.section .bss
18    .align  2
19    .globl  g_trapstackalloc
20    .global g_trapstackbase
21    .global g_top_trapstack
22g_trapstackalloc:
23g_trapstackbase:
24    .space 512
25g_top_trapstack:
26
27    .align 2
28    .globl g_trap_sp
29    .type  g_trap_sp, object
30g_trap_sp:
31    .long 0
32    .size g_trap_sp, .-g_trap_sp
33
34irq_nested_level:
35.long 0
36
37    .align  2
38    .global default_interrupt_handler
39    .weak   default_interrupt_handler
40    .type   default_interrupt_handler, %function
41default_interrupt_handler:
42    addi    sp, sp, -48
43    sw      t0, 4(sp)
44    sw      t1, 8(sp)
45    csrr    t0, mepc
46    csrr    t1, mcause
47    sw      t1, 40(sp)
48    sw      t0, 44(sp)
49    csrs    mstatus, 8
50
51    sw      ra, 0(sp)
52    sw      t2, 12(sp)
53    sw      a0, 16(sp)
54    sw      a1, 20(sp)
55    sw      a2, 24(sp)
56    sw      a3, 28(sp)
57    sw      a4, 32(sp)
58    sw      a5, 36(sp)
59
60    andi    t1, t1, 0x3FF
61    csrw    mscratch, t1
62    slli    t1, t1, 2
63
64    la      t2, interrupt_entry
65    jalr    t2
66
67    /* deal N+32 irq */
68    csrr    t1, mscratch
69    add     t1, t1,32
70    slli    t1, t1, 2
71
72    la      t2, interrupt_entry
73    jalr    t2
74
75    csrc    mstatus, 8
76
77    lw      a1, 40(sp)
78    andi    a0, a1, 0x3FF
79    slli    a0, a0, 2
80
81    /* clear pending */
82    li      a2, 0xE0801000
83    add     a2, a2, a0
84    sb      zero, 0(a2)
85
86    li      t0, MSTATUS_PRV1
87    csrs    mstatus, t0
88    csrw    mcause, a1
89    lw      t0, 44(sp)
90    csrw    mepc, t0
91    lw      ra, 0(sp)
92    lw      t0, 4(sp)
93    lw      t1, 8(sp)
94    lw      t2, 12(sp)
95    lw      a0, 16(sp)
96    lw      a1, 20(sp)
97    lw      a2, 24(sp)
98    lw      a3, 28(sp)
99    lw      a4, 32(sp)
100    lw      a5, 36(sp)
101
102    addi    sp, sp, 48
103    mret
104
105/******************************************************************************
106 * Functions:
107 *     void trap(void);
108 * default exception handler
109 ******************************************************************************/
110    .align  2
111    .global default_trap_handler
112    .type   default_trap_handler, %function
113default_trap_handler:
114trap:
115    /* Check for interrupt */
116    addi    sp, sp, -4
117    sw      t0, 0x0(sp)
118    csrr    t0, mcause
119
120    blt     t0, x0, .Lirq
121
122    addi    sp, sp, 4
123
124    la      t0,  g_trap_sp
125    addi    t0,  t0, -XCPTCONTEXT_SIZE
126    sw      x1,  REG_X1(t0)
127    sw      x2,  REG_X2(t0)
128    sw      x3,  REG_X3(t0)
129    sw      x4,  REG_X4(t0)
130    sw      x6,  REG_X6(t0)
131    sw      x7,  REG_X7(t0)
132    sw      x8,  REG_X8(t0)
133    sw      x9,  REG_X9(t0)
134    sw      x10, REG_X10(t0)
135    sw      x11, REG_X11(t0)
136    sw      x12, REG_X12(t0)
137    sw      x13, REG_X13(t0)
138    sw      x14, REG_X14(t0)
139    sw      x15, REG_X15(t0)
140    csrr    a0,  mepc
141    sw      a0,  REG_EPC(t0)
142    csrr    a0,  mstatus
143    sw      a0,  REG_INT_CTX(t0)
144
145    mv      a0, t0
146    lw      t0, -4(sp)
147    mv      sp, a0
148    sw      t0, REG_X5(sp)
149
150    jal     exception_entry
151
152    lw      t0, REG_INT_CTX(sp)
153    csrw    mstatus, t0
154    lw      t0, REG_EPC(sp)
155    csrw    mepc, t0
156
157    lw      x15, REG_X15(sp)
158    lw      x14, REG_X14(sp)
159    lw      x13, REG_X13(sp)
160    lw      x12, REG_X12(sp)
161    lw      x11, REG_X11(sp)
162    lw      x10, REG_X10(sp)
163    lw      x9,  REG_X9(sp)
164    lw      x8,  REG_X8(sp)
165    lw      x7,  REG_X7(sp)
166    lw      x6,  REG_X6(sp)
167    lw      x5,  REG_X5(sp)
168    lw      x4,  REG_X4(sp)
169    lw      x3,  REG_X3(sp)
170    lw      x1,  REG_X1(sp)
171    lw      x2,  REG_X2(sp)
172
173    mret
174
175.Lirq:
176    lw      t0, 0x0(sp)
177    addi    sp, sp, 4
178    j       default_interrupt_handler
179
180    .size   default_trap_handler, . - default_trap_handler
181