1 /**
2 * @file interrupt.c
3 * @brief
4 *
5 * Copyright (c) 2021 Bouffalolab team
6 *
7 * Licensed to the Apache Software Foundation (ASF) under one or more
8 * contributor license agreements. See the NOTICE file distributed with
9 * this work for additional information regarding copyright ownership. The
10 * ASF licenses this file to you under the Apache License, Version 2.0 (the
11 * "License"); you may not use this file except in compliance with the
12 * License. You may obtain a copy of the License at
13 *
14 * http://www.apache.org/licenses/LICENSE-2.0
15 *
16 * Unless required by applicable law or agreed to in writing, software
17 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
18 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
19 * License for the specific language governing permissions and limitations
20 * under the License.
21 *
22 */
23 #include "bflb_core.h"
24 #include <csi_core.h>
25 #include "irq_ctx.h"
26
27 typedef void (*pFunc)(void);
28
29 struct bflb_irq_info_s g_irqvector[CONFIG_IRQ_NUM];
30
31 extern void default_trap_handler(void);
32 extern void default_interrupt_handler(void);
33
34 const pFunc __Vectors[] __attribute__((section(".vector"), aligned(64))) = {
35 default_interrupt_handler, /* */
36 default_interrupt_handler, /* */
37 default_interrupt_handler, /* */
38 default_interrupt_handler, /* 3: M-mode Soft IRQ */
39 default_interrupt_handler, /* */
40 default_interrupt_handler, /* */
41 default_interrupt_handler, /* */
42 default_interrupt_handler, /* 7: M-mode Timer IRQ */
43 default_interrupt_handler, /* */
44 default_interrupt_handler, /* */
45 default_interrupt_handler, /* */
46 default_interrupt_handler, /* */
47 default_interrupt_handler, /* */
48 default_interrupt_handler, /* */
49 default_interrupt_handler, /* */
50 default_interrupt_handler, /* */
51
52 default_interrupt_handler, //BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */
53 default_interrupt_handler, //BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */
54 default_interrupt_handler, //L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */
55 default_interrupt_handler, //L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */
56 default_interrupt_handler, //SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */
57 default_interrupt_handler, //RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */
58 default_interrupt_handler, //RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */
59 default_interrupt_handler, //SDIO_IRQHandler_Wrapper, /* 16 + 7 */
60 default_interrupt_handler, //DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */
61 default_interrupt_handler, //SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */
62 default_interrupt_handler, //SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */
63 default_interrupt_handler, //SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */
64 default_interrupt_handler, //SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */
65 default_interrupt_handler, //SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */
66 default_interrupt_handler, //SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */
67 default_interrupt_handler, //DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */
68 default_interrupt_handler, //0, /* 16 + 16 */
69 default_interrupt_handler, //0, /* 16 + 17 */
70 default_interrupt_handler, //0, /* 16 + 18 */
71 default_interrupt_handler, //IRTX_IRQHandler_Wrapper, /* 16 + 19 */
72 default_interrupt_handler, //IRRX_IRQHandler_Wrapper, /* 16 + 20 */
73 default_interrupt_handler, //0, /* 16 + 21 */
74 default_interrupt_handler, //0, /* 16 + 22 */
75 default_interrupt_handler, //SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */
76 default_interrupt_handler, //0, /* 16 + 24 */
77 default_interrupt_handler, //GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */
78 default_interrupt_handler, //EFUSE_IRQHandler_Wrapper, /* 16 + 26 */
79 default_interrupt_handler, //SPI_IRQHandler_Wrapper, /* 16 + 27 */
80 default_interrupt_handler, //0, /* 16 + 28 */
81 default_interrupt_handler, //UART0_IRQHandler_Wrapper, /* 16 + 29 */
82 default_interrupt_handler, //UART1_IRQHandler_Wrapper, /* 16 + 30 */
83 default_interrupt_handler, //0, /* 16 + 31 */
84 default_interrupt_handler, //I2C_IRQHandler_Wrapper, /* 16 + 32 */
85 default_interrupt_handler, //0, /* 16 + 33 */
86 default_interrupt_handler, //PWM_IRQHandler_Wrapper, /* 16 + 34 */
87 default_interrupt_handler, //0, /* 16 + 35 */
88 default_interrupt_handler, //TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */
89 default_interrupt_handler, //TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */
90 default_interrupt_handler, //TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */
91 default_interrupt_handler, //0, /* 16 + 39 */
92 default_interrupt_handler, //0, /* 16 + 40 */
93 default_interrupt_handler, //0, /* 16 + 41 */
94 default_interrupt_handler, //0, /* 16 + 42 */
95 default_interrupt_handler, //0, /* 16 + 43 */
96 default_interrupt_handler, //GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */
97 default_interrupt_handler, //0, /* 16 + 45 */
98 default_interrupt_handler, //0, /* 16 + 46 */
99 default_interrupt_handler, //0, /* 16 + 47 */
100 default_interrupt_handler, //0, /* 16 + 48 */
101 default_interrupt_handler, //0, /* 16 + 49 */
102 default_interrupt_handler, //PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */
103 default_interrupt_handler, //HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */
104 default_interrupt_handler, //HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */
105 default_interrupt_handler, //BOR_IRQHandler_Wrapper, /* 16 + 53 */
106 default_interrupt_handler, //WIFI_IRQHandler_Wrapper, /* 16 + 54 */
107 default_interrupt_handler, //BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */
108 default_interrupt_handler, //BLE_IRQHandler_Wrapper, /* 16 + 56 */
109 default_interrupt_handler, //MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */
110 default_interrupt_handler, //MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */
111 default_interrupt_handler, //MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */
112 default_interrupt_handler, //MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */
113 default_interrupt_handler, //MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */
114 default_interrupt_handler, //MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */
115 default_interrupt_handler, //WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */
116 };
117
exception_entry(uintptr_t * regs)118 void exception_entry(uintptr_t *regs)
119 {
120 #ifndef CONFIG_TRAP_DUMP_DISABLE
121 unsigned long cause;
122 unsigned long epc;
123 unsigned long tval;
124
125 printf("exception_entry\r\n");
126
127 cause = READ_CSR(CSR_MCAUSE);
128 printf("mcause=%08x\r\n", (int)cause);
129 epc = READ_CSR(CSR_MEPC);
130 printf("mepc:%08x\r\n", (int)epc);
131 tval = READ_CSR(CSR_MTVAL);
132 printf("mtval:%08x\r\n", (int)tval);
133
134 cause = (cause & 0x3ff);
135
136
137 const char *mcause_str[] = {
138 "Instruction address misaligned",
139 "Instruction access fault",
140 "Illegal instruction",
141 "Breakpoint",
142 "Load address misaligned",
143 "Load access fault",
144 "Store/AMO address misaligned",
145 "Store/AMO access fault",
146 "Environment call from U-mode",
147 "Environment call from S-mode",
148 "RSVD",
149 "Environment call from M-mode",
150 "Instruction page fault",
151 "Load page fault",
152 "RSVD",
153 "Store/AMO page fault"
154 };
155
156 printf("%s\r\n", mcause_str[cause & 0xf]);
157
158 if ((cause == 8) || (cause == 11)) {
159 epc += 4;
160 WRITE_CSR(CSR_MEPC, epc);
161 } else {
162 while (1) {
163 }
164 }
165 #endif
166 }
167
interrupt_entry(void)168 void interrupt_entry(void)
169 {
170 irq_callback handler;
171 void *arg;
172 volatile uint32_t mcause = 0UL;
173 uint32_t irq_num;
174
175 mcause = READ_CSR(CSR_MCAUSE);
176 irq_num = mcause & 0x3FF;
177
178 if (irq_num < CONFIG_IRQ_NUM) {
179 handler = g_irqvector[irq_num].handler;
180 arg = g_irqvector[irq_num].arg;
181 if (handler) {
182 handler(irq_num, arg);
183 } else {
184 }
185 } else {
186 }
187 }
188