1 #include "bl808_clock.h"
2 #include "bl808_pds.h"
3 #include "tzc_sec_reg.h"
4 #include "rv_hart.h"
5 #include "rv_pmp.h"
6
Tzc_Sec_PSRAMA_Access_Set_Not_Lock(uint8_t region,uint32_t startAddr,uint32_t endAddr,uint8_t group)7 static void Tzc_Sec_PSRAMA_Access_Set_Not_Lock(uint8_t region, uint32_t startAddr, uint32_t endAddr, uint8_t group)
8 {
9 uint32_t tmpVal = 0;
10
11 tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);
12 tmpVal &= (~(3 << (region * 2)));
13 tmpVal |= (group << (region * 2));
14 BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);
15
16 tmpVal = ((((endAddr >> 10) & 0xffff) - 1) & 0xffff) | (((startAddr >> 10) & 0xffff) << 16);
17 BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMA_TZSRG_R0_OFFSET + region * 4, tmpVal);
18
19 /* set enable but not lock */
20 tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);
21 tmpVal |= 1 << (region + 16);
22 BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);
23 }
24
Tzc_Sec_PSRAMB_Access_Set_Not_Lock(uint8_t region,uint32_t startAddr,uint32_t endAddr,uint8_t group)25 static void Tzc_Sec_PSRAMB_Access_Set_Not_Lock(uint8_t region, uint32_t startAddr, uint32_t endAddr, uint8_t group)
26 {
27 uint32_t tmpVal = 0;
28
29 tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
30 tmpVal &= (~(3 << (region * 2)));
31 tmpVal |= (group << (region * 2));
32 BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
33
34 tmpVal = ((((endAddr >> 10) & 0xffff) - 1) & 0xffff) | (((startAddr >> 10) & 0xffff) << 16);
35 BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMB_TZSRG_R0_OFFSET + region * 4, tmpVal);
36
37 /* set enable but not lock */
38 tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
39 tmpVal |= 1 << (region + 16);
40 BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
41 }
42
pmp_init(void)43 static void pmp_init(void)
44 {
45 const pmp_config_entry_t pmp_entry_tab[1] = {
46 /* no access */
47 [0] = {
48 .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
49 .entry_pa_base = 0x80000000,
50 .entry_pa_length = PMP_REG_SZ_256M,
51 }
52 };
53 rvpmp_init(pmp_entry_tab, sizeof(pmp_entry_tab) / sizeof(pmp_config_entry_t));
54 }
55
SystemInit(void)56 void SystemInit(void)
57 {
58 uint32_t i = 0;
59
60 /* CPU Prefetching barrier */
61 Tzc_Sec_PSRAMA_Access_Set_Not_Lock(0, 0x0, 64 * 1024 * 1024, 0);
62 Tzc_Sec_PSRAMB_Access_Set_Not_Lock(0, 0x0, 64 * 1024 * 1024, 0);
63 pmp_init();
64
65 /* enable mstatus FS */
66 uint32_t mstatus = __get_MSTATUS();
67 mstatus |= (1 << 13);
68 __set_MSTATUS(mstatus);
69
70 /* enable mxstatus THEADISAEE */
71 uint32_t mxstatus = __get_MXSTATUS();
72 mxstatus |= (1 << 22);
73 /* enable mxstatus MM */
74 mxstatus |= (1 << 15);
75 __set_MXSTATUS(mxstatus);
76
77 /* get interrupt level from info */
78 CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
79
80 /* Every interrupt should be clear by software*/
81 for (i = 0; i < IRQn_LAST; i++) {
82 CLIC->CLICINT[i].IE = 0;
83 CLIC->CLICINT[i].IP = 0;
84 CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
85 }
86
87 /* tspend interrupt will be clear auto*/
88 /* tspend use positive interrupt */
89 CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;
90
91 csi_dcache_enable();
92 csi_icache_enable();
93
94 /* enable preload $ AMR for D$ */
95 __set_MHINT(0x000c);
96
97 /* disable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop*/
98 uint32_t mexstatus = __get_MEXSTATUS();
99 mexstatus &= ~(0x3 << 16);
100 __set_MEXSTATUS(mexstatus);
101
102 GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO0_GPIO11, 0);
103 GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 0);
104 GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO24_GPIO35, 0);
105 GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 0);
106
107 BL_WR_REG(GLB_BASE, GLB_UART_CFG1, 0xffffffff);
108 BL_WR_REG(GLB_BASE, GLB_UART_CFG2, 0x0000ffff);
109
110 GLB_Set_EM_Sel(GLB_WRAM160KB_EM0KB);
111 }
112
System_Post_Init(void)113 void System_Post_Init(void)
114 {
115 csi_dcache_clean();
116 csi_icache_invalid();
117
118 PDS_Power_On_MM_System();
119 /* make D0 all ram avalable for mcu usage */
120 GLB_Set_DSP_L2SRAM_Available_Size(3, 1, 1, 1);
121
122 extern uint32_t __drambss_start__;
123 extern uint32_t __drambss_end__;
124 uint32_t *pDest;
125 pDest = &__drambss_start__;
126
127 for (; pDest < &__drambss_end__;) {
128 *pDest++ = 0ul;
129 }
130
131 /* global IRQ enable */
132 __enable_irq();
133 }