1 /**
2 * @file system_bl702.c
3 * @brief
4 *
5 * Copyright (c) 2021 Bouffalolab team
6 *
7 * Licensed to the Apache Software Foundation (ASF) under one or more
8 * contributor license agreements. See the NOTICE file distributed with
9 * this work for additional information regarding copyright ownership. The
10 * ASF licenses this file to you under the Apache License, Version 2.0 (the
11 * "License"); you may not use this file except in compliance with the
12 * License. You may obtain a copy of the License at
13 *
14 * http://www.apache.org/licenses/LICENSE-2.0
15 *
16 * Unless required by applicable law or agreed to in writing, software
17 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
18 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
19 * License for the specific language governing permissions and limitations
20 * under the License.
21 *
22 */
23 #include "bl602_glb.h"
24 #include <arch/risc-v/e24/clic.h>
25
SystemInit(void)26 void SystemInit(void)
27 {
28 uint32_t *p;
29 uint8_t i;
30 uint32_t tmpVal = 0;
31
32 /* global IRQ disable */
33 __disable_irq();
34
35 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
36 tmpVal |= (1 << 8); /*mask pds wakeup*/
37 tmpVal |= (1 << 10); /*mask rf done*/
38 tmpVal |= (1 << 11); /*mask pll done*/
39 tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/
40 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
41
42 /* GLB_Set_EM_Sel(GLB_EM_0KB); */
43 tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
44 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00); //GLB_EM_0KB
45 BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
46
47 /* Restore default setting*/
48 /* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
49 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
50 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, 0x00); //UART_SIG_SWAP_NONE
51 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
52
53 /* CLear all interrupt */
54 p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIE_OFFSET);
55
56 for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
57 p[i] = 0;
58 }
59
60 p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIP_OFFSET);
61
62 for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
63 p[i] = 0;
64 }
65
66 BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, 0xffffffff);
67
68 /* init bor for all platform */
69 // HBN_BOR_CFG_Type borCfg = { 0 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 0 /* bor_sel */ };
70 // HBN_Set_BOR_Cfg(&borCfg);
71 }
72
System_Post_Init(void)73 void System_Post_Init(void)
74 {
75 PDS_Trim_RC32M();
76 HBN_Trim_RC32K();
77 /* global IRQ enable */
78 __enable_irq();
79 }