1 #include "bl616_clock.h"
2 #include "bl616_pds.h"
3 #include "tzc_sec_reg.h"
4 #include "rv_hart.h"
5 #include "rv_pmp.h"
6
Tzc_Sec_PSRAMB_Access_Set_Not_Lock(uint8_t region,uint32_t startAddr,uint32_t endAddr,uint8_t group)7 static void Tzc_Sec_PSRAMB_Access_Set_Not_Lock(uint8_t region, uint32_t startAddr, uint32_t endAddr, uint8_t group)
8 {
9 uint32_t tmpVal = 0;
10
11 tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
12 tmpVal &= (~(3 << (region * 2)));
13 tmpVal |= (group << (region * 2));
14 BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
15
16 tmpVal = ((((endAddr >> 10) & 0xffff) - 1) & 0xffff) | (((startAddr >> 10) & 0xffff) << 16);
17 BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMB_TZSRG_R0_OFFSET + region * 4, tmpVal);
18
19 /* set enable but not lock */
20 tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
21 tmpVal |= 1 << (region + 16);
22 //tmpVal |= 1<<(region+24);
23 BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
24 }
Tzc_Sec_ROM_Access_Set_Not_Lock(uint8_t region,uint32_t startAddr,uint32_t length,uint8_t group)25 static void Tzc_Sec_ROM_Access_Set_Not_Lock(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
26 {
27 uint32_t tmpVal = 0;
28 uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
29
30 /* check the parameter */
31 group = group & 0xf;
32
33 tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
34 tmpVal &= (~(0xf << (region * 4)));
35 tmpVal |= (group << (region * 4));
36 BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
37
38 tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
39 BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_ROM_TZSRG_R0_OFFSET + region * 4, tmpVal);
40
41 /* set enable and lock */
42 tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
43 tmpVal |= 1 << (region + 16);
44 // tmpVal |= 1 << (region + 24);
45 BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
46 }
pmp_init(void)47 static void pmp_init(void)
48 {
49 const pmp_config_entry_t pmp_entry_tab[6] = {
50 /* no access 0x00000000-0x20000000*/
51 [0] = {
52 .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
53 .entry_pa_base = 0x00000000,
54 .entry_pa_length = PMP_REG_SZ_512M,
55 },
56 /* no access 0x40000000-0x60000000*/
57 [1] = {
58 .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
59 .entry_pa_base = 0x40000000,
60 .entry_pa_length = PMP_REG_SZ_512M,
61 },
62 /* no access 0x70000000-0x80000000*/
63 [2] = {
64 .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
65 .entry_pa_base = 0x70000000,
66 .entry_pa_length = PMP_REG_SZ_256M,
67 },
68 /* no access 0x80000000-0x90000000*/
69 [3] = {
70 .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
71 .entry_pa_base = 0x80000000,
72 .entry_pa_length = PMP_REG_SZ_256M,
73 },
74 /* no access 0xB0000000-0xC0000000*/
75 [4] = {
76 .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
77 .entry_pa_base = 0xB0000000,
78 .entry_pa_length = PMP_REG_SZ_256M,
79 },
80 /* no access 0xC0000000-0xE0000000*/
81 [5] = {
82 .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
83 .entry_pa_base = 0xC0000000,
84 .entry_pa_length = PMP_REG_SZ_512M,
85 }
86 };
87 rvpmp_init(pmp_entry_tab, sizeof(pmp_entry_tab) / sizeof(pmp_config_entry_t));
88 }
89
SystemInit(void)90 void SystemInit(void)
91 {
92 uint32_t i = 0;
93
94 /* CPU Prefetching barrier */
95 Tzc_Sec_PSRAMB_Access_Set_Not_Lock(0, 0x0, 64 * 1024 * 1024, 0);
96 Tzc_Sec_ROM_Access_Set_Not_Lock(1, 0x90020000, ((256 * 1024 * 1024) - (128 * 1024)), 0);
97 pmp_init();
98
99 /* enable mstatus FS */
100 uint32_t mstatus = __get_MSTATUS();
101 mstatus |= (1 << 13);
102 __set_MSTATUS(mstatus);
103
104 /* enable mxstatus THEADISAEE */
105 uint32_t mxstatus = __get_MXSTATUS();
106 mxstatus |= (1 << 22);
107 /* enable mxstatus MM */
108 mxstatus |= (1 << 15);
109 __set_MXSTATUS(mxstatus);
110
111 /* get interrupt level from info */
112 CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
113
114 /* Every interrupt should be clear by software*/
115 for (i = 0; i < IRQn_LAST; i++) {
116 CLIC->CLICINT[i].IE = 0;
117 CLIC->CLICINT[i].IP = 0;
118 CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
119 }
120
121 /* tspend interrupt will be clear auto*/
122 /* tspend use positive interrupt */
123 CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;
124
125 csi_dcache_enable();
126 csi_icache_enable();
127
128 /* disable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop*/
129 uint32_t mexstatus = __get_MEXSTATUS();
130 mexstatus &= ~(0x3 << 16);
131 __set_MEXSTATUS(mexstatus);
132
133 BL_WR_REG(GLB_BASE, GLB_UART_CFG1, 0xffffffff);
134 BL_WR_REG(GLB_BASE, GLB_UART_CFG2, 0x0000ffff);
135 }
136
System_Post_Init(void)137 void System_Post_Init(void)
138 {
139 /* Bootrom not use dcache,so ignore this flush*/
140 #ifndef BOOTROM
141 csi_dcache_clean();
142 csi_icache_invalid();
143 #endif
144
145 /* global IRQ enable */
146 __enable_irq();
147 }
148