1 /**
2 * @file system_bl702.c
3 * @brief
4 *
5 * Copyright (c) 2021 Bouffalolab team
6 *
7 * Licensed to the Apache Software Foundation (ASF) under one or more
8 * contributor license agreements. See the NOTICE file distributed with
9 * this work for additional information regarding copyright ownership. The
10 * ASF licenses this file to you under the Apache License, Version 2.0 (the
11 * "License"); you may not use this file except in compliance with the
12 * License. You may obtain a copy of the License at
13 *
14 * http://www.apache.org/licenses/LICENSE-2.0
15 *
16 * Unless required by applicable law or agreed to in writing, software
17 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
18 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
19 * License for the specific language governing permissions and limitations
20 * under the License.
21 *
22 */
23 #include "bl702_glb.h"
24 #include "bl702_hbn.h"
25 #include "bl702_aon.h"
26 #include <arch/risc-v/e24/clic.h>
27
SystemInit(void)28 void SystemInit(void)
29 {
30 uint32_t *p;
31 uint8_t i;
32 uint32_t tmpVal = 0;
33 uint8_t flashCfg = 0;
34 uint8_t psramCfg = 0;
35 uint8_t isInternalFlash = 0;
36 uint8_t isInternalPsram = 0;
37
38 /* global IRQ disable */
39 __disable_irq();
40
41 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
42 tmpVal |= (1 << 8); /*mask pds wakeup*/
43 tmpVal |= (1 << 10); /*mask rf done*/
44 tmpVal |= (1 << 11); /*mask pll done*/
45 tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/
46 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
47
48 /* GLB_Set_EM_Sel(GLB_EM_0KB); */
49 tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
50 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00); //GLB_EM_0KB
51 BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
52
53 /* Restore default setting*/
54 /* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
55 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
56 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, 0x00); //UART_SIG_SWAP_NONE
57 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
58
59 /* CLear all interrupt */
60 p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIE_OFFSET);
61
62 for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
63 p[i] = 0;
64 }
65
66 p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIP_OFFSET);
67
68 for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
69 p[i] = 0;
70 }
71
72 /* SF io select from efuse value */
73 tmpVal = BL_RD_WORD(0x40007074);
74 flashCfg = ((tmpVal >> 26) & 7);
75 psramCfg = ((tmpVal >> 24) & 3);
76 if (flashCfg == 1 || flashCfg == 2) {
77 isInternalFlash = 1;
78 } else {
79 isInternalFlash = 0;
80 }
81 if (psramCfg == 1) {
82 isInternalPsram = 1;
83 } else {
84 isInternalPsram = 0;
85 }
86 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
87 if (isInternalFlash == 1 && isInternalPsram == 0) {
88 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
89 } else {
90 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
91 }
92 BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
93
94 BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, 0xffffffff);
95
96 /* init bor for all platform */
97 // HBN_BOR_CFG_Type borCfg = { 0 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 0 /* bor_sel */ };
98 // HBN_Set_BOR_Cfg(&borCfg);
99 /* dcdc 1.8v -> 1.5v */
100 tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_0);
101 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VOUT_SEL_AON, 0xC);
102 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VPFM_AON, 0x3);
103 BL_WR_REG(AON_BASE, AON_DCDC18_TOP_0, tmpVal);
104 }
105
System_Post_Init(void)106 void System_Post_Init(void)
107 {
108 PDS_Trim_RC32M();
109 HBN_Trim_RC32K();
110 /* global IRQ enable */
111 __enable_irq();
112 }