1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32L1xx_HAL_CORTEX_H 22 #define __STM32L1xx_HAL_CORTEX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l1xx_hal_def.h" 30 31 /** @addtogroup STM32L1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup CORTEX 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup CORTEX_Exported_Types Cortex Exported Types 41 * @{ 42 */ 43 44 #if (__MPU_PRESENT == 1) 45 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 46 * @brief MPU Region initialization structure 47 * @{ 48 */ 49 typedef struct 50 { 51 uint8_t Enable; /*!< Specifies the status of the region. 52 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 53 uint8_t Number; /*!< Specifies the number of the region to protect. 54 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 55 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 56 uint8_t Size; /*!< Specifies the size of the region to protect. 57 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 58 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 59 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 60 uint8_t TypeExtField; /*!< Specifies the TEX field level. 61 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 62 uint8_t AccessPermission; /*!< Specifies the region access permission type. 63 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 64 uint8_t DisableExec; /*!< Specifies the instruction access status. 65 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 66 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 67 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 68 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 69 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 70 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 71 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 72 }MPU_Region_InitTypeDef; 73 /** 74 * @} 75 */ 76 #endif /* __MPU_PRESENT */ 77 78 /** 79 * @} 80 */ 81 82 /* Exported constants --------------------------------------------------------*/ 83 84 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 85 * @{ 86 */ 87 88 89 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 90 * @{ 91 */ 92 93 #define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority 94 4 bits for subpriority */ 95 #define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority 96 3 bits for subpriority */ 97 #define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority 98 2 bits for subpriority */ 99 #define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority 100 1 bits for subpriority */ 101 #define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority 102 0 bits for subpriority */ 103 /** 104 * @} 105 */ 106 107 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 108 * @{ 109 */ 110 #define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) 111 #define SYSTICK_CLKSOURCE_HCLK (0x00000004U) 112 113 /** 114 * @} 115 */ 116 117 #if (__MPU_PRESENT == 1) 118 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control 119 * @{ 120 */ 121 #define MPU_HFNMI_PRIVDEF_NONE (0x00000000U) 122 #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) 123 #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) 124 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 125 126 /** 127 * @} 128 */ 129 130 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 131 * @{ 132 */ 133 #define MPU_REGION_ENABLE ((uint8_t)0x01) 134 #define MPU_REGION_DISABLE ((uint8_t)0x00) 135 /** 136 * @} 137 */ 138 139 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 140 * @{ 141 */ 142 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 143 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 144 /** 145 * @} 146 */ 147 148 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 149 * @{ 150 */ 151 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 152 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 153 /** 154 * @} 155 */ 156 157 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 158 * @{ 159 */ 160 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 161 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 162 /** 163 * @} 164 */ 165 166 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 167 * @{ 168 */ 169 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 170 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 171 /** 172 * @} 173 */ 174 175 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels 176 * @{ 177 */ 178 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 179 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 180 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 181 /** 182 * @} 183 */ 184 185 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 186 * @{ 187 */ 188 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 189 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 190 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 191 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 192 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 193 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 194 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 195 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 196 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 197 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 198 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 199 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 200 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 201 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 202 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 203 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 204 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 205 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 206 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 207 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 208 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 209 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 210 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 211 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 212 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 213 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 214 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 215 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 216 /** 217 * @} 218 */ 219 220 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 221 * @{ 222 */ 223 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 224 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 225 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 226 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 227 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 228 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 229 /** 230 * @} 231 */ 232 233 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 234 * @{ 235 */ 236 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 237 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 238 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 239 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 240 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 241 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 242 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 243 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 244 /** 245 * @} 246 */ 247 #endif /* __MPU_PRESENT */ 248 /** 249 * @} 250 */ 251 252 /* Exported Macros -----------------------------------------------------------*/ 253 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 254 * @{ 255 */ 256 257 /** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group 258 * @{ 259 */ 260 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 261 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 262 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 263 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 264 ((GROUP) == NVIC_PRIORITYGROUP_4)) 265 266 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 267 268 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 269 270 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) 271 272 /** 273 * @} 274 */ 275 276 /** 277 * @} 278 */ 279 280 /* Private macro -------------------------------------------------------------*/ 281 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 282 * @{ 283 */ 284 285 /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source 286 * @{ 287 */ 288 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 289 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 290 /** 291 * @} 292 */ 293 294 #if (__MPU_PRESENT == 1) 295 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 296 ((STATE) == MPU_REGION_DISABLE)) 297 298 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 299 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 300 301 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 302 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 303 304 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 305 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 306 307 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 308 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 309 310 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 311 ((TYPE) == MPU_TEX_LEVEL1) || \ 312 ((TYPE) == MPU_TEX_LEVEL2)) 313 314 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 315 ((TYPE) == MPU_REGION_PRIV_RW) || \ 316 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 317 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 318 ((TYPE) == MPU_REGION_PRIV_RO) || \ 319 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 320 321 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 322 ((NUMBER) == MPU_REGION_NUMBER1) || \ 323 ((NUMBER) == MPU_REGION_NUMBER2) || \ 324 ((NUMBER) == MPU_REGION_NUMBER3) || \ 325 ((NUMBER) == MPU_REGION_NUMBER4) || \ 326 ((NUMBER) == MPU_REGION_NUMBER5) || \ 327 ((NUMBER) == MPU_REGION_NUMBER6) || \ 328 ((NUMBER) == MPU_REGION_NUMBER7)) 329 330 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 331 ((SIZE) == MPU_REGION_SIZE_64B) || \ 332 ((SIZE) == MPU_REGION_SIZE_128B) || \ 333 ((SIZE) == MPU_REGION_SIZE_256B) || \ 334 ((SIZE) == MPU_REGION_SIZE_512B) || \ 335 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 336 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 337 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 338 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 339 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 340 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 341 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 342 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 343 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 344 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 345 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 346 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 347 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 348 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 349 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 350 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 351 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 352 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 353 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 354 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 355 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 356 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 357 ((SIZE) == MPU_REGION_SIZE_4GB)) 358 359 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) 360 #endif /* __MPU_PRESENT */ 361 362 /** 363 * @} 364 */ 365 366 /* Private functions ---------------------------------------------------------*/ 367 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions 368 * @brief CORTEX private functions 369 * @{ 370 */ 371 372 373 /** 374 * @} 375 */ 376 377 /* Exported functions --------------------------------------------------------*/ 378 /** @addtogroup CORTEX_Exported_Functions 379 * @{ 380 */ 381 382 /** @addtogroup CORTEX_Exported_Functions_Group1 383 * @{ 384 */ 385 /* Initialization and de-initialization functions *****************************/ 386 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 387 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 388 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 389 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 390 void HAL_NVIC_SystemReset(void); 391 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 392 /** 393 * @} 394 */ 395 396 /** @addtogroup CORTEX_Exported_Functions_Group2 397 * @{ 398 */ 399 /* Peripheral Control functions ***********************************************/ 400 #if (__MPU_PRESENT == 1) 401 void HAL_MPU_Enable(uint32_t MPU_Control); 402 void HAL_MPU_Disable(void); 403 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 404 #endif /* __MPU_PRESENT */ 405 uint32_t HAL_NVIC_GetPriorityGrouping(void); 406 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 407 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 408 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 409 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 410 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 411 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 412 void HAL_SYSTICK_IRQHandler(void); 413 void HAL_SYSTICK_Callback(void); 414 /** 415 * @} 416 */ 417 418 /** 419 * @} 420 */ 421 422 /** 423 * @} 424 */ 425 426 /** 427 * @} 428 */ 429 430 #ifdef __cplusplus 431 } 432 #endif 433 434 #endif /* __STM32L1xx_HAL_CORTEX_H */ 435 436 437 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 438