1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32L1xx_LL_DMA_H
22 #define __STM32L1xx_LL_DMA_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l1xx.h"
30
31 /** @addtogroup STM32L1xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1) || defined (DMA2)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
47 static const uint8_t CHANNEL_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
56 };
57 /**
58 * @}
59 */
60
61 /* Private constants ---------------------------------------------------------*/
62
63 /* Private macros ------------------------------------------------------------*/
64 #if defined(USE_FULL_LL_DRIVER)
65 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
66 * @{
67 */
68 /**
69 * @}
70 */
71 #endif /*USE_FULL_LL_DRIVER*/
72
73 /* Exported types ------------------------------------------------------------*/
74 #if defined(USE_FULL_LL_DRIVER)
75 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
76 * @{
77 */
78 typedef struct
79 {
80 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
81 or as Source base address in case of memory to memory transfer direction.
82
83 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
84
85 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
86 or as Destination base address in case of memory to memory transfer direction.
87
88 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
89
90 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
91 from memory to memory or from peripheral to memory.
92 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
93
94 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
95
96 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
97 This parameter can be a value of @ref DMA_LL_EC_MODE
98 @note: The circular buffer mode cannot be used if the memory to memory
99 data transfer direction is configured on the selected Channel
100
101 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
102
103 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
104 is incremented or not.
105 This parameter can be a value of @ref DMA_LL_EC_PERIPH
106
107 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
108
109 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
110 is incremented or not.
111 This parameter can be a value of @ref DMA_LL_EC_MEMORY
112
113 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
114
115 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
116 in case of memory to memory transfer direction.
117 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
118
119 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
120
121 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
122 in case of memory to memory transfer direction.
123 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
124
125 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
126
127 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
128 The data unit is equal to the source buffer configuration set in PeripheralSize
129 or MemorySize parameters depending in the transfer direction.
130 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
131
132 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
133
134 uint32_t Priority; /*!< Specifies the channel priority level.
135 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
136
137 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
138
139 } LL_DMA_InitTypeDef;
140 /**
141 * @}
142 */
143 #endif /*USE_FULL_LL_DRIVER*/
144
145 /* Exported constants --------------------------------------------------------*/
146 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
147 * @{
148 */
149 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
150 * @brief Flags defines which can be used with LL_DMA_WriteReg function
151 * @{
152 */
153 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
154 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
155 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
156 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
157 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
158 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
159 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
160 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
161 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
162 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
163 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
164 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
165 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
166 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
167 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
168 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
169 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
170 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
171 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
172 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
173 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
174 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
175 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
176 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
177 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
178 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
179 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
180 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
181 /**
182 * @}
183 */
184
185 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
186 * @brief Flags defines which can be used with LL_DMA_ReadReg function
187 * @{
188 */
189 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
190 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
191 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
192 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
193 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
194 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
195 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
196 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
197 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
198 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
199 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
200 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
201 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
202 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
203 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
204 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
205 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
206 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
207 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
208 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
209 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
210 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
211 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
212 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
213 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
214 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
215 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
216 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
217 /**
218 * @}
219 */
220
221 /** @defgroup DMA_LL_EC_IT IT Defines
222 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
223 * @{
224 */
225 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
226 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
227 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
228 /**
229 * @}
230 */
231
232 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
233 * @{
234 */
235 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
236 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
237 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
238 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
239 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
240 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
241 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
242 #if defined(USE_FULL_LL_DRIVER)
243 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
244 #endif /*USE_FULL_LL_DRIVER*/
245 /**
246 * @}
247 */
248
249 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
250 * @{
251 */
252 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
253 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
254 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
255 /**
256 * @}
257 */
258
259 /** @defgroup DMA_LL_EC_MODE Transfer mode
260 * @{
261 */
262 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
263 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
264 /**
265 * @}
266 */
267
268 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
269 * @{
270 */
271 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
272 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
273 /**
274 * @}
275 */
276
277 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
278 * @{
279 */
280 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
281 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
282 /**
283 * @}
284 */
285
286 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
287 * @{
288 */
289 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
290 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
291 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
292 /**
293 * @}
294 */
295
296 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
297 * @{
298 */
299 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
300 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
301 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
302 /**
303 * @}
304 */
305
306 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
307 * @{
308 */
309 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
310 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
311 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
312 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
313 /**
314 * @}
315 */
316
317
318 /**
319 * @}
320 */
321
322 /* Exported macro ------------------------------------------------------------*/
323 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
324 * @{
325 */
326
327 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
328 * @{
329 */
330 /**
331 * @brief Write a value in DMA register
332 * @param __INSTANCE__ DMA Instance
333 * @param __REG__ Register to be written
334 * @param __VALUE__ Value to be written in the register
335 * @retval None
336 */
337 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
338
339 /**
340 * @brief Read a value in DMA register
341 * @param __INSTANCE__ DMA Instance
342 * @param __REG__ Register to be read
343 * @retval Register value
344 */
345 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
346 /**
347 * @}
348 */
349
350 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
351 * @{
352 */
353 /**
354 * @brief Convert DMAx_Channely into DMAx
355 * @param __CHANNEL_INSTANCE__ DMAx_Channely
356 * @retval DMAx
357 */
358 #if defined(DMA2)
359 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
360 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
361 #else
362 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
363 #endif
364
365 /**
366 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
367 * @param __CHANNEL_INSTANCE__ DMAx_Channely
368 * @retval LL_DMA_CHANNEL_y
369 */
370 #if defined (DMA2)
371 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
372 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
373 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
374 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
375 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
376 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
377 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
378 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
379 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
380 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
381 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
382 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
383 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
384 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
385 LL_DMA_CHANNEL_7)
386 #else
387 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
388 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
397 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
398 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
399 LL_DMA_CHANNEL_7)
400 #endif
401 #else
402 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
403 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
407 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
408 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
409 LL_DMA_CHANNEL_7)
410 #endif
411
412 /**
413 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
414 * @param __DMA_INSTANCE__ DMAx
415 * @param __CHANNEL__ LL_DMA_CHANNEL_y
416 * @retval DMAx_Channely
417 */
418 #if defined (DMA2)
419 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
420 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
421 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
422 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
423 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
424 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
425 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
426 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
427 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
428 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
429 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
430 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
431 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
432 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
433 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
434 DMA2_Channel7)
435 #else
436 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
437 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
448 DMA1_Channel7)
449 #endif
450 #else
451 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
452 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
458 DMA1_Channel7)
459 #endif
460
461 /**
462 * @}
463 */
464
465 /**
466 * @}
467 */
468
469 /* Exported functions --------------------------------------------------------*/
470 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
471 * @{
472 */
473
474 /** @defgroup DMA_LL_EF_Configuration Configuration
475 * @{
476 */
477 /**
478 * @brief Enable DMA channel.
479 * @rmtoll CCR EN LL_DMA_EnableChannel
480 * @param DMAx DMAx Instance
481 * @param Channel This parameter can be one of the following values:
482 * @arg @ref LL_DMA_CHANNEL_1
483 * @arg @ref LL_DMA_CHANNEL_2
484 * @arg @ref LL_DMA_CHANNEL_3
485 * @arg @ref LL_DMA_CHANNEL_4
486 * @arg @ref LL_DMA_CHANNEL_5
487 * @arg @ref LL_DMA_CHANNEL_6
488 * @arg @ref LL_DMA_CHANNEL_7
489 * @retval None
490 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)491 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
492 {
493 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
494 }
495
496 /**
497 * @brief Disable DMA channel.
498 * @rmtoll CCR EN LL_DMA_DisableChannel
499 * @param DMAx DMAx Instance
500 * @param Channel This parameter can be one of the following values:
501 * @arg @ref LL_DMA_CHANNEL_1
502 * @arg @ref LL_DMA_CHANNEL_2
503 * @arg @ref LL_DMA_CHANNEL_3
504 * @arg @ref LL_DMA_CHANNEL_4
505 * @arg @ref LL_DMA_CHANNEL_5
506 * @arg @ref LL_DMA_CHANNEL_6
507 * @arg @ref LL_DMA_CHANNEL_7
508 * @retval None
509 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)510 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
511 {
512 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
513 }
514
515 /**
516 * @brief Check if DMA channel is enabled or disabled.
517 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
518 * @param DMAx DMAx Instance
519 * @param Channel This parameter can be one of the following values:
520 * @arg @ref LL_DMA_CHANNEL_1
521 * @arg @ref LL_DMA_CHANNEL_2
522 * @arg @ref LL_DMA_CHANNEL_3
523 * @arg @ref LL_DMA_CHANNEL_4
524 * @arg @ref LL_DMA_CHANNEL_5
525 * @arg @ref LL_DMA_CHANNEL_6
526 * @arg @ref LL_DMA_CHANNEL_7
527 * @retval State of bit (1 or 0).
528 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)529 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
530 {
531 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
532 DMA_CCR_EN) == (DMA_CCR_EN));
533 }
534
535 /**
536 * @brief Configure all parameters link to DMA transfer.
537 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
538 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
539 * CCR CIRC LL_DMA_ConfigTransfer\n
540 * CCR PINC LL_DMA_ConfigTransfer\n
541 * CCR MINC LL_DMA_ConfigTransfer\n
542 * CCR PSIZE LL_DMA_ConfigTransfer\n
543 * CCR MSIZE LL_DMA_ConfigTransfer\n
544 * CCR PL LL_DMA_ConfigTransfer
545 * @param DMAx DMAx Instance
546 * @param Channel This parameter can be one of the following values:
547 * @arg @ref LL_DMA_CHANNEL_1
548 * @arg @ref LL_DMA_CHANNEL_2
549 * @arg @ref LL_DMA_CHANNEL_3
550 * @arg @ref LL_DMA_CHANNEL_4
551 * @arg @ref LL_DMA_CHANNEL_5
552 * @arg @ref LL_DMA_CHANNEL_6
553 * @arg @ref LL_DMA_CHANNEL_7
554 * @param Configuration This parameter must be a combination of all the following values:
555 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
556 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
557 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
558 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
559 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
560 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
561 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
562 * @retval None
563 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)564 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
565 {
566 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
567 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
568 Configuration);
569 }
570
571 /**
572 * @brief Set Data transfer direction (read from peripheral or from memory).
573 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
574 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
575 * @param DMAx DMAx Instance
576 * @param Channel This parameter can be one of the following values:
577 * @arg @ref LL_DMA_CHANNEL_1
578 * @arg @ref LL_DMA_CHANNEL_2
579 * @arg @ref LL_DMA_CHANNEL_3
580 * @arg @ref LL_DMA_CHANNEL_4
581 * @arg @ref LL_DMA_CHANNEL_5
582 * @arg @ref LL_DMA_CHANNEL_6
583 * @arg @ref LL_DMA_CHANNEL_7
584 * @param Direction This parameter can be one of the following values:
585 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
586 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
587 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
588 * @retval None
589 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)590 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
591 {
592 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
593 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
594 }
595
596 /**
597 * @brief Get Data transfer direction (read from peripheral or from memory).
598 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
599 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
600 * @param DMAx DMAx Instance
601 * @param Channel This parameter can be one of the following values:
602 * @arg @ref LL_DMA_CHANNEL_1
603 * @arg @ref LL_DMA_CHANNEL_2
604 * @arg @ref LL_DMA_CHANNEL_3
605 * @arg @ref LL_DMA_CHANNEL_4
606 * @arg @ref LL_DMA_CHANNEL_5
607 * @arg @ref LL_DMA_CHANNEL_6
608 * @arg @ref LL_DMA_CHANNEL_7
609 * @retval Returned value can be one of the following values:
610 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
611 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
612 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
613 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)614 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
615 {
616 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
617 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
618 }
619
620 /**
621 * @brief Set DMA mode circular or normal.
622 * @note The circular buffer mode cannot be used if the memory-to-memory
623 * data transfer is configured on the selected Channel.
624 * @rmtoll CCR CIRC LL_DMA_SetMode
625 * @param DMAx DMAx Instance
626 * @param Channel This parameter can be one of the following values:
627 * @arg @ref LL_DMA_CHANNEL_1
628 * @arg @ref LL_DMA_CHANNEL_2
629 * @arg @ref LL_DMA_CHANNEL_3
630 * @arg @ref LL_DMA_CHANNEL_4
631 * @arg @ref LL_DMA_CHANNEL_5
632 * @arg @ref LL_DMA_CHANNEL_6
633 * @arg @ref LL_DMA_CHANNEL_7
634 * @param Mode This parameter can be one of the following values:
635 * @arg @ref LL_DMA_MODE_NORMAL
636 * @arg @ref LL_DMA_MODE_CIRCULAR
637 * @retval None
638 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)639 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
640 {
641 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
642 Mode);
643 }
644
645 /**
646 * @brief Get DMA mode circular or normal.
647 * @rmtoll CCR CIRC LL_DMA_GetMode
648 * @param DMAx DMAx Instance
649 * @param Channel This parameter can be one of the following values:
650 * @arg @ref LL_DMA_CHANNEL_1
651 * @arg @ref LL_DMA_CHANNEL_2
652 * @arg @ref LL_DMA_CHANNEL_3
653 * @arg @ref LL_DMA_CHANNEL_4
654 * @arg @ref LL_DMA_CHANNEL_5
655 * @arg @ref LL_DMA_CHANNEL_6
656 * @arg @ref LL_DMA_CHANNEL_7
657 * @retval Returned value can be one of the following values:
658 * @arg @ref LL_DMA_MODE_NORMAL
659 * @arg @ref LL_DMA_MODE_CIRCULAR
660 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)661 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
662 {
663 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
664 DMA_CCR_CIRC));
665 }
666
667 /**
668 * @brief Set Peripheral increment mode.
669 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
670 * @param DMAx DMAx Instance
671 * @param Channel This parameter can be one of the following values:
672 * @arg @ref LL_DMA_CHANNEL_1
673 * @arg @ref LL_DMA_CHANNEL_2
674 * @arg @ref LL_DMA_CHANNEL_3
675 * @arg @ref LL_DMA_CHANNEL_4
676 * @arg @ref LL_DMA_CHANNEL_5
677 * @arg @ref LL_DMA_CHANNEL_6
678 * @arg @ref LL_DMA_CHANNEL_7
679 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
680 * @arg @ref LL_DMA_PERIPH_INCREMENT
681 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
682 * @retval None
683 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)684 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
685 {
686 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
687 PeriphOrM2MSrcIncMode);
688 }
689
690 /**
691 * @brief Get Peripheral increment mode.
692 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
693 * @param DMAx DMAx Instance
694 * @param Channel This parameter can be one of the following values:
695 * @arg @ref LL_DMA_CHANNEL_1
696 * @arg @ref LL_DMA_CHANNEL_2
697 * @arg @ref LL_DMA_CHANNEL_3
698 * @arg @ref LL_DMA_CHANNEL_4
699 * @arg @ref LL_DMA_CHANNEL_5
700 * @arg @ref LL_DMA_CHANNEL_6
701 * @arg @ref LL_DMA_CHANNEL_7
702 * @retval Returned value can be one of the following values:
703 * @arg @ref LL_DMA_PERIPH_INCREMENT
704 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
705 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)706 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
707 {
708 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
709 DMA_CCR_PINC));
710 }
711
712 /**
713 * @brief Set Memory increment mode.
714 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
715 * @param DMAx DMAx Instance
716 * @param Channel This parameter can be one of the following values:
717 * @arg @ref LL_DMA_CHANNEL_1
718 * @arg @ref LL_DMA_CHANNEL_2
719 * @arg @ref LL_DMA_CHANNEL_3
720 * @arg @ref LL_DMA_CHANNEL_4
721 * @arg @ref LL_DMA_CHANNEL_5
722 * @arg @ref LL_DMA_CHANNEL_6
723 * @arg @ref LL_DMA_CHANNEL_7
724 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
725 * @arg @ref LL_DMA_MEMORY_INCREMENT
726 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
727 * @retval None
728 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)729 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
730 {
731 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
732 MemoryOrM2MDstIncMode);
733 }
734
735 /**
736 * @brief Get Memory increment mode.
737 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
738 * @param DMAx DMAx Instance
739 * @param Channel This parameter can be one of the following values:
740 * @arg @ref LL_DMA_CHANNEL_1
741 * @arg @ref LL_DMA_CHANNEL_2
742 * @arg @ref LL_DMA_CHANNEL_3
743 * @arg @ref LL_DMA_CHANNEL_4
744 * @arg @ref LL_DMA_CHANNEL_5
745 * @arg @ref LL_DMA_CHANNEL_6
746 * @arg @ref LL_DMA_CHANNEL_7
747 * @retval Returned value can be one of the following values:
748 * @arg @ref LL_DMA_MEMORY_INCREMENT
749 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
750 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)751 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
752 {
753 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
754 DMA_CCR_MINC));
755 }
756
757 /**
758 * @brief Set Peripheral size.
759 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
760 * @param DMAx DMAx Instance
761 * @param Channel This parameter can be one of the following values:
762 * @arg @ref LL_DMA_CHANNEL_1
763 * @arg @ref LL_DMA_CHANNEL_2
764 * @arg @ref LL_DMA_CHANNEL_3
765 * @arg @ref LL_DMA_CHANNEL_4
766 * @arg @ref LL_DMA_CHANNEL_5
767 * @arg @ref LL_DMA_CHANNEL_6
768 * @arg @ref LL_DMA_CHANNEL_7
769 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
770 * @arg @ref LL_DMA_PDATAALIGN_BYTE
771 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
772 * @arg @ref LL_DMA_PDATAALIGN_WORD
773 * @retval None
774 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)775 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
776 {
777 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
778 PeriphOrM2MSrcDataSize);
779 }
780
781 /**
782 * @brief Get Peripheral size.
783 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
784 * @param DMAx DMAx Instance
785 * @param Channel This parameter can be one of the following values:
786 * @arg @ref LL_DMA_CHANNEL_1
787 * @arg @ref LL_DMA_CHANNEL_2
788 * @arg @ref LL_DMA_CHANNEL_3
789 * @arg @ref LL_DMA_CHANNEL_4
790 * @arg @ref LL_DMA_CHANNEL_5
791 * @arg @ref LL_DMA_CHANNEL_6
792 * @arg @ref LL_DMA_CHANNEL_7
793 * @retval Returned value can be one of the following values:
794 * @arg @ref LL_DMA_PDATAALIGN_BYTE
795 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
796 * @arg @ref LL_DMA_PDATAALIGN_WORD
797 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)798 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
799 {
800 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
801 DMA_CCR_PSIZE));
802 }
803
804 /**
805 * @brief Set Memory size.
806 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
807 * @param DMAx DMAx Instance
808 * @param Channel This parameter can be one of the following values:
809 * @arg @ref LL_DMA_CHANNEL_1
810 * @arg @ref LL_DMA_CHANNEL_2
811 * @arg @ref LL_DMA_CHANNEL_3
812 * @arg @ref LL_DMA_CHANNEL_4
813 * @arg @ref LL_DMA_CHANNEL_5
814 * @arg @ref LL_DMA_CHANNEL_6
815 * @arg @ref LL_DMA_CHANNEL_7
816 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
817 * @arg @ref LL_DMA_MDATAALIGN_BYTE
818 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
819 * @arg @ref LL_DMA_MDATAALIGN_WORD
820 * @retval None
821 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)822 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
823 {
824 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
825 MemoryOrM2MDstDataSize);
826 }
827
828 /**
829 * @brief Get Memory size.
830 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
831 * @param DMAx DMAx Instance
832 * @param Channel This parameter can be one of the following values:
833 * @arg @ref LL_DMA_CHANNEL_1
834 * @arg @ref LL_DMA_CHANNEL_2
835 * @arg @ref LL_DMA_CHANNEL_3
836 * @arg @ref LL_DMA_CHANNEL_4
837 * @arg @ref LL_DMA_CHANNEL_5
838 * @arg @ref LL_DMA_CHANNEL_6
839 * @arg @ref LL_DMA_CHANNEL_7
840 * @retval Returned value can be one of the following values:
841 * @arg @ref LL_DMA_MDATAALIGN_BYTE
842 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
843 * @arg @ref LL_DMA_MDATAALIGN_WORD
844 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)845 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
846 {
847 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
848 DMA_CCR_MSIZE));
849 }
850
851 /**
852 * @brief Set Channel priority level.
853 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
854 * @param DMAx DMAx Instance
855 * @param Channel This parameter can be one of the following values:
856 * @arg @ref LL_DMA_CHANNEL_1
857 * @arg @ref LL_DMA_CHANNEL_2
858 * @arg @ref LL_DMA_CHANNEL_3
859 * @arg @ref LL_DMA_CHANNEL_4
860 * @arg @ref LL_DMA_CHANNEL_5
861 * @arg @ref LL_DMA_CHANNEL_6
862 * @arg @ref LL_DMA_CHANNEL_7
863 * @param Priority This parameter can be one of the following values:
864 * @arg @ref LL_DMA_PRIORITY_LOW
865 * @arg @ref LL_DMA_PRIORITY_MEDIUM
866 * @arg @ref LL_DMA_PRIORITY_HIGH
867 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
868 * @retval None
869 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)870 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
871 {
872 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
873 Priority);
874 }
875
876 /**
877 * @brief Get Channel priority level.
878 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
879 * @param DMAx DMAx Instance
880 * @param Channel This parameter can be one of the following values:
881 * @arg @ref LL_DMA_CHANNEL_1
882 * @arg @ref LL_DMA_CHANNEL_2
883 * @arg @ref LL_DMA_CHANNEL_3
884 * @arg @ref LL_DMA_CHANNEL_4
885 * @arg @ref LL_DMA_CHANNEL_5
886 * @arg @ref LL_DMA_CHANNEL_6
887 * @arg @ref LL_DMA_CHANNEL_7
888 * @retval Returned value can be one of the following values:
889 * @arg @ref LL_DMA_PRIORITY_LOW
890 * @arg @ref LL_DMA_PRIORITY_MEDIUM
891 * @arg @ref LL_DMA_PRIORITY_HIGH
892 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
893 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)894 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
895 {
896 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
897 DMA_CCR_PL));
898 }
899
900 /**
901 * @brief Set Number of data to transfer.
902 * @note This action has no effect if
903 * channel is enabled.
904 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
905 * @param DMAx DMAx Instance
906 * @param Channel This parameter can be one of the following values:
907 * @arg @ref LL_DMA_CHANNEL_1
908 * @arg @ref LL_DMA_CHANNEL_2
909 * @arg @ref LL_DMA_CHANNEL_3
910 * @arg @ref LL_DMA_CHANNEL_4
911 * @arg @ref LL_DMA_CHANNEL_5
912 * @arg @ref LL_DMA_CHANNEL_6
913 * @arg @ref LL_DMA_CHANNEL_7
914 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
915 * @retval None
916 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)917 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
918 {
919 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
920 DMA_CNDTR_NDT, NbData);
921 }
922
923 /**
924 * @brief Get Number of data to transfer.
925 * @note Once the channel is enabled, the return value indicate the
926 * remaining bytes to be transmitted.
927 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
928 * @param DMAx DMAx Instance
929 * @param Channel This parameter can be one of the following values:
930 * @arg @ref LL_DMA_CHANNEL_1
931 * @arg @ref LL_DMA_CHANNEL_2
932 * @arg @ref LL_DMA_CHANNEL_3
933 * @arg @ref LL_DMA_CHANNEL_4
934 * @arg @ref LL_DMA_CHANNEL_5
935 * @arg @ref LL_DMA_CHANNEL_6
936 * @arg @ref LL_DMA_CHANNEL_7
937 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
938 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)939 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
940 {
941 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
942 DMA_CNDTR_NDT));
943 }
944
945 /**
946 * @brief Configure the Source and Destination addresses.
947 * @note This API must not be called when the DMA channel is enabled.
948 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
949 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
950 * CMAR MA LL_DMA_ConfigAddresses
951 * @param DMAx DMAx Instance
952 * @param Channel This parameter can be one of the following values:
953 * @arg @ref LL_DMA_CHANNEL_1
954 * @arg @ref LL_DMA_CHANNEL_2
955 * @arg @ref LL_DMA_CHANNEL_3
956 * @arg @ref LL_DMA_CHANNEL_4
957 * @arg @ref LL_DMA_CHANNEL_5
958 * @arg @ref LL_DMA_CHANNEL_6
959 * @arg @ref LL_DMA_CHANNEL_7
960 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
961 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
962 * @param Direction This parameter can be one of the following values:
963 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
964 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
965 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
966 * @retval None
967 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)968 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
969 uint32_t DstAddress, uint32_t Direction)
970 {
971 /* Direction Memory to Periph */
972 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
973 {
974 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
975 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
976 }
977 /* Direction Periph to Memory and Memory to Memory */
978 else
979 {
980 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
981 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
982 }
983 }
984
985 /**
986 * @brief Set the Memory address.
987 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
988 * @note This API must not be called when the DMA channel is enabled.
989 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
990 * @param DMAx DMAx Instance
991 * @param Channel This parameter can be one of the following values:
992 * @arg @ref LL_DMA_CHANNEL_1
993 * @arg @ref LL_DMA_CHANNEL_2
994 * @arg @ref LL_DMA_CHANNEL_3
995 * @arg @ref LL_DMA_CHANNEL_4
996 * @arg @ref LL_DMA_CHANNEL_5
997 * @arg @ref LL_DMA_CHANNEL_6
998 * @arg @ref LL_DMA_CHANNEL_7
999 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1000 * @retval None
1001 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1002 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1003 {
1004 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1005 }
1006
1007 /**
1008 * @brief Set the Peripheral address.
1009 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1010 * @note This API must not be called when the DMA channel is enabled.
1011 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1012 * @param DMAx DMAx Instance
1013 * @param Channel This parameter can be one of the following values:
1014 * @arg @ref LL_DMA_CHANNEL_1
1015 * @arg @ref LL_DMA_CHANNEL_2
1016 * @arg @ref LL_DMA_CHANNEL_3
1017 * @arg @ref LL_DMA_CHANNEL_4
1018 * @arg @ref LL_DMA_CHANNEL_5
1019 * @arg @ref LL_DMA_CHANNEL_6
1020 * @arg @ref LL_DMA_CHANNEL_7
1021 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1022 * @retval None
1023 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1024 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1025 {
1026 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
1027 }
1028
1029 /**
1030 * @brief Get Memory address.
1031 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1032 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1033 * @param DMAx DMAx Instance
1034 * @param Channel This parameter can be one of the following values:
1035 * @arg @ref LL_DMA_CHANNEL_1
1036 * @arg @ref LL_DMA_CHANNEL_2
1037 * @arg @ref LL_DMA_CHANNEL_3
1038 * @arg @ref LL_DMA_CHANNEL_4
1039 * @arg @ref LL_DMA_CHANNEL_5
1040 * @arg @ref LL_DMA_CHANNEL_6
1041 * @arg @ref LL_DMA_CHANNEL_7
1042 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1043 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1044 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1045 {
1046 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1047 }
1048
1049 /**
1050 * @brief Get Peripheral address.
1051 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1052 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1053 * @param DMAx DMAx Instance
1054 * @param Channel This parameter can be one of the following values:
1055 * @arg @ref LL_DMA_CHANNEL_1
1056 * @arg @ref LL_DMA_CHANNEL_2
1057 * @arg @ref LL_DMA_CHANNEL_3
1058 * @arg @ref LL_DMA_CHANNEL_4
1059 * @arg @ref LL_DMA_CHANNEL_5
1060 * @arg @ref LL_DMA_CHANNEL_6
1061 * @arg @ref LL_DMA_CHANNEL_7
1062 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1063 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1064 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1065 {
1066 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1067 }
1068
1069 /**
1070 * @brief Set the Memory to Memory Source address.
1071 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1072 * @note This API must not be called when the DMA channel is enabled.
1073 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1074 * @param DMAx DMAx Instance
1075 * @param Channel This parameter can be one of the following values:
1076 * @arg @ref LL_DMA_CHANNEL_1
1077 * @arg @ref LL_DMA_CHANNEL_2
1078 * @arg @ref LL_DMA_CHANNEL_3
1079 * @arg @ref LL_DMA_CHANNEL_4
1080 * @arg @ref LL_DMA_CHANNEL_5
1081 * @arg @ref LL_DMA_CHANNEL_6
1082 * @arg @ref LL_DMA_CHANNEL_7
1083 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1084 * @retval None
1085 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1086 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1087 {
1088 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
1089 }
1090
1091 /**
1092 * @brief Set the Memory to Memory Destination address.
1093 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1094 * @note This API must not be called when the DMA channel is enabled.
1095 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1096 * @param DMAx DMAx Instance
1097 * @param Channel This parameter can be one of the following values:
1098 * @arg @ref LL_DMA_CHANNEL_1
1099 * @arg @ref LL_DMA_CHANNEL_2
1100 * @arg @ref LL_DMA_CHANNEL_3
1101 * @arg @ref LL_DMA_CHANNEL_4
1102 * @arg @ref LL_DMA_CHANNEL_5
1103 * @arg @ref LL_DMA_CHANNEL_6
1104 * @arg @ref LL_DMA_CHANNEL_7
1105 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1106 * @retval None
1107 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1108 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1109 {
1110 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1111 }
1112
1113 /**
1114 * @brief Get the Memory to Memory Source address.
1115 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1116 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1117 * @param DMAx DMAx Instance
1118 * @param Channel This parameter can be one of the following values:
1119 * @arg @ref LL_DMA_CHANNEL_1
1120 * @arg @ref LL_DMA_CHANNEL_2
1121 * @arg @ref LL_DMA_CHANNEL_3
1122 * @arg @ref LL_DMA_CHANNEL_4
1123 * @arg @ref LL_DMA_CHANNEL_5
1124 * @arg @ref LL_DMA_CHANNEL_6
1125 * @arg @ref LL_DMA_CHANNEL_7
1126 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1127 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1128 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1129 {
1130 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1131 }
1132
1133 /**
1134 * @brief Get the Memory to Memory Destination address.
1135 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1136 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1137 * @param DMAx DMAx Instance
1138 * @param Channel This parameter can be one of the following values:
1139 * @arg @ref LL_DMA_CHANNEL_1
1140 * @arg @ref LL_DMA_CHANNEL_2
1141 * @arg @ref LL_DMA_CHANNEL_3
1142 * @arg @ref LL_DMA_CHANNEL_4
1143 * @arg @ref LL_DMA_CHANNEL_5
1144 * @arg @ref LL_DMA_CHANNEL_6
1145 * @arg @ref LL_DMA_CHANNEL_7
1146 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1147 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1148 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1149 {
1150 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1151 }
1152
1153
1154 /**
1155 * @}
1156 */
1157
1158 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1159 * @{
1160 */
1161
1162 /**
1163 * @brief Get Channel 1 global interrupt flag.
1164 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1165 * @param DMAx DMAx Instance
1166 * @retval State of bit (1 or 0).
1167 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1168 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1169 {
1170 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
1171 }
1172
1173 /**
1174 * @brief Get Channel 2 global interrupt flag.
1175 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1176 * @param DMAx DMAx Instance
1177 * @retval State of bit (1 or 0).
1178 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1179 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1180 {
1181 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
1182 }
1183
1184 /**
1185 * @brief Get Channel 3 global interrupt flag.
1186 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1187 * @param DMAx DMAx Instance
1188 * @retval State of bit (1 or 0).
1189 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1190 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1191 {
1192 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
1193 }
1194
1195 /**
1196 * @brief Get Channel 4 global interrupt flag.
1197 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1198 * @param DMAx DMAx Instance
1199 * @retval State of bit (1 or 0).
1200 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1201 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1202 {
1203 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
1204 }
1205
1206 /**
1207 * @brief Get Channel 5 global interrupt flag.
1208 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1209 * @param DMAx DMAx Instance
1210 * @retval State of bit (1 or 0).
1211 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1212 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1213 {
1214 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
1215 }
1216
1217 /**
1218 * @brief Get Channel 6 global interrupt flag.
1219 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1220 * @param DMAx DMAx Instance
1221 * @retval State of bit (1 or 0).
1222 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1223 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1224 {
1225 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
1226 }
1227
1228 /**
1229 * @brief Get Channel 7 global interrupt flag.
1230 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1231 * @param DMAx DMAx Instance
1232 * @retval State of bit (1 or 0).
1233 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1234 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1235 {
1236 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
1237 }
1238
1239 /**
1240 * @brief Get Channel 1 transfer complete flag.
1241 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1242 * @param DMAx DMAx Instance
1243 * @retval State of bit (1 or 0).
1244 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1245 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1246 {
1247 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
1248 }
1249
1250 /**
1251 * @brief Get Channel 2 transfer complete flag.
1252 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1253 * @param DMAx DMAx Instance
1254 * @retval State of bit (1 or 0).
1255 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1256 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1257 {
1258 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
1259 }
1260
1261 /**
1262 * @brief Get Channel 3 transfer complete flag.
1263 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1264 * @param DMAx DMAx Instance
1265 * @retval State of bit (1 or 0).
1266 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1267 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1268 {
1269 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
1270 }
1271
1272 /**
1273 * @brief Get Channel 4 transfer complete flag.
1274 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1275 * @param DMAx DMAx Instance
1276 * @retval State of bit (1 or 0).
1277 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1278 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1279 {
1280 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
1281 }
1282
1283 /**
1284 * @brief Get Channel 5 transfer complete flag.
1285 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1286 * @param DMAx DMAx Instance
1287 * @retval State of bit (1 or 0).
1288 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1289 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1290 {
1291 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
1292 }
1293
1294 /**
1295 * @brief Get Channel 6 transfer complete flag.
1296 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1297 * @param DMAx DMAx Instance
1298 * @retval State of bit (1 or 0).
1299 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1300 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1301 {
1302 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
1303 }
1304
1305 /**
1306 * @brief Get Channel 7 transfer complete flag.
1307 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1308 * @param DMAx DMAx Instance
1309 * @retval State of bit (1 or 0).
1310 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1311 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1312 {
1313 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
1314 }
1315
1316 /**
1317 * @brief Get Channel 1 half transfer flag.
1318 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1319 * @param DMAx DMAx Instance
1320 * @retval State of bit (1 or 0).
1321 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1322 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1323 {
1324 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
1325 }
1326
1327 /**
1328 * @brief Get Channel 2 half transfer flag.
1329 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1330 * @param DMAx DMAx Instance
1331 * @retval State of bit (1 or 0).
1332 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1333 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1334 {
1335 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
1336 }
1337
1338 /**
1339 * @brief Get Channel 3 half transfer flag.
1340 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1341 * @param DMAx DMAx Instance
1342 * @retval State of bit (1 or 0).
1343 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1344 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1345 {
1346 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
1347 }
1348
1349 /**
1350 * @brief Get Channel 4 half transfer flag.
1351 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1352 * @param DMAx DMAx Instance
1353 * @retval State of bit (1 or 0).
1354 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1355 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1356 {
1357 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
1358 }
1359
1360 /**
1361 * @brief Get Channel 5 half transfer flag.
1362 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1363 * @param DMAx DMAx Instance
1364 * @retval State of bit (1 or 0).
1365 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1366 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1367 {
1368 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
1369 }
1370
1371 /**
1372 * @brief Get Channel 6 half transfer flag.
1373 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1374 * @param DMAx DMAx Instance
1375 * @retval State of bit (1 or 0).
1376 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1377 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1378 {
1379 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
1380 }
1381
1382 /**
1383 * @brief Get Channel 7 half transfer flag.
1384 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1385 * @param DMAx DMAx Instance
1386 * @retval State of bit (1 or 0).
1387 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1388 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1389 {
1390 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
1391 }
1392
1393 /**
1394 * @brief Get Channel 1 transfer error flag.
1395 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1396 * @param DMAx DMAx Instance
1397 * @retval State of bit (1 or 0).
1398 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1399 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1400 {
1401 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
1402 }
1403
1404 /**
1405 * @brief Get Channel 2 transfer error flag.
1406 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1407 * @param DMAx DMAx Instance
1408 * @retval State of bit (1 or 0).
1409 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1410 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1411 {
1412 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
1413 }
1414
1415 /**
1416 * @brief Get Channel 3 transfer error flag.
1417 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1418 * @param DMAx DMAx Instance
1419 * @retval State of bit (1 or 0).
1420 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1421 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1422 {
1423 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
1424 }
1425
1426 /**
1427 * @brief Get Channel 4 transfer error flag.
1428 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1429 * @param DMAx DMAx Instance
1430 * @retval State of bit (1 or 0).
1431 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1432 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1433 {
1434 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
1435 }
1436
1437 /**
1438 * @brief Get Channel 5 transfer error flag.
1439 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1440 * @param DMAx DMAx Instance
1441 * @retval State of bit (1 or 0).
1442 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1443 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1444 {
1445 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
1446 }
1447
1448 /**
1449 * @brief Get Channel 6 transfer error flag.
1450 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1451 * @param DMAx DMAx Instance
1452 * @retval State of bit (1 or 0).
1453 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1454 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1455 {
1456 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
1457 }
1458
1459 /**
1460 * @brief Get Channel 7 transfer error flag.
1461 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1462 * @param DMAx DMAx Instance
1463 * @retval State of bit (1 or 0).
1464 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1465 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1466 {
1467 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
1468 }
1469
1470 /**
1471 * @brief Clear Channel 1 global interrupt flag.
1472 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1473 * @param DMAx DMAx Instance
1474 * @retval None
1475 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1476 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1477 {
1478 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
1479 }
1480
1481 /**
1482 * @brief Clear Channel 2 global interrupt flag.
1483 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1484 * @param DMAx DMAx Instance
1485 * @retval None
1486 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1487 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1488 {
1489 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
1490 }
1491
1492 /**
1493 * @brief Clear Channel 3 global interrupt flag.
1494 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1495 * @param DMAx DMAx Instance
1496 * @retval None
1497 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1498 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1499 {
1500 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
1501 }
1502
1503 /**
1504 * @brief Clear Channel 4 global interrupt flag.
1505 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1506 * @param DMAx DMAx Instance
1507 * @retval None
1508 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1509 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1510 {
1511 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
1512 }
1513
1514 /**
1515 * @brief Clear Channel 5 global interrupt flag.
1516 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1517 * @param DMAx DMAx Instance
1518 * @retval None
1519 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1520 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1521 {
1522 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
1523 }
1524
1525 /**
1526 * @brief Clear Channel 6 global interrupt flag.
1527 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1528 * @param DMAx DMAx Instance
1529 * @retval None
1530 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1531 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1532 {
1533 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
1534 }
1535
1536 /**
1537 * @brief Clear Channel 7 global interrupt flag.
1538 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1539 * @param DMAx DMAx Instance
1540 * @retval None
1541 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1542 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1543 {
1544 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
1545 }
1546
1547 /**
1548 * @brief Clear Channel 1 transfer complete flag.
1549 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1550 * @param DMAx DMAx Instance
1551 * @retval None
1552 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1553 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1554 {
1555 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
1556 }
1557
1558 /**
1559 * @brief Clear Channel 2 transfer complete flag.
1560 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1561 * @param DMAx DMAx Instance
1562 * @retval None
1563 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1564 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1565 {
1566 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
1567 }
1568
1569 /**
1570 * @brief Clear Channel 3 transfer complete flag.
1571 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1572 * @param DMAx DMAx Instance
1573 * @retval None
1574 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1575 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1576 {
1577 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
1578 }
1579
1580 /**
1581 * @brief Clear Channel 4 transfer complete flag.
1582 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1583 * @param DMAx DMAx Instance
1584 * @retval None
1585 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1586 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1587 {
1588 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
1589 }
1590
1591 /**
1592 * @brief Clear Channel 5 transfer complete flag.
1593 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1594 * @param DMAx DMAx Instance
1595 * @retval None
1596 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1597 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1598 {
1599 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
1600 }
1601
1602 /**
1603 * @brief Clear Channel 6 transfer complete flag.
1604 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1605 * @param DMAx DMAx Instance
1606 * @retval None
1607 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)1608 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1609 {
1610 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
1611 }
1612
1613 /**
1614 * @brief Clear Channel 7 transfer complete flag.
1615 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1616 * @param DMAx DMAx Instance
1617 * @retval None
1618 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)1619 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1620 {
1621 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
1622 }
1623
1624 /**
1625 * @brief Clear Channel 1 half transfer flag.
1626 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1627 * @param DMAx DMAx Instance
1628 * @retval None
1629 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1630 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1631 {
1632 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
1633 }
1634
1635 /**
1636 * @brief Clear Channel 2 half transfer flag.
1637 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1638 * @param DMAx DMAx Instance
1639 * @retval None
1640 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1641 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1642 {
1643 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
1644 }
1645
1646 /**
1647 * @brief Clear Channel 3 half transfer flag.
1648 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1649 * @param DMAx DMAx Instance
1650 * @retval None
1651 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1652 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1653 {
1654 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
1655 }
1656
1657 /**
1658 * @brief Clear Channel 4 half transfer flag.
1659 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1660 * @param DMAx DMAx Instance
1661 * @retval None
1662 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)1663 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1664 {
1665 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
1666 }
1667
1668 /**
1669 * @brief Clear Channel 5 half transfer flag.
1670 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1671 * @param DMAx DMAx Instance
1672 * @retval None
1673 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)1674 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1675 {
1676 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
1677 }
1678
1679 /**
1680 * @brief Clear Channel 6 half transfer flag.
1681 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1682 * @param DMAx DMAx Instance
1683 * @retval None
1684 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)1685 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1686 {
1687 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
1688 }
1689
1690 /**
1691 * @brief Clear Channel 7 half transfer flag.
1692 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1693 * @param DMAx DMAx Instance
1694 * @retval None
1695 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)1696 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1697 {
1698 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
1699 }
1700
1701 /**
1702 * @brief Clear Channel 1 transfer error flag.
1703 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1704 * @param DMAx DMAx Instance
1705 * @retval None
1706 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1707 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1708 {
1709 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
1710 }
1711
1712 /**
1713 * @brief Clear Channel 2 transfer error flag.
1714 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1715 * @param DMAx DMAx Instance
1716 * @retval None
1717 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1718 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1719 {
1720 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
1721 }
1722
1723 /**
1724 * @brief Clear Channel 3 transfer error flag.
1725 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1726 * @param DMAx DMAx Instance
1727 * @retval None
1728 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1729 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1730 {
1731 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
1732 }
1733
1734 /**
1735 * @brief Clear Channel 4 transfer error flag.
1736 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1737 * @param DMAx DMAx Instance
1738 * @retval None
1739 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)1740 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1741 {
1742 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
1743 }
1744
1745 /**
1746 * @brief Clear Channel 5 transfer error flag.
1747 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
1748 * @param DMAx DMAx Instance
1749 * @retval None
1750 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)1751 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1752 {
1753 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
1754 }
1755
1756 /**
1757 * @brief Clear Channel 6 transfer error flag.
1758 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
1759 * @param DMAx DMAx Instance
1760 * @retval None
1761 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)1762 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
1763 {
1764 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
1765 }
1766
1767 /**
1768 * @brief Clear Channel 7 transfer error flag.
1769 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
1770 * @param DMAx DMAx Instance
1771 * @retval None
1772 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)1773 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
1774 {
1775 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
1776 }
1777
1778 /**
1779 * @}
1780 */
1781
1782 /** @defgroup DMA_LL_EF_IT_Management IT_Management
1783 * @{
1784 */
1785 /**
1786 * @brief Enable Transfer complete interrupt.
1787 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
1788 * @param DMAx DMAx Instance
1789 * @param Channel This parameter can be one of the following values:
1790 * @arg @ref LL_DMA_CHANNEL_1
1791 * @arg @ref LL_DMA_CHANNEL_2
1792 * @arg @ref LL_DMA_CHANNEL_3
1793 * @arg @ref LL_DMA_CHANNEL_4
1794 * @arg @ref LL_DMA_CHANNEL_5
1795 * @arg @ref LL_DMA_CHANNEL_6
1796 * @arg @ref LL_DMA_CHANNEL_7
1797 * @retval None
1798 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1799 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1800 {
1801 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1802 }
1803
1804 /**
1805 * @brief Enable Half transfer interrupt.
1806 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
1807 * @param DMAx DMAx Instance
1808 * @param Channel This parameter can be one of the following values:
1809 * @arg @ref LL_DMA_CHANNEL_1
1810 * @arg @ref LL_DMA_CHANNEL_2
1811 * @arg @ref LL_DMA_CHANNEL_3
1812 * @arg @ref LL_DMA_CHANNEL_4
1813 * @arg @ref LL_DMA_CHANNEL_5
1814 * @arg @ref LL_DMA_CHANNEL_6
1815 * @arg @ref LL_DMA_CHANNEL_7
1816 * @retval None
1817 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1818 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1819 {
1820 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1821 }
1822
1823 /**
1824 * @brief Enable Transfer error interrupt.
1825 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
1826 * @param DMAx DMAx Instance
1827 * @param Channel This parameter can be one of the following values:
1828 * @arg @ref LL_DMA_CHANNEL_1
1829 * @arg @ref LL_DMA_CHANNEL_2
1830 * @arg @ref LL_DMA_CHANNEL_3
1831 * @arg @ref LL_DMA_CHANNEL_4
1832 * @arg @ref LL_DMA_CHANNEL_5
1833 * @arg @ref LL_DMA_CHANNEL_6
1834 * @arg @ref LL_DMA_CHANNEL_7
1835 * @retval None
1836 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1837 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1838 {
1839 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1840 }
1841
1842 /**
1843 * @brief Disable Transfer complete interrupt.
1844 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
1845 * @param DMAx DMAx Instance
1846 * @param Channel This parameter can be one of the following values:
1847 * @arg @ref LL_DMA_CHANNEL_1
1848 * @arg @ref LL_DMA_CHANNEL_2
1849 * @arg @ref LL_DMA_CHANNEL_3
1850 * @arg @ref LL_DMA_CHANNEL_4
1851 * @arg @ref LL_DMA_CHANNEL_5
1852 * @arg @ref LL_DMA_CHANNEL_6
1853 * @arg @ref LL_DMA_CHANNEL_7
1854 * @retval None
1855 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1856 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1857 {
1858 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1859 }
1860
1861 /**
1862 * @brief Disable Half transfer interrupt.
1863 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
1864 * @param DMAx DMAx Instance
1865 * @param Channel This parameter can be one of the following values:
1866 * @arg @ref LL_DMA_CHANNEL_1
1867 * @arg @ref LL_DMA_CHANNEL_2
1868 * @arg @ref LL_DMA_CHANNEL_3
1869 * @arg @ref LL_DMA_CHANNEL_4
1870 * @arg @ref LL_DMA_CHANNEL_5
1871 * @arg @ref LL_DMA_CHANNEL_6
1872 * @arg @ref LL_DMA_CHANNEL_7
1873 * @retval None
1874 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1875 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1876 {
1877 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1878 }
1879
1880 /**
1881 * @brief Disable Transfer error interrupt.
1882 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
1883 * @param DMAx DMAx Instance
1884 * @param Channel This parameter can be one of the following values:
1885 * @arg @ref LL_DMA_CHANNEL_1
1886 * @arg @ref LL_DMA_CHANNEL_2
1887 * @arg @ref LL_DMA_CHANNEL_3
1888 * @arg @ref LL_DMA_CHANNEL_4
1889 * @arg @ref LL_DMA_CHANNEL_5
1890 * @arg @ref LL_DMA_CHANNEL_6
1891 * @arg @ref LL_DMA_CHANNEL_7
1892 * @retval None
1893 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1894 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1895 {
1896 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1897 }
1898
1899 /**
1900 * @brief Check if Transfer complete Interrupt is enabled.
1901 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
1902 * @param DMAx DMAx Instance
1903 * @param Channel This parameter can be one of the following values:
1904 * @arg @ref LL_DMA_CHANNEL_1
1905 * @arg @ref LL_DMA_CHANNEL_2
1906 * @arg @ref LL_DMA_CHANNEL_3
1907 * @arg @ref LL_DMA_CHANNEL_4
1908 * @arg @ref LL_DMA_CHANNEL_5
1909 * @arg @ref LL_DMA_CHANNEL_6
1910 * @arg @ref LL_DMA_CHANNEL_7
1911 * @retval State of bit (1 or 0).
1912 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1913 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1914 {
1915 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1916 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
1917 }
1918
1919 /**
1920 * @brief Check if Half transfer Interrupt is enabled.
1921 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
1922 * @param DMAx DMAx Instance
1923 * @param Channel This parameter can be one of the following values:
1924 * @arg @ref LL_DMA_CHANNEL_1
1925 * @arg @ref LL_DMA_CHANNEL_2
1926 * @arg @ref LL_DMA_CHANNEL_3
1927 * @arg @ref LL_DMA_CHANNEL_4
1928 * @arg @ref LL_DMA_CHANNEL_5
1929 * @arg @ref LL_DMA_CHANNEL_6
1930 * @arg @ref LL_DMA_CHANNEL_7
1931 * @retval State of bit (1 or 0).
1932 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1933 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1934 {
1935 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1936 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
1937 }
1938
1939 /**
1940 * @brief Check if Transfer error Interrupt is enabled.
1941 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
1942 * @param DMAx DMAx Instance
1943 * @param Channel This parameter can be one of the following values:
1944 * @arg @ref LL_DMA_CHANNEL_1
1945 * @arg @ref LL_DMA_CHANNEL_2
1946 * @arg @ref LL_DMA_CHANNEL_3
1947 * @arg @ref LL_DMA_CHANNEL_4
1948 * @arg @ref LL_DMA_CHANNEL_5
1949 * @arg @ref LL_DMA_CHANNEL_6
1950 * @arg @ref LL_DMA_CHANNEL_7
1951 * @retval State of bit (1 or 0).
1952 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1953 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1954 {
1955 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1956 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
1957 }
1958
1959 /**
1960 * @}
1961 */
1962
1963 #if defined(USE_FULL_LL_DRIVER)
1964 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
1965 * @{
1966 */
1967
1968 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
1969 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
1970 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
1971
1972 /**
1973 * @}
1974 */
1975 #endif /* USE_FULL_LL_DRIVER */
1976
1977 /**
1978 * @}
1979 */
1980
1981 /**
1982 * @}
1983 */
1984
1985 #endif /* DMA1 || DMA2 */
1986
1987 /**
1988 * @}
1989 */
1990
1991 #ifdef __cplusplus
1992 }
1993 #endif
1994
1995 #endif /* __STM32L1xx_LL_DMA_H */
1996
1997 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1998