1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the people's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 #ifndef __SUN8IW18_CODEC_H 33 #define __SUN8IW18_CODEC_H 34 35 #define SUNXI_CODEC_BASE_ADDR (0x05096000) 36 37 #define SUNXI_DAC_DPC 0x00 38 #define SUNXI_DAC_FIFO_CTL 0x10 39 #define SUNXI_DAC_FIFO_STA 0x14 40 #define SUNXI_DAC_TXDATA 0X20 41 #define SUNXI_DAC_CNT 0x24 42 #define SUNXI_DAC_DG 0x28 43 44 #define SUNXI_ADC_FIFO_CTL 0x30 45 #define SUNXI_ADC_FIFO_STA 0x38 46 #define SUNXI_ADC_RXDATA 0x40 47 #define SUNXI_ADC_CNT 0x44 48 #define SUNXI_ADC_DG 0x4C 49 50 /* DAP */ 51 #define SUNXI_DAC_DAP_CTL 0xf0 52 #define SUNXI_ADC_DAP_CTL 0xf8 53 54 #define AC_DAC_DRC_HHPFC (0x100) 55 #define AC_DAC_DRC_LHPFC (0x104) 56 #define AC_DAC_DRC_CTL (0x108) 57 #define AC_DAC_DRC_LPFHAT (0x10c) 58 #define AC_DAC_DRC_LPFLAT (0x110) 59 #define AC_DAC_DRC_RPFHAT (0x114) 60 #define AC_DAC_DRC_RPFLAT (0x118) 61 #define AC_DAC_DRC_LPFHRT (0x11c) 62 #define AC_DAC_DRC_LPFLRT (0x120) 63 #define AC_DAC_DRC_RPFHRT (0x124) 64 #define AC_DAC_DRC_RPFLRT (0x128) 65 #define AC_DAC_DRC_LRMSHAT (0x12c) 66 #define AC_DAC_DRC_LRMSLAT (0x130) 67 #define AC_DAC_DRC_RRMSHAT (0x134) 68 #define AC_DAC_DRC_RRMSLAT (0x138) 69 #define AC_DAC_DRC_HCT (0x13c) 70 #define AC_DAC_DRC_LCT (0x140) 71 #define AC_DAC_DRC_HKC (0x144) 72 #define AC_DAC_DRC_LKC (0x148) 73 #define AC_DAC_DRC_HOPC (0x14c) 74 #define AC_DAC_DRC_LOPC (0x150) 75 #define AC_DAC_DRC_HLT (0x154) 76 #define AC_DAC_DRC_LLT (0x158) 77 #define AC_DAC_DRC_HKI (0x15c) 78 #define AC_DAC_DRC_LKI (0x160) 79 #define AC_DAC_DRC_HOPL (0x164) 80 #define AC_DAC_DRC_LOPL (0x168) 81 #define AC_DAC_DRC_HET (0x16c) 82 #define AC_DAC_DRC_LET (0x170) 83 #define AC_DAC_DRC_HKE (0x174) 84 #define AC_DAC_DRC_LKE (0x178) 85 #define AC_DAC_DRC_HOPE (0x17c) 86 #define AC_DAC_DRC_LOPE (0x180) 87 #define AC_DAC_DRC_HKN (0x184) 88 #define AC_DAC_DRC_LKN (0x188) 89 #define AC_DAC_DRC_SFHAT (0x18c) 90 #define AC_DAC_DRC_SFLAT (0x190) 91 #define AC_DAC_DRC_SFHRT (0x194) 92 #define AC_DAC_DRC_SFLRT (0x198) 93 #define AC_DAC_DRC_MXGHS (0x19c) 94 #define AC_DAC_DRC_MXGLS (0x1a0) 95 #define AC_DAC_DRC_MNGHS (0x1a4) 96 #define AC_DAC_DRC_MNGLS (0x1a8) 97 #define AC_DAC_DRC_EPSHC (0x1ac) 98 #define AC_DAC_DRC_EPSLC (0x1b0) 99 #define AC_DAC_DRC_OPT (0x1b4) 100 #define AC_DAC_DRC_HPFHGAIN (0x1b8) 101 #define AC_DAC_DRC_HPFLGAIN (0x1bc) 102 103 /* 104 * DAC_DRC Control Register 105 * AC_DAC_DRC_CTL:codecbase+0x108 106 */ 107 #define DAC_DRC_CTL_COMPLETE (15) 108 #define DAC_DRC_CTL_SIGNAL_DEL_TIMESET (8) 109 #define DAC_DRC_CTL_DELAY_USE_BUF (7) 110 #define DAC_DRC_CTL_GAIN_MAXLIM_EN (6) 111 #define DAC_DRC_CTL_GAIN_MINLIM_EN (5) 112 #define DAC_DRC_CTL_CONTROL_DRC_EN (4) 113 #define DAC_DRC_CTL_SIGNAL_FUN_SEL (3) 114 #define DAC_DRC_CTL_DEL_FUN_EN (2) 115 #define DAC_DRC_CTL_DRC_LT_EN (1) 116 #define DAC_DRC_CTL_DRC_ET_EN (0) 117 118 /* 119 * DAC_DRC Left Peak Filter High Attack Time Coef Register 120 * AC_DAC_DRC_LPFHAT:codecbase+0x10c 121 */ 122 #define DAC_DRC_LPFHAT_ATT_TIME_PARA_SET (0) 123 124 /* 125 * DAC_DRC Left Peak Filter Low Attack Time Coef Register 126 * AC_DAC_DRC_LPFLAT:codecbase+0x110 127 */ 128 #define DAC_DRC_LPFLAT_ATT_TIME_PARA_SET (0) 129 130 /* 131 * DAC_DRC Right Peak Filter High Attack Time Coef Register 132 * AC_DAC_DRC_RPFHAT:codecbase+0x114 133 */ 134 #define DAC_DRC_RPFHAT_ATT_TIME_PARA_SET (0) 135 136 /* 137 * DAC_DRC Right Peak Filter Low Attack Time Coef Register 138 * AC_DAC_DRC_RPFLAT:codecbase+0x118 139 */ 140 #define DAC_DRC_RPFLAT_ATT_TIME_PARA_SET (0) 141 142 /* 143 * DAC_DRC Left Peak Filter High Release Time Coef Register 144 * AC_DAC_DRC_LPFHRT:codecbase+0x11c 145 */ 146 #define DAC_DRC_LPFHRT_REL_TIME_PARA_SET (0) 147 148 /* 149 * DAC_DRC Left Peak Filter Low Release Time Coef Register 150 * AC_DAC_DRC_LPFLRT:codecbase+0x120 151 */ 152 #define DAC_DRC_LPFLRT_REL_TIME_PARA_SET (0) 153 154 /* 155 * DAC_DRC Right Peak Filter High Release Time Coef Register 156 * AC_DAC_DRC_RPFHRT:codecbase+0x124 157 */ 158 #define DAC_DRC_RPFHRT_REL_TIME_PARA_SET (0) 159 160 /* 161 * DAC_DRC Left Peak Filter Low Release Time Coef Register 162 * AC_DAC_DRC_RPFLRT:codecbase+0x128 163 */ 164 #define DAC_DRC_RPFLRT_REL_TIME_PARA_SET (0) 165 166 /* 167 * DAC_DRC Left RMS Filter High Coef Register 168 * AC_DAC_DRC_LRMSHAT:codecbase+0x12c 169 */ 170 #define DAC_DRC_LRMSHAT_AVE_TIME_PARA_SET (0) 171 172 /* 173 * DAC_DRC Left RMS Filter Low Coef Register 174 * AC_DAC_DRC_LRMSLAT:codecbase+0x130 175 */ 176 #define DAC_DRC_LRMSHAT_AVE_TIME_PARA_SET (0) 177 178 /* 179 * DAC_DRC Right RMS Filter High Coef Register 180 * AC_DAC_DRC_RRMSHAT:codecbase+0x134 181 */ 182 #define DAC_DRC_RRMSHAT_AVE_TIME_PARA_SET (0) 183 184 /* 185 * DAC_DRC Right RMS Filter Low Coef Register 186 * AC_DAC_DRC_RRMSLAT:codecbase+0x138 187 */ 188 #define DAC_DRC_RRMSLAT_AVE_TIME_PARA_SET (0) 189 190 /* 191 * DAC_DRC Compressor Theshold High Setting Register 192 * AC_DAC_DRC_HCT:codecbase+0x13c 193 */ 194 #define DAC_DRC_HCT_COMP_THRES_SET (0) 195 196 /* 197 * DAC_DRC Compressor Theshold Low Setting Register 198 * AC_DAC_DRC_LCT:codecbase+0x140 199 */ 200 #define DAC_DRC_LCT_COMP_THRES_SET (0) 201 202 /* 203 * DAC_DRC Compressor Slope High Setting Register 204 * AC_DAC_DRC_HKC:codecbase+0x144 205 */ 206 #define DAC_DRC_HKC_SLOPE_SET (0) 207 208 /* 209 * DAC_DRC Compressor Slope Low Setting Register 210 * AC_DAC_DRC_LKC:codecbase+0x148 211 */ 212 #define DAC_DRC_LKC_SLOPE_SET (0) 213 214 /* 215 * DAC_DRC Compressor High Output at Compressor Threshold Register 216 * AC_DAC_DRC_HOPC:codecbase+0x14c 217 */ 218 #define DAC_DRC_HOPC_COMP_OUT (0) 219 220 /* 221 * DAC_DRC Compressor Low Output at Compressor Threshold Register 222 * AC_DAC_DRC_LOPC:codecbase+0x150 223 */ 224 #define DAC_DRC_LOPC_COMP_OUT (0) 225 226 /* 227 * DAC_DRC Limiter Threshold High Setting Register 228 * AC_DAC_DRC_HLT:codecbase+0x154 229 */ 230 #define DAC_DRC_HLT_LIM_THRES_SET (0) 231 232 /* 233 * DAC_DRC Limiter Threshold Low Setting Register 234 * AC_DAC_DRC_LLT:codecbase+0x158 235 */ 236 #define DAC_DRC_LLT_LIM_THRES_SET (0) 237 238 /* 239 * DAC_DRC Limiter Slope High Setting Register 240 * AC_DAC_DRC_HKI:codecbase+0x15c 241 */ 242 #define DAC_DRC_HKI_LIM_SLOPE_SET (0) 243 244 /* 245 * DAC_DRC Limiter Slope Low Setting Register 246 * AC_DAC_DRC_LKI:codecbase+0x160 247 */ 248 #define DAC_DRC_LKI_LIM_SLOPE_SET (0) 249 250 /* 251 * DAC_DRC Limiter High Output at Limiter Threshold 252 * AC_DAC_DRC_HOPL:codecbase+0x164 253 */ 254 #define DAC_DRC_HOPL_LIM_THRES_OUT (0) 255 256 /* 257 * DAC_DRC Limiter Low Output at Limiter Threshold 258 * AC_DAC_DRC_LOPL:codecbase+0x168 259 */ 260 #define DAC_DRC_LOPL_LIM_THRES_OUT (0) 261 262 /* 263 * DAC_DRC Expander Theshold High Setting Register 264 * AC_DAC_DRC_HET:codecbase+0x16c 265 */ 266 #define DAC_DRC_HET_EXPAN_THRES_SET (0) 267 268 /* 269 * DAC_DRC Expander Theshold Low Setting Register 270 * AC_DAC_DRC_LET:codecbase+0x170 271 */ 272 #define DAC_DRC_LET_EXPAN_THRES_SET (0) 273 274 /* 275 * DAC_DRC Expander Slope High Setting Register 276 * AC_DAC_DRC_HKE:codecbase+0x174 277 */ 278 #define DAC_DRC_HKE_EXPAN_SLOPE_SET (0) 279 280 /* 281 * DAC_DRC Expander Slope Low Setting Register 282 * AC_DAC_DRC_LKE:codecbase+0x178 283 */ 284 #define DAC_DRC_LKE_EXPAN_SLOPE_SET (0) 285 286 /* 287 * DAC_DRC Expander High Output at Expander Threshold 288 * AC_DAC_DRC_HOPE:codecbase+0x17c 289 */ 290 #define DAC_DRC_HOPE_EXPAN_DET_EQU (0) 291 292 /* 293 * DAC_DRC Expander Low Output at Expander Threshold 294 * AC_DAC_DRC_LOPE:codecbase+0x180 295 */ 296 #define DAC_DRC_LOPE_EXPAN_DET_EQU (0) 297 298 /* 299 * DAC_DRC Linear Slope High Setting Register 300 * AC_DAC_DRC_HKN:codecbase+0x184 301 */ 302 #define DAC_DRC_HKN_SLOPE_LIN_DET_EQU (0) 303 304 /* 305 * DAC_DRC Linear Slope Low Setting Register 306 * AC_DAC_DRC_LKN:codecbase+0x188 307 */ 308 #define DAC_DRC_LKN_SLOPE_LIN_DET_EQU (0) 309 310 /* 311 * DAC_DRC Smooth filter Gain High Attack Time Coef Register 312 * AC_DAC_DRC_SFHAT:codecbase+0x18c 313 */ 314 #define DAC_DRC_SFHAT_ATT_TIME_PARAM_SET (0) 315 316 /* 317 * DAC_DRC Smooth filter Gain Low Attack Time Coef Register 318 * AC_DAC_DRC_SFLAT:codecbase+0x190 319 */ 320 #define DAC_DRC_SFLAT_ATT_TIME_PARAM_SET (0) 321 322 /* 323 * DAC_DRC Smooth filter Gain High Release Time Coef Register 324 * AC_DAC_DRC_SFHRT:codecbase+0x194 325 */ 326 #define DAC_DRC_SFHRT_REL_TIME_PARAM_SET (0) 327 328 /* 329 * DAC_DRC Smooth filter Gain Low Release Time Coef Register 330 * AC_DAC_DRC_SFLRT:codecbase+0x198 331 */ 332 #define DAC_DRC_SFLRT_REL_TIME_PARAM_SET (0) 333 334 /* 335 * DAC_DRC MAX Gain High Setting Register 336 * AC_DAC_DRC_MXGHS:codecbase+0x19c 337 */ 338 #define DAC_DRC_MXGHS_GAIN_SET_DET_EUQ (0) 339 340 /* 341 * DAC_DRC MAX Gain Low Setting Register 342 * AC_DAC_DRC_MXGLS:codecbase+0x1A0 343 */ 344 #define DAC_DRC_MXGLS_GAIN_SET_DET_EUQ (0) 345 346 /* 347 * DAC_DRC Min Gain High Setting Register 348 * AC_DAC_DRC_MNGHS:codecbase+0x1A4 349 */ 350 #define DAC_DRC_MNGHS_GAIN_SET_DET_EUQ (0) 351 352 /* 353 * DAC_DRC Min Gain Low Setting Register 354 * AC_DAC_DRC_MNGHS:codecbase+0x1A8 355 */ 356 #define DAC_DRC_MNGLS_GAIN_SET_DET_EUQ (0) 357 358 /* 359 * DAC_DRC Expander Smooth Time High Coef Register 360 * AC_DAC_DRC_EPSHC:codecbase+0x1AC 361 */ 362 #define DAC_DRC_EPSHC_GAIN_FILT_REL_ATT_PARA (0) 363 364 /* 365 * DAC_DRC Expander Smooth Time Low Coef Register 366 * AC_DAC_DRC_EPSLC:codecbase+0x1B0 367 */ 368 #define DAC_DRC_EPSLC_GAIN_FILT_REL_ATT_PARA (0) 369 370 /* 371 * DAC_DRC Optimum Register 372 * AC_DAC_DRC_OPT:codecbase+0x1B4 373 */ 374 #define DAC_DRC_OPT_GS_EXP_COEFF_USE_SEL (10) 375 #define DAC_DRC_OPT_GS_COEFF_MOD_SEL (9) 376 #define DAC_DRC_OPT_MIN_ENERGY (8) 377 #define DAC_DRC_OPT_RMS_DET_MOD (7) 378 #define DAC_DRC_OPT_DATA_OUTPUT (6) 379 #define DAC_DRC_OPT_GAIN_DEFAULT_VAL (5) 380 #define DAC_DRC_OPT_HYS_GAIN_SMOOTH_DEL_TIME (0) 381 382 /* 383 * DAC_DRC HPF Gain High Coef Register 384 * AC_DAC_DRC_HPFHGAIN:codecbase+0x1B8 385 */ 386 #define DAC_DRC_HPFHGAIN_GAIN_HPF_COEFF_SET (0) 387 388 /* 389 * DAC_DRC HPF Gain Low Coef Register 390 * AC_DAC_DRC_HPFLGAIN:codecbase+0x1Bc 391 */ 392 #define DAC_DRC_HPFLGAIN_GAIN_HPF_COEFF_SET (0) 393 394 /* 395 * ADC DRC 396 */ 397 #define AC_ADC_DRC_HHPFC (0x200) 398 #define AC_ADC_DRC_LHPFC (0x204) 399 #define AC_ADC_DRC_CTRL (0x208) 400 #define AC_ADC_DRC_LPFHAT (0x20c) 401 #define AC_ADC_DRC_LPFLAT (0x210) 402 #define AC_ADC_DRC_RPFHAT (0x214) 403 #define AC_ADC_DRC_RPFLAT (0x218) 404 #define AC_ADC_DRC_LPFHRT (0x21c) 405 #define AC_ADC_DRC_LPFLRT (0x220) 406 #define AC_ADC_DRC_RPFHRT (0x224) 407 #define AC_ADC_DRC_RPFLRT (0x228) 408 #define AC_ADC_DRC_LRMSHAT (0x22c) 409 #define AC_ADC_DRC_LRMSLAT (0x230) 410 #define AC_ADC_DRC_RRMSHAT (0x234) 411 #define AC_ADC_DRC_RRMSLAT (0x238) 412 #define AC_ADC_DRC_HCT (0x23c) 413 #define AC_ADC_DRC_LCT (0x240) 414 #define AC_ADC_DRC_HKC (0x244) 415 #define AC_ADC_DRC_LKC (0x248) 416 #define AC_ADC_DRC_HOPC (0x24c) 417 #define AC_ADC_DRC_LOPC (0x250) 418 #define AC_ADC_DRC_HLT (0x254) 419 #define AC_ADC_DRC_LLT (0x258) 420 #define AC_ADC_DRC_HKI (0x25c) 421 #define AC_ADC_DRC_LKI (0x260) 422 #define AC_ADC_DRC_HOPL (0x264) 423 #define AC_ADC_DRC_LOPL (0x268) 424 #define AC_ADC_DRC_HET (0x26c) 425 #define AC_ADC_DRC_LET (0x270) 426 #define AC_ADC_DRC_HKE (0x274) 427 #define AC_ADC_DRC_LKE (0x278) 428 #define AC_ADC_DRC_HOPE (0x27c) 429 #define AC_ADC_DRC_LOPE (0x280) 430 #define AC_ADC_DRC_HKN (0x284) 431 #define AC_ADC_DRC_LKN (0x288) 432 #define AC_ADC_DRC_SFHAT (0x28c) 433 #define AC_ADC_DRC_SFLAT (0x290) 434 #define AC_ADC_DRC_SFHRT (0x294) 435 #define AC_ADC_DRC_SFLRT (0x298) 436 #define AC_ADC_DRC_MXGHS (0x29c) 437 #define AC_ADC_DRC_MXGLS (0x2a0) 438 #define AC_ADC_DRC_MNGHS (0x2a4) 439 #define AC_ADC_DRC_MNGLS (0x2a8) 440 #define AC_ADC_DRC_EPSHC (0x2ac) 441 #define AC_ADC_DRC_EPSLC (0x2b0) 442 #define AC_ADC_DRC_OPT (0x2b4) 443 #define AC_ADC_DRC_HPFHGAIN (0x2b8) 444 #define AC_ADC_DRC_HPFLGAIN (0x2bc) 445 446 #define AC_VERSION (0x2c0) 447 448 449 /* 450 * ADC_DRC High HPF Coef Register 451 * AC_ADC_DRC_HHPFC:codecbase+0x200 452 */ 453 #define ADC_DRC_HHPFC_COEF_SET (0) 454 455 /* 456 * ADC_DRC Low HPF Coef Register 457 * AC_ADC_DRC_LHPFC:codecbase+0x204 458 */ 459 #define ADC_DRC_LHPFC_COEF_SET (0) 460 461 /* 462 * ADC_DRC Control Register 463 * AC_ADC_DRC_CTRL:codecbase+0x208 464 */ 465 #define ADC_DRC_CTL_COMPLETE (15) 466 #define ADC_DRC_CTL_SIGNAL_DEL_TIMESET (8) 467 #define ADC_DRC_CTL_DELAY_USE_BUF (7) 468 #define ADC_DRC_CTL_GAIN_MAXLIM_EN (6) 469 #define ADC_DRC_CTL_GAIN_MINLIM_EN (5) 470 #define ADC_DRC_CTL_CONTROL_DRC_EN (4) 471 #define ADC_DRC_CTL_SIGNAL_FUN_SEL (3) 472 #define ADC_DRC_CTL_DEL_FUN_EN (2) 473 #define ADC_DRC_CTL_DRC_LT_EN (1) 474 #define ADC_DRC_CTL_DRC_ET_EN (0) 475 476 /* 477 * ADC_DRC Left Peak Filter High Attack Time Coef Register 478 * AC_ADC_DRC_LPFHAT:codecbase+0x20c 479 */ 480 #define ADC_DRC_LPFHAT_ATT_TIME_PARA_SET (0) 481 482 /* 483 * ADC_DRC Left Peak Filter Low Attack Time Coef Register 484 * AC_ADC_DRC_LPFLAT:codecbase+0x210 485 */ 486 #define ADC_DRC_LPFLAT_ATT_TIME_PARA_SET (0) 487 488 /* 489 * ADC_DRC Right Peak Filter High Attack Time Coef Register 490 * AC_ADC_DRC_RPFHAT:codecbase+0x214 491 */ 492 #define ADC_DRC_RPFHAT_ATT_TIME_PARA_SET (0) 493 494 /* 495 * ADC_DRC Right Peak Filter Low Attack Time Coef Register 496 * AC_ADC_DRC_RPFLAT:codecbase+0x218 497 */ 498 #define ADC_DRC_RPFLAT_ATT_TIME_PARA_SET (0) 499 500 /* 501 * ADC_DRC Left Peak Filter High Release Time Coef Register 502 * AC_ADC_DRC_LPFHRT:codecbase+0x21c 503 */ 504 #define DRC7_LPFHRT_REL_TIME_PARA_SET (0) 505 506 /* 507 * ADC_DRC Left Peak Filter Low Release Time Coef Register 508 * AC_ADC_DRC_LPFLRT:codecbase+0x220 509 */ 510 #define ADC_DRC_LPFLRT_REL_TIME_PARA_SET (0) 511 512 /* 513 * ADC_DRC Right Peak Filter High Release Time Coef Register 514 * AC_ADC_DRC_RPFHRT:codecbase+0x224 515 */ 516 #define ADC_DRC_RPFHRT_REL_TIME_PARA_SET (0) 517 518 /* 519 * ADC_DRC Left Peak Filter Low Release Time Coef Register 520 * AC_ADC_DRC_RPFLRT:codecbase+0x228 521 */ 522 #define ADC_DRC_RPFLRT_REL_TIME_PARA_SET (0) 523 524 /* 525 * ADC_DRC Left RMS Filter High Coef Register 526 * AC_ADC_DRC_LRMSHAT:codecbase+0x22c 527 */ 528 #define ADC_DRC_LRMSHAT_AVE_TIME_PARA_SET (0) 529 530 /* 531 * ADC_DRC Left RMS Filter Low Coef Register 532 * AC_ADC_DRC_LRMSLAT:codecbase+0x230 533 */ 534 #define ADC_DRC_LRMSHAT_AVE_TIME_PARA_SET (0) 535 536 /* 537 * ADC_DRC Right RMS Filter High Coef Register 538 * AC_ADC_DRC_RRMSHAT:codecbase+0x234 539 */ 540 #define ADC_DRC_RRMSHAT_AVE_TIME_PARA_SET (0) 541 542 /* 543 * ADC_DRC Right RMS Filter Low Coef Register 544 * AC_ADC_DRC_RRMSLAT:codecbase+0x238 545 */ 546 #define ADC_DRC_RRMSLAT_AVE_TIME_PARA_SET (0) 547 548 /* 549 * ADC_DRC Compressor Theshold High Setting Register 550 * AC_ADC_DRC_HCT:codecbase+0x23c 551 */ 552 #define ADC_DRC_HCT_COMP_THRES_SET (0) 553 554 /* 555 * ADC_DRC Compressor Theshold Low Setting Register 556 * AC_ADC_DRC_LCT:codecbase+0x240 557 */ 558 #define ADC_DRC_LCT_COMP_THRES_SET (0) 559 560 /* 561 * ADC_DRC Compressor Slope High Setting Register 562 * AC_ADC_DRC_HKC:codecbase+0x244 563 */ 564 #define ADC_DRC_HKC_SLOPE_SET (0) 565 566 /* 567 * ADC_DRC Compressor Slope Low Setting Register 568 * AC_ADC_DRC_LKC:codecbase+0x248 569 */ 570 #define ADC_DRC_LKC_SLOPE_SET (0) 571 572 /* 573 * ADC_DRC Compressor High Output at Compressor Threshold Register 574 * AC_ADC_DRC_HOPC:codecbase+0x24c 575 */ 576 #define ADC_DRC_HOPC_COMP_OUT (0) 577 578 /* 579 * ADC_DRC Compressor Low Output at Compressor Threshold Register 580 * AC_ADC_DRC_LOPC:codecbase+0x250 581 */ 582 #define ADC_DRC_LOPC_COMP_OUT (0) 583 584 /* 585 * ADC_DRC Limiter Threshold High Setting Register 586 * AC_ADC_DRC_HLT:codecbase+0x254 587 */ 588 #define ADC_DRC_HLT_LIM_THRES_SET (0) 589 590 /* 591 * ADC_DRC Limiter Threshold Low Setting Register 592 * AC_ADC_DRC_LLT:codecbase+0x258 593 */ 594 #define ADC_DRC_LLT_LIM_THRES_SET (0) 595 596 /* 597 * ADC_DRC Limiter Slope High Setting Register 598 * AC_ADC_DRC_HKI:codecbase+0x25c 599 */ 600 #define ADC_DRC_HKI_LIM_SLOPE_SET (0) 601 602 /* 603 * ADC_DRC Limiter Slope Low Setting Register 604 * AC_ADC_DRC_LKI:codecbase+0x260 605 */ 606 #define ADC_DRC_LKI_LIM_SLOPE_SET (0) 607 608 /* 609 * ADC_DRC Limiter High Output at Limiter Threshold 610 * AC_ADC_DRC_HOPL:codecbase+0x264 611 */ 612 #define ADC_DRC_HOPL_LIM_THRES_OUT (0) 613 614 /* 615 * ADC_DRC Limiter Low Output at Limiter Threshold 616 * AC_ADC_DRC_LOPL:codecbase+0x268 617 */ 618 #define ADC_DRC_LOPL_LIM_THRES_OUT (0) 619 620 /* 621 * ADC_DRC Expander Theshold High Setting Register 622 * AC_ADC_DRC_HET:codecbase+0x26c 623 */ 624 #define ADC_DRC_HET_EXPAN_THRES_SET (0) 625 626 /* 627 * ADC_DRC Expander Theshold Low Setting Register 628 * AC_ADC_DRC_LET:codecbase+0x270 629 */ 630 #define ADC_DRC_LET_EXPAN_THRES_SET (0) 631 632 /* 633 * ADC_DRC Expander Slope High Setting Register 634 * AC_ADC_DRC_HKE:codecbase+0x274 635 */ 636 #define ADC_DRC_HKE_EXPAN_SLOPE_SET (0) 637 638 /* 639 * ADC_DRC Expander Slope Low Setting Register 640 * AC_ADC_DRC_LKE:codecbase+0x278 641 */ 642 #define ADC_DRC_LKE_EXPAN_SLOPE_SET (0) 643 644 /* 645 * ADC_DRC Expander High Output at Expander Threshold 646 * AC_ADC_DRC_HOPE:codecbase+0x27c 647 */ 648 #define ADC_DRC_HOPE_EXPAN_DET_EQU (0) 649 650 /* 651 * ADC_DRC Expander Low Output at Expander Threshold 652 * AC_ADC_DRC_LOPE:codecbase+0x280 653 */ 654 #define ADC_DRC_LOPE_EXPAN_DET_EQU (0) 655 656 /* 657 * ADC_DRC Linear Slope High Setting Register 658 * AC_ADC_DRC_HKN:codecbase+0x284 659 */ 660 #define ADC_DRC_HKN_SLOPE_LIN_DET_EQU (0) 661 662 /* 663 * ADC_DRC Linear Slope Low Setting Register 664 * AC_ADC_DRC_LKN:codecbase+0x288 665 */ 666 #define ADC_DRC_LKN_SLOPE_LIN_DET_EQU (0) 667 668 /* 669 * ADC_DRC Smooth filter Gain High Attack Time Coef Register 670 * AC_ADC_DRC_SFHAT:codecbase+0x28c 671 */ 672 #define ADC_DRC_SFHAT_ATT_TIME_PARAM_SET (0) 673 674 /* 675 * ADC_DRC Smooth filter Gain Low Attack Time Coef Register 676 * AC_ADC_DRC_SFLAT:codecbase+0x290 677 */ 678 #define ADC_DRC_SFLAT_ATT_TIME_PARAM_SET (0) 679 680 /* 681 * ADC_DRC Smooth filter Gain High Release Time Coef Register 682 * AC_ADC_DRC_SFHRT:codecbase+0x294 683 */ 684 #define ADC_DRC_SFHRT_REL_TIME_PARAM_SET (0) 685 686 /* 687 * ADC_DRC Smooth filter Gain Low Release Time Coef Register 688 * AC_ADC_DRC_SFLRT:codecbase+0x298 689 */ 690 #define ADC_DRC_SFLRT_REL_TIME_PARAM_SET (0) 691 692 /* 693 * ADC_DRC MAX Gain High Setting Register 694 * AC_ADC_DRC_MXGHS:codecbase+0x29c 695 */ 696 #define ADC_DRC_MXGHS_GAIN_SET_DET_EUQ (0) 697 698 /* 699 * ADC_DRC MAX Gain Low Setting Register 700 * AC_ADC_DRC_MXGLS:codecbase+0x2A0 701 */ 702 #define ADC_DRC_MXGLS_GAIN_SET_DET_EUQ (0) 703 704 /* 705 * ADC_DRC Min Gain High Setting Register 706 * AC_ADC_DRC_MNGHS:codecbase+0x2A4 707 */ 708 #define ADC_DRC_MNGHS_GAIN_SET_DET_EUQ (0) 709 710 /* 711 * ADC_DRC Min Gain Low Setting Register 712 * AC_ADC_DRC_MNGHS:codecbase+0x2A8 713 */ 714 #define ADC_DRC_MNGLS_GAIN_SET_DET_EUQ (0) 715 716 /* 717 * ADC_DRC Expander Smooth Time High Coef Register 718 * AC_ADC_DRC_EPSHC:codecbase+0x2AC 719 */ 720 #define ADC_DRC_EPSHC_GAIN_FILT_REL_ATT_PARA (0) 721 722 /* 723 * ADC_DRC Expander Smooth Time Low Coef Register 724 * AC_ADC_DRC_EPSLC:codecbase+0x2B0 725 */ 726 #define ADC_DRC_EPSLC_GAIN_FILT_REL_ATT_PARA (0) 727 728 /* 729 * ADC_DRC Optimum Register 730 * AC_ADC_DRC_OPT:codecbase+0x2B4 731 */ 732 #define ADC_DRC_OPT_GS_EXP_COEFF_USE_SEL (10) 733 #define ADC_DRC_OPT_GS_COEFF_MOD_SEL (9) 734 #define ADC_DRC_OPT_MIN_ENERGY (8) 735 #define ADC_DRC_OPT_RMS_DET_MOD (7) 736 #define ADC_DRC_OPT_DATA_OUTPUT (6) 737 #define ADC_DRC_OPT_GAIN_DEFAULT_VAL (5) 738 #define ADC_DRC_OPT_HYS_GAIN_SMOOTH_DEL_TIME (0) 739 740 /* 741 * ADC_DRC HPF Gain High Coef Register 742 * AC_ADC_DRC_HPFHGAIN:codecbase+0x2B8 743 */ 744 #define ADC_DRC_HPFHGAIN_GAIN_HPF_COEFF_SET (0) 745 746 /* 747 * ADC_DRC HPF Gain Low Coef Register 748 * AC_ADC_DRC_HPFLGAIN:codecbase+0x2Bc 749 */ 750 #define ADC_DRC_HPFLGAIN_GAIN_HPF_COEFF_SET (0) 751 752 753 /* Analog register base - Digital register base */ 754 /*SUNXI_PR_CFG is to tear the acreg and dcreg, it is of no real meaning*/ 755 #define SUNXI_PR_CFG 0x300 756 #define SUNXI_HP_CTL (SUNXI_PR_CFG + 0x00) 757 #define SUNXI_MIX_DAC_CTL (SUNXI_PR_CFG + 0x03) 758 #define SUNXI_LINEOUT_CTL0 (SUNXI_PR_CFG + 0x05) 759 #define SUNXI_LINEOUT_CTL1 (SUNXI_PR_CFG + 0x06) 760 #define SUNXI_MIC1_CTL (SUNXI_PR_CFG + 0x07) 761 #define SUNXI_MIC2_MIC3_CTL (SUNXI_PR_CFG + 0x08) 762 #define SUNXI_LADCMIX_SRC (SUNXI_PR_CFG + 0x09) 763 #define SUNXI_RADCMIX_SRC (SUNXI_PR_CFG + 0x0A) 764 #define SUNXI_XADCMIX_SRC (SUNXI_PR_CFG + 0x0B) 765 766 #define SUNXI_ADC_CTL (SUNXI_PR_CFG + 0x0D) 767 #define SUNXI_MBIAS_CTL (SUNXI_PR_CFG + 0x0E) 768 #define SUNXI_APT_REG (SUNXI_PR_CFG + 0x0F) 769 #define SUNXI_OP_BIAS_CTL0 (SUNXI_PR_CFG + 0x10) 770 #define SUNXI_OP_BIAS_CTL1 (SUNXI_PR_CFG + 0x11) 771 #define SUNXI_ZC_VOL_CTL (SUNXI_PR_CFG + 0x12) 772 #define SUNXI_BIAS_CAL_CTRL (SUNXI_PR_CFG + 0x15) 773 774 /* SUNXI_DAC_DPC:0x00 */ 775 #define EN_DAC 31 776 #define MODQU 25 777 #define DWA_EN 24 778 #define HPF_EN 18 779 #define DVOL 12 780 #define DAC_HUB_EN 0 781 782 /* SUNXI_DAC_FIFO_CTL:0x10 */ 783 #define DAC_FS 29 784 #define FIR_VER 28 785 #define SEND_LASAT 26 786 #define FIFO_MODE 24 787 #define DAC_DRQ_CLR_CNT 21 788 #define TX_TRIG_LEVEL 8 789 #define DAC_MONO_EN 6 790 #define TX_SAMPLE_BITS 5 791 #define DAC_DRQ_EN 4 792 #define DAC_IRQ_EN 3 793 #define FIFO_UNDERRUN_IRQ_EN 2 794 #define FIFO_OVERRUN_IRQ_EN 1 795 #define FIFO_FLUSH 0 796 797 /* SUNXI_DAC_FIFO_STA:0x14 */ 798 #define TX_EMPTY 23 799 #define DAC_TXE_CNT 8 800 #define DAC_TXE_INT 3 801 #define DAC_TXU_INT 2 802 #define DAC_TXO_INT 1 803 804 /* SUNXI_DAC_DG:0x28 */ 805 #define DAC_MODU_SEL 11 806 #define DAC_PATTERN_SEL 9 807 #define CODEC_CLK_SELECT 8 808 #define DA_SWP 6 809 #define ADDA_LOOP_MODE 0 810 811 /* SUNXI_ADC_FIFO_CTL:0x30 */ 812 #define ADC_FS 29 813 #define EN_AD 28 814 #define ADCFDT 26 815 #define ADCDFEN 25 816 #define RX_FIFO_MODE 24 817 #define RX_SAMPLE_BITS 16 818 #define ADC_CHAN_SEL 12 819 #define RX_FIFO_TRG_LEVEL 4 820 #define ADC_DRQ_EN 3 821 #define ADC_IRQ_EN 2 822 #define ADC_OVERRUN_IRQ_EN 1 823 #define ADC_FIFO_FLUSH 0 824 825 /* SUNXI_ADC_FIFO_STA:0x38 */ 826 #define ADC_RXA 23 827 #define ADC_RXA_CNT 8 828 #define ADC_RXA_INT 3 829 #define ADC_RXO_INT 1 830 831 /* SUNXI_ADC_DG:0x4C */ 832 #define AD_SWP 4 833 834 /* SUNXI_DAC_DAP_CTL:0xf0 */ 835 #define DDAP_EN 31 836 #define DDAP_DRC_EN 29 837 #define DDAP_HPF_EN 28 838 839 /* SUNXI_ADC_DAP_CTL:0xf8 */ 840 #define ADC_DAP0_EN 31 841 #define ADC_DRC0_EN 29 842 #define ADC_HPF0_EN 28 843 #define ADC_DAP1_EN 27 844 #define ADC_DRC1_EN 25 845 #define ADC_HPF1_EN 24 846 847 848 /* SUNXI_PR_CFG:0x07010280 */ 849 #define AC_PR_RST 28 850 #define AC_PR_RW 24 851 #define AC_PR_ADDR 16 852 #define ADDA_PR_WDAT 8 853 #define ADDA_PR_RDAT 0 854 855 /* SUNXI_HP_CTL:0x00 */ 856 #define PA_CLK_GATE 7 857 858 /* SUNXI_MIX_DAC_CTL:0x03 */ 859 #define DACALEN 6 860 861 /* SUNXI_LINEOUT_CTL0:0x05 */ 862 #define LINEOUTL_EN 7 863 #define LINEOUTR_EN 6 864 #define LINEOUTL_SRC 5 865 #define LINEOUTR_SRC 4 866 867 /* SUNXI_LINEOUT_CTL1:0x06 */ 868 #define LINEOUT_VOL 0 869 870 /* SUNXI_MIC1_CTL:0x07 */ 871 #define MIC1AMPEN 3 872 #define MIC1BOOST 0 873 874 /* SUNXI_MIC2_MIC3_CTL:0x08 */ 875 #define MIC3AMPEN 7 876 #define MIC3BOOST 4 877 #define MIC2AMPEN 3 878 #define MIC2BOOST 0 879 880 /* SUNXI_LADCMIX_SRC:0x09 */ 881 #define LADC_MIC3_STAGE 4 882 #define LADC_MIC2_STAGE 3 883 #define LADC_MIC1_STAGE 2 884 #define LADC_DACL 1 885 #define LADCMIXMUTE 0 886 887 /* SUNXI_RADCMIX_SRC:0x0A*/ 888 #define RADC_MIC3_STAGE 4 889 #define RADC_MIC2_STAGE 3 890 #define RADC_MIC1_STAGE 2 891 #define RADC_DACL 0 892 #define RADCMIXMUTE 0 893 894 /* SUNXI_XADCMIX_SRC:0x0B*/ 895 #define XADC_MIC3_STAGE 4 896 #define XADC_MIC2_STAGE 3 897 #define XADC_MIC1_STAGE 2 898 #define XADC_DACL 1 899 #define XADCMIXMUTE 0 900 901 /* SUNXI_ADC_CTL:0x0D */ 902 #define ADCREN 7 903 #define ADCLEN 6 904 #define ADCXEN 4 905 #define DITHER_SEL 3 906 #define ADCG 0 907 908 /* SUNXI_MBIAS_CTL:0x0E */ 909 #define MMICBIASEN 7 910 #define MBIASSEL 5 911 912 /* SUNXI_APT_REG:0x0F */ 913 #define MMIC_BIAS_CHOP_EN 7 914 #define MMIC_BIAS_CHOP_CLK_SEL 5 915 #define DITHER 4 916 #define DITHER_CLK_SEL 2 917 #define BIHE_CTRL 0 918 919 /* SUNXI_OP_BIAS_CTL0:0x10 */ 920 #define OPDRV_OPEAR_CUR 6 921 #define OPADC1_BIAS_CUR 4 922 #define OPADC2_BIAS_CUR 2 923 #define OPAAF_BIAS_CUR 0 924 925 /* SUNXI_OP_BIAS_CTL1:0x11 */ 926 #define OPMIC_BIAS_CUR 6 927 #define OPVR_BIAS_CUR 4 928 #define OPDAC_BIAS_CUR 2 929 #define OPMIX_BIAS_CUR 0 930 931 /* SUNXI_ZC_VOL_CTL:0x12 */ 932 #define ZC_EN 7 933 #define ZC_TIMEOUT_SEL 6 934 #define USB_BIAS_CUR 0 935 936 /* SUNXI_BIAS_CAL_CTRL:0x15 */ 937 #define CUR_TEST_SEL 6 938 939 #endif /* __SUN8IW18_CODEC_H */ 940