1 /** 2 * drivers/usb/host/sunxi_hci.h 3 * (C) Copyright 2010-2015 4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 5 * yangnaitian, 2011-5-24, create this file 6 * 7 * Include file for SUNXI HCI Host Controller Driver 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 */ 15 16 #ifndef __SUNXI_HCI_SUNXI_H__ 17 #define __SUNXI_HCI_SUNXI_H__ 18 19 //#include <linux/delay.h> 20 //#include <linux/types.h> 21 // 22 //#include <linux/io.h> 23 //#include <linux/irq.h> 24 //#include <linux/of_gpio.h> 25 //#include <linux/sunxi-gpio.h> 26 // 27 //#include <log.h> 28 // 29 //#include <linux/pm_wakeirq.h> 30 //#include <linux/regulator/consumer.h> 31 32 #include <platform_usb.h> 33 #include <usb_os_platform.h> 34 #include <stdlib.h> 35 #include <hal_clk.h> 36 37 38 extern int usb_disabled(void); 39 40 #if defined(CONFIG_AW_AXP) 41 extern s32 axp_usb_vbus_output(int high); 42 #endif 43 44 #define DMSG_ERR(format, args...) pr_err("hci: "format, ##args) 45 #define DMSG_PRINT(stuff...) printk(stuff) 46 47 #define HCI_USBC_NO "hci_ctrl_no" 48 49 50 #define HCI0_USBC_NO 0 51 #define HCI1_USBC_NO 1 52 #define HCI2_USBC_NO 2 53 #define HCI3_USBC_NO 3 54 55 56 //static uint32_t hci_irq_num[] = 57 //{ 58 // SUNXI_USB_EHCI0_IRQ, 59 // SUNXI_USB_EHCI1_IRQ, 60 //}; 61 #define STANDBY_TIMEOUT 30000 62 63 /* 64 * Support Low-power mode USB standby. 65 */ 66 #if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW9) \ 67 || defined(CONFIG_ARCH_SUN50IW10) 68 #define SUNXI_USB_STANDBY_LOW_POW_MODE 69 #endif 70 /*no cpus*/ 71 #if defined(CONFIG_ARCH_SUN50IW9) || defined(CONFIG_ARCH_SUN50IW10) 72 #define SUNXI_USB_STANDBY_NEW_MODE 73 #endif 74 75 #if 0 76 #define DMSG_DEBUG DMSG_PRINT 77 #else 78 #define DMSG_DEBUG(...) 79 #endif 80 81 #if 1 82 #define DMSG_INFO DMSG_PRINT 83 #else 84 #define DMSG_INFO(...) 85 #endif 86 87 #if 1 88 #define DMSG_PANIC DMSG_ERR 89 #else 90 #define DMSG_PANIC(...) 91 #endif 92 93 #define USBC_Readb(reg) (*((volatile unsigned char *)(long)(reg))) 94 #define USBC_Readw(reg) (*((volatile unsigned short *)(reg))) 95 #define USBC_Readl(reg) (*((volatile unsigned int *)(long)(reg))) 96 97 #define USBC_Writeb(value, reg) (*((volatile unsigned char *)(long)(reg)) = (unsigned char)(value)) 98 #define USBC_Writew(value, reg) (*((volatile unsigned short *)(reg)) = (unsigned short)(value)) 99 #define USBC_Writel(value, reg) (*((volatile unsigned int *)(long)(reg)) = (unsigned int)(value)) 100 101 #define USBC_REG_test_bit_b(bp, reg) (USBC_Readb(reg) & (1 << (bp))) 102 #define USBC_REG_test_bit_w(bp, reg) (USBC_Readw(reg) & (1 << (bp))) 103 #define USBC_REG_test_bit_l(bp, reg) (USBC_Readl(reg) & (1 << (bp))) 104 105 #define USBC_REG_set_bit_b(bp, reg) (USBC_Writeb((USBC_Readb(reg) | (1 << (bp))), (reg))) 106 #define USBC_REG_set_bit_w(bp, reg) (USBC_Writew((USBC_Readw(reg) | (1 << (bp))), (reg))) 107 #define USBC_REG_set_bit_l(bp, reg) (USBC_Writel((USBC_Readl(reg) | (1 << (bp))), (reg))) 108 109 #define USBC_REG_clear_bit_b(bp, reg) (USBC_Writeb((USBC_Readb(reg) & (~(1 << (bp)))), (reg))) 110 #define USBC_REG_clear_bit_w(bp, reg) (USBC_Writew((USBC_Readw(reg) & (~(1 << (bp)))), (reg))) 111 #define USBC_REG_clear_bit_l(bp, reg) (USBC_Writel((USBC_Readl(reg) & (~(1 << (bp)))), (reg))) 112 113 #define SUNXI_USB_EHCI_BASE_OFFSET 0x00 114 #define SUNXI_USB_OHCI_BASE_OFFSET 0x400 115 #define SUNXI_USB_EHCI_LEN 0x58 116 #define SUNXI_USB_OHCI_LEN 0x58 117 118 #define SUNXI_USB_EHCI_TIME_INT 0x30 119 #define SUNXI_USB_EHCI_STANDBY_IRQ_STATUS 1 120 #define SUNXI_USB_EHCI_STANDBY_IRQ 2 121 122 #define SUNXI_USB_PMU_IRQ_ENABLE 0x800 123 #define SUNXI_HCI_CTRL_3 0X808 124 #define SUNXI_HCI_PHY_CTRL 0x810 125 #define SUNXI_HCI_PHY_TUNE 0x818 126 #define SUNXI_HCI_UTMI_PHY_STATUS 0x824 127 #define SUNXI_HCI_CTRL_3_REMOTE_WAKEUP 3 128 #define SUNXI_HCI_RC16M_CLK_ENBALE 2 129 #define SUNXI_HCI_PHY_CTRL_SIDDQ 3 130 131 #define SUNXI_OTG_PHY_CTRL 0x410 132 #define SUNXI_OTG_PHY_CFG 0x420 133 #define SUNXI_OTG_PHY_STATUS 0x424 134 #define SUNXI_USBC_REG_INTUSBE 0x0050 135 136 #define EHCI_CAP_OFFSET (0x00) 137 #define EHCI_CAP_LEN (0x10) 138 139 #define EHCI_CAP_CAPLEN (EHCI_CAP_OFFSET + 0x00) 140 #define EHCI_CAP_HCIVER (EHCI_CAP_OFFSET + 0x00) 141 #define EHCI_CAP_HCSPAR (EHCI_CAP_OFFSET + 0x04) 142 #define EHCI_CAP_HCCPAR (EHCI_CAP_OFFSET + 0x08) 143 #define EHCI_CAP_COMPRD (EHCI_CAP_OFFSET + 0x0c) 144 145 146 #define EHCI_OPR_OFFSET (EHCI_CAP_OFFSET + EHCI_CAP_LEN) 147 148 #define EHCI_OPR_USBCMD (EHCI_OPR_OFFSET + 0x00) 149 #define EHCI_OPR_USBSTS (EHCI_OPR_OFFSET + 0x04) 150 #define EHCI_OPR_USBINTR (EHCI_OPR_OFFSET + 0x08) 151 #define EHCI_OPR_FRINDEX (EHCI_OPR_OFFSET + 0x0c) 152 #define EHCI_OPR_CRTLDSS (EHCI_OPR_OFFSET + 0x10) 153 #define EHCI_OPR_PDLIST (EHCI_OPR_OFFSET + 0x14) 154 #define EHCI_OPR_ASLIST (EHCI_OPR_OFFSET + 0x18) 155 #define EHCI_OPR_CFGFLAG (EHCI_OPR_OFFSET + 0x40) 156 #define EHCI_OPR_PORTSC (EHCI_OPR_OFFSET + 0x44) 157 158 /** 159 * PORT Control and Status Register 160 * port_no is 0 based, 0, 1, 2, ..... 161 * 162 * Reg EHCI_OPR_PORTSC 163 */ 164 165 /* Port Test Control bits */ 166 #define EHCI_PORTSC_PTC_MASK (0xf<<16) 167 #define EHCI_PORTSC_PTC_DIS (0x0<<16) 168 #define EHCI_PORTSC_PTC_J (0x1<<16) 169 #define EHCI_PORTSC_PTC_K (0x2<<16) 170 #define EHCI_PORTSC_PTC_SE0NAK (0x3<<16) 171 #define EHCI_PORTSC_PTC_PACKET (0x4<<16) 172 #define EHCI_PORTSC_PTC_FORCE (0x5<<16) 173 174 #define EHCI_PORTSC_OWNER (0x1<<13) 175 #define EHCI_PORTSC_POWER (0x1<<12) 176 177 #define EHCI_PORTSC_LS_MASK (0x3<<10) 178 #define EHCI_PORTSC_LS_SE0 (0x0<<10) 179 #define EHCI_PORTSC_LS_J (0x2<<10) 180 #define EHCI_PORTSC_LS_K (0x1<<10) 181 #define EHCI_PORTSC_LS_UDF (0x3<<10) 182 183 #define EHCI_PORTSC_RESET (0x1<<8) 184 #define EHCI_PORTSC_SUSPEND (0x1<<7) 185 #define EHCI_PORTSC_RESUME (0x1<<6) 186 #define EHCI_PORTSC_OCC (0x1<<5) 187 #define EHCI_PORTSC_OC (0x1<<4) 188 #define EHCI_PORTSC_PEC (0x1<<3) 189 #define EHCI_PORTSC_PE (0x1<<2) 190 #define EHCI_PORTSC_CSC (0x1<<1) 191 #define EHCI_PORTSC_CCS (0x1<<0) 192 193 #define EHCI_PORTSC_CHANGE (EHCI_PORTSC_OCC | EHCI_PORTSC_PEC | EHCI_PORTSC_CSC) 194 195 #define SUNXI_USB_HCI_DEBUG 196 197 #define KEY_USB_ENABLE "usb_used" 198 #define KEY_USB_DRVVBUS_TYPE "usb_drv_vbus_type" 199 #define KEY_USB_DRVVBUS_GPIO "usb_drv_vbus_gpio" 200 #define KEY_USB_REGULATOR_IO "usb_regulator_io" 201 #define KEY_USB_REGULATOR_IO_VOL "usb_regulator_vol" 202 #define KEY_USB_WAKEUP_SUSPEND "usb_wakeup_suspend" 203 #define KEY_USB_HSIC_USBED "usb_hsic_used" 204 #define KEY_USB_HSIC_CTRL "usb_hsic_ctrl" 205 #define KEY_USB_HSIC_RDY_GPIO "usb_hsic_rdy_gpio" 206 #define KEY_USB_HSIC_REGULATOR_IO "usb_hsic_regulator_io" 207 #define KEY_WAKEUP_SOURCE "wakeup-source" 208 #define KEY_USB_PORT_TYPE "usb_port_type" 209 #define KEY_USB_DRIVER_LEVEL "usbh_driver_level" 210 #define KEY_USB_IRQ_FLAG "usbh_irq_flag" 211 212 /* xHCI */ 213 #define XHCI_RESOURCES_NUM 2 214 #define XHCI_REGS_START 0x0 215 #define XHCI_REGS_END 0x7fff 216 217 /* xHCI Operational Registers */ 218 #define XHCI_OP_REGS_HCUSBCMD 0X0020 219 #define XHCI_OP_REGS_HCUSBSTS 0X0024 220 #define XHCI_OP_REGS_HCPORT1SC 0X0420 221 #define XHCI_OP_REGS_HCPORT1PMSC 0X0424 222 223 #define SUNXI_GLOBALS_REGS_START 0xc100 224 #define SUNXI_GLOBALS_REGS_END 0xc6ff 225 226 /* Global Registers */ 227 #define SUNXI_GLOBALS_REGS_GCTL 0xc110 228 #define SUNXI_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 229 #define SUNXI_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 230 231 /* Interface Status and Control Register */ 232 #define SUNXI_APP 0x10000 233 #define SUNXI_PIPE_CLOCK_CONTROL 0x10014 234 #define SUNXI_PHY_TUNE_LOW 0x10018 235 #define SUNXI_PHY_TUNE_HIGH 0x1001c 236 #define SUNXI_PHY_EXTERNAL_CONTROL 0x10020 237 238 /* Bit fields */ 239 240 /* Global Configuration Register */ 241 #define SUNXI_GCTL_PRTCAPDIR(n) ((n) << 12) 242 #define SUNXI_GCTL_PRTCAP_HOST 1 243 #define SUNXI_GCTL_PRTCAP_DEVICE 2 244 #define SUNXI_GCTL_PRTCAP_OTG 3 245 #define SUNXI_GCTL_SOFITPSYNC (0x01 << 10) 246 #define SUNXI_GCTL_CORESOFTRESET (1 << 11) 247 248 /* Global USB2 PHY Configuration Register n */ 249 #define SUNXI_USB2PHYCFG_SUSPHY (0x01 << 6) 250 #define SUNXI_USB2PHYCFG_PHYSOFTRST (1 << 31) 251 252 /* Global USB3 PIPE Control Register */ 253 #define SUNXI_USB3PIPECTL_PHYSOFTRST (1 << 31) 254 255 /* USB2.0 Interface Status and Control Register */ 256 #define SUNXI_APP_FOCE_VBUS (0x03 << 12) 257 258 /* PIPE Clock Control Register */ 259 #define SUNXI_PPC_PIPE_CLK_OPEN (0x01 << 6) 260 261 /* PHY External Control Register */ 262 #define SUNXI_PEC_EXTERN_VBUS (0x03 << 1) 263 #define SUNXI_PEC_SSC_EN (0x01 << 24) 264 #define SUNXI_PEC_REF_SSP_EN (0x01 << 26) 265 266 /* PHY Tune High Register */ 267 #define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19) 268 #define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13) 269 #define SUNXI_TX_SWING_FULL(n) ((n) << 6) 270 #define SUNXI_LOS_BIAS(n) ((n) << 3) 271 #define SUNXI_TXVBOOSTLVL(n) ((n) << 0) 272 273 /* HCI UTMI PHY TUNE */ 274 #define SUNXI_TX_VREF_TUNE_OFFSET 8 275 #define SUNXI_TX_RISE_TUNE_OFFSET 4 276 #define SUNXI_TX_RES_TUNE_OFFSET 2 277 #define SUNXI_TX_PREEMPAMP_TUNE_OFFSET 0 278 #define SUNXI_TX_VREF_TUNE (0xf << SUNXI_TX_VREF_TUNE_OFFSET) 279 #define SUNXI_TX_RISE_TUNE (0x3 << SUNXI_TX_RISE_TUNE_OFFSET) 280 #define SUNXI_TX_RES_TUNE (0x3 << SUNXI_TX_RES_TUNE_OFFSET) 281 #define SUNXI_TX_PREEMPAMP_TUNE (0x3 << SUNXI_TX_PREEMPAMP_TUNE_OFFSET) 282 283 284 enum sunxi_usbc_used { 285 SUNXI_USB_DISABLE = 0, 286 SUNXI_USB_ENABLE, 287 }; 288 289 /*usb_type*/ 290 enum sunxi_usbc_type { 291 SUNXI_USB_UNKNOWN = 0, 292 SUNXI_USB_EHCI, 293 SUNXI_USB_OHCI, 294 SUNXI_USB_XHCI, 295 }; 296 297 enum usb_drv_vbus_type { 298 USB_DRV_VBUS_TYPE_NULL = 0, 299 USB_DRV_VBUS_TYPE_GIPO, 300 USB_DRV_VBUS_TYPE_AXP, 301 }; 302 303 /* 0: device only; 1: host only; 2: otg */ 304 enum usb_port_type { 305 USB_PORT_TYPE_DEVICE = 0, 306 USB_PORT_TYPE_HOST, 307 USB_PORT_TYPE_OTG, 308 }; 309 310 enum usb_wakeup_source_type { 311 SUPER_STANDBY = 0, 312 USB_STANDBY, 313 NORMAL_STANDBY, 314 }; 315 316 // static hal_clk_id_t ehci_clk[] = 317 // { 318 // HAL_CLK_PERIPH_USBEHCI0, 319 // HAL_CLK_PERIPH_USBEHCI1, 320 // }; 321 322 // static hal_clk_id_t phy_clk[] = 323 // { 324 // SUNXI_CLK_USB0, 325 // SUNXI_CLK_USB1, 326 // }; 327 328 struct sunxi_hci_hcd { 329 uint32_t usbc_no; /* usb controller number */ 330 uint32_t irq_no; /* interrupt number */ 331 char hci_name[32]; /* hci name */ 332 int usbc_type; /* usb controller type*/ 333 334 struct resource *usb_base_res; /* USB resources */ 335 struct resource *usb_base_req; /* USB resources */ 336 uint32_t usb_vbase; /* USB base address */ 337 338 uint32_t otg_vbase; /* USB base address */ 339 340 uint32_t ehci_base; 341 uint32_t ehci_reg_length; 342 uint32_t *ohci_base; 343 uint32_t ohci_reg_length; 344 345 struct resource *sram_base_res; /* SRAM resources */ 346 struct resource *sram_base_req; /* SRAM resources */ 347 uint32_t *sram_vbase; /* SRAM base address */ 348 uint32_t sram_reg_start; 349 uint32_t sram_reg_length; 350 351 struct resource *clock_base_res; /* clock resources */ 352 struct resource *clock_base_req; /* clock resources */ 353 uint32_t *clock_vbase; /* clock base address */ 354 uint32_t clock_reg_start; 355 uint32_t clock_reg_length; 356 357 struct resource *gpio_base_res; /* gpio resources */ 358 struct resource *gpio_base_req; /* gpio resources */ 359 uint32_t *gpio_vbase; /* gpio base address */ 360 uint32_t gpio_reg_start; 361 uint32_t gpio_reg_length; 362 363 struct resource *sdram_base_res; /* sdram resources */ 364 struct resource *sdram_base_req; /* sdram resources */ 365 uint32_t *sdram_vbase; /* sdram base address */ 366 uint32_t sdram_reg_start; 367 uint32_t sdram_reg_length; 368 369 struct platform_device *pdev; 370 struct hc_gen_dev *hcd; 371 372 struct clk *ahb; /* ahb clock handle */ 373 struct clk *mod_usb; /* mod_usb otg clock handle */ 374 struct clk *mod_usbphy; /* PHY0 clock handle */ 375 struct clk *hsic_usbphy; /* hsic clock handle */ 376 struct clk *pll_hsic; /* pll_hsic clock handle */ 377 struct clk *clk_usbhsic12m; /* pll_hsic clock handle */ 378 379 struct clk *clk_usbohci12m; /* clk_usbohci12m clock handle */ 380 struct clk *clk_hoscx2; /* clk_hoscx2 clock handle */ 381 struct clk *clk_hosc; /* clk_hosc clock handle */ 382 struct clk *clk_losc; /* clk_losc clock handle */ 383 384 uint32_t clk_is_open; /* is usb clock open */ 385 386 hal_clk_id_t bus_clk_id; 387 hal_clk_id_t phy_clk_id; 388 uint32_t reset_phy_clk; 389 uint32_t reset_bus_clk; 390 hal_clk_id_t ohci_clk_id; 391 392 hal_clk_t bus_clk; 393 hal_clk_t phy_clk; 394 hal_clk_t ohci_clk; 395 396 struct reset_control *reset_hci; 397 struct reset_control *reset_phy; 398 399 //struct gpio_config drv_vbus_gpio_set; 400 int drv_vbus_gpio_set; 401 402 const char *regulator_io; 403 const char *used_status; 404 int regulator_value; 405 struct regulator *regulator_io_hdle; 406 enum usb_drv_vbus_type drv_vbus_type; 407 const char *drv_vbus_name; 408 const char *det_vbus_name; 409 int drv_vbus_gpio; 410 int usb_irq_flag; 411 int usb_driver_level; 412 u32 drv_vbus_gpio_valid; 413 u32 usb_restrict_valid; 414 uint8_t power_flag; /* flag. power on or not */ 415 struct regulator *supply; 416 417 int used; /* flag. in use or not */ 418 uint8_t probe; /* hc initialize */ 419 uint8_t no_suspend; /* when usb is being enable, stop system suspend */ 420 enum usb_port_type port_type; /* usb port type */ 421 int wakeup_suspend; /* flag. not suspend */ 422 423 int wakeup_source_flag; 424 425 int (*open_clock)(struct sunxi_hci_hcd *sunxi_hci, u32 ohci); 426 int (*close_clock)(struct sunxi_hci_hcd *sunxi_hci, u32 ohci); 427 void (*set_power)(struct sunxi_hci_hcd *sunxi_hci, int is_on); 428 void (*port_configure)(struct sunxi_hci_hcd *sunxi_hci, u32 enable); 429 void (*usb_passby)(struct sunxi_hci_hcd *sunxi_hci, u32 enable); 430 void (*hci_phy_ctrl)(struct sunxi_hci_hcd *sunxi_hci, u32 enable); 431 #if 0 432 /* xhci */ 433 struct resource xhci_resources[XHCI_RESOURCES_NUM]; 434 spinlock_t lock; 435 struct device *dev; 436 void *mem; 437 uint32_t *regs; 438 size_t regs_size; 439 uint32_t *xhci_base; 440 uint32_t xhci_reg_length; 441 #endif 442 /* resume work */ 443 //struct work_struct resume_work; 444 //struct completion standby_complete; 445 }; 446 447 #ifdef CONFIG_PM 448 extern atomic_t g_sunxi_usb_super_standby; 449 #endif 450 451 int sunxi_hci_standby_completion(int usbc_type); 452 int init_sunxi_hci(int usbc_type, int hci_num); 453 int exit_sunxi_hci(struct sunxi_hci_hcd *sunxi_hci); 454 int sunxi_get_hci_num(struct platform_device *pdev); 455 void sunxi_set_host_hisc_rdy(struct sunxi_hci_hcd *sunxi_hci, int is_on); 456 void sunxi_set_host_vbus(struct sunxi_hci_hcd *sunxi_hci, int is_on); 457 int usb_phyx_tp_write(struct sunxi_hci_hcd *sunxi_hci, 458 int addr, int data, int len); 459 int usb_phyx_write(struct sunxi_hci_hcd *sunxi_hci, int data); 460 int usb_phyx_read(struct sunxi_hci_hcd *sunxi_hci); 461 int usb_phyx_tp_read(struct sunxi_hci_hcd *sunxi_hci, int addr, int len); 462 int sunxi_usb_enable_xhci(void); 463 int sunxi_usb_disable_xhci(void); 464 #ifdef SUNXI_USB_STANDBY_LOW_POW_MODE 465 void sunxi_hci_set_siddq(struct sunxi_hci_hcd *sunxi_hci, int is_on); 466 void sunxi_hci_set_wakeup_ctrl(struct sunxi_hci_hcd *sunxi_hci, int is_on); 467 void sunxi_hci_set_rc_clk(struct sunxi_hci_hcd *sunxi_hci, int is_on); 468 void sunxi_hci_set_standby_irq(struct sunxi_hci_hcd *sunxi_hci, int is_on); 469 void sunxi_hci_clean_standby_irq(struct sunxi_hci_hcd *sunxi_hci); 470 #endif 471 472 int hci_clock_init(struct sunxi_hci_hcd *sunxi_hci); 473 int open_clock(struct sunxi_hci_hcd *sunxi_hci, u32 ohci); 474 void usb_passby(struct sunxi_hci_hcd *sunxi_hci, u32 enable); 475 int close_clock(struct sunxi_hci_hcd *sunxi_hci, u32 ohci); 476 477 void sunxi_set_vbus(struct sunxi_hci_hcd *sunxi_hci, int is_on); 478 void sunxi_hci_get_config_param(struct sunxi_hci_hcd *sunxi_hci); 479 void usb_new_phy_adjust(struct sunxi_hci_hcd *sunxi_hci, int driver_level); 480 #endif /* __SUNXI_HCI_SUNXI_H__ */ 481 482