1 /*
2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
3 *
4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
5 * the the People's Republic of China and other countries.
6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission.
7 *
8 * DISCLAIMER
9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
16 *
17 *
18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
30 * OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #ifndef __SUNXI_HAL_PHY_H__
34 #define __SUNXI_HAL_PHY_H__
35
36 #include <stdint.h>
37 #include <sunxi_hal_mii.h>
38 #include <sunxi_hal_mdio.h>
39 #include <aw_list.h>
40
41 #define PHY_MAX_ADDR 32
42
43 /* Indicates what features are supported by the interface. */
44 #define SUPPORTED_10baseT_Half (1 << 0)
45 #define SUPPORTED_10baseT_Full (1 << 1)
46 #define SUPPORTED_100baseT_Half (1 << 2)
47 #define SUPPORTED_100baseT_Full (1 << 3)
48 #define SUPPORTED_1000baseT_Half (1 << 4)
49 #define SUPPORTED_1000baseT_Full (1 << 5)
50 #define SUPPORTED_Autoneg (1 << 6)
51 #define SUPPORTED_TP (1 << 7)
52 #define SUPPORTED_AUI (1 << 8)
53 #define SUPPORTED_MII (1 << 9)
54 #define SUPPORTED_FIBRE (1 << 10)
55 #define SUPPORTED_BNC (1 << 11)
56 #define SUPPORTED_10000baseT_Full (1 << 12)
57 #define SUPPORTED_Pause (1 << 13)
58 #define SUPPORTED_Asym_Pause (1 << 14)
59 #define SUPPORTED_2500baseX_Full (1 << 15)
60 #define SUPPORTED_Backplane (1 << 16)
61 #define SUPPORTED_1000baseKX_Full (1 << 17)
62 #define SUPPORTED_10000baseKX4_Full (1 << 18)
63 #define SUPPORTED_10000baseKR_Full (1 << 19)
64 #define SUPPORTED_10000baseR_FEC (1 << 20)
65 #define SUPPORTED_1000baseX_Half (1 << 21)
66 #define SUPPORTED_1000baseX_Full (1 << 22)
67
68 /* Indicates what features are advertised by the interface. */
69 #define ADVERTISED_10baseT_Half (1 << 0)
70 #define ADVERTISED_10baseT_Full (1 << 1)
71 #define ADVERTISED_100baseT_Half (1 << 2)
72 #define ADVERTISED_100baseT_Full (1 << 3)
73 #define ADVERTISED_1000baseT_Half (1 << 4)
74 #define ADVERTISED_1000baseT_Full (1 << 5)
75 #define ADVERTISED_Autoneg (1 << 6)
76 #define ADVERTISED_TP (1 << 7)
77 #define ADVERTISED_AUI (1 << 8)
78 #define ADVERTISED_MII (1 << 9)
79 #define ADVERTISED_FIBRE (1 << 10)
80 #define ADVERTISED_BNC (1 << 11)
81 #define ADVERTISED_10000baseT_Full (1 << 12)
82 #define ADVERTISED_Pause (1 << 13)
83 #define ADVERTISED_Asym_Pause (1 << 14)
84 #define ADVERTISED_2500baseX_Full (1 << 15)
85 #define ADVERTISED_Backplane (1 << 16)
86 #define ADVERTISED_1000baseKX_Full (1 << 17)
87 #define ADVERTISED_10000baseKX4_Full (1 << 18)
88 #define ADVERTISED_10000baseKR_Full (1 << 19)
89 #define ADVERTISED_10000baseR_FEC (1 << 20)
90 #define ADVERTISED_1000baseX_Half (1 << 21)
91 #define ADVERTISED_1000baseX_Full (1 << 22)
92
93 /* The following are all involved in forcing a particular link
94 * mode for the device for setting things. When getting the
95 * devices settings, these indicate the current mode and whether
96 * it was foced up into this mode or autonegotiated.
97 */
98
99 /* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */
100 #define SPEED_10 10
101 #define SPEED_100 100
102 #define SPEED_1000 1000
103 #define SPEED_2500 2500
104 #define SPEED_10000 10000
105
106 /* Duplex, half or full. */
107 #define DUPLEX_HALF 0x00
108 #define DUPLEX_FULL 0x01
109
110 /* Which connector port. */
111 #define PORT_TP 0x00
112 #define PORT_AUI 0x01
113 #define PORT_MII 0x02
114 #define PORT_FIBRE 0x03
115 #define PORT_BNC 0x04
116 #define PORT_DA 0x05
117 #define PORT_NONE 0xef
118 #define PORT_OTHER 0xff
119
120 /* Which transceiver to use. */
121 #define XCVR_INTERNAL 0x00
122 #define XCVR_EXTERNAL 0x01
123 #define XCVR_DUMMY1 0x02
124 #define XCVR_DUMMY2 0x03
125 #define XCVR_DUMMY3 0x04
126
127 /* Enable or disable autonegotiation. If this is set to enable,
128 * the forced link modes above are completely ignored.
129 */
130 #define AUTONEG_DISABLE 0x00
131 #define AUTONEG_ENABLE 0x01
132
133 #define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
134 SUPPORTED_10baseT_Full | \
135 SUPPORTED_100baseT_Half | \
136 SUPPORTED_100baseT_Full | \
137 SUPPORTED_Autoneg | \
138 SUPPORTED_TP | \
139 SUPPORTED_MII)
140
141 #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
142 SUPPORTED_1000baseT_Half | \
143 SUPPORTED_1000baseT_Full)
144
145 #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
146 SUPPORTED_10000baseT_Full)
147
148 #define PHY_ANEG_TIMEOUT 4000
149
150
151 typedef enum {
152 PHY_INTERFACE_MODE_MII,
153 PHY_INTERFACE_MODE_GMII,
154 PHY_INTERFACE_MODE_SGMII,
155 PHY_INTERFACE_MODE_QSGMII,
156 PHY_INTERFACE_MODE_TBI,
157 PHY_INTERFACE_MODE_RMII,
158 PHY_INTERFACE_MODE_RGMII,
159 PHY_INTERFACE_MODE_RGMII_ID,
160 PHY_INTERFACE_MODE_RGMII_RXID,
161 PHY_INTERFACE_MODE_RGMII_TXID,
162 PHY_INTERFACE_MODE_RTBI,
163 PHY_INTERFACE_MODE_XGMII,
164 PHY_INTERFACE_MODE_NONE /* Must be last */
165 } phy_interface_t;
166
167 static const char *phy_interface_strings[] = {
168 [PHY_INTERFACE_MODE_MII] = "mii",
169 [PHY_INTERFACE_MODE_GMII] = "gmii",
170 [PHY_INTERFACE_MODE_SGMII] = "sgmii",
171 [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
172 [PHY_INTERFACE_MODE_TBI] = "tbi",
173 [PHY_INTERFACE_MODE_RMII] = "rmii",
174 [PHY_INTERFACE_MODE_RGMII] = "rgmii",
175 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
176 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
177 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
178 [PHY_INTERFACE_MODE_RTBI] = "rtbi",
179 [PHY_INTERFACE_MODE_XGMII] = "xgmii",
180 [PHY_INTERFACE_MODE_NONE] = "",
181 };
182
phy_string_for_interface(phy_interface_t i)183 static inline const char *phy_string_for_interface(phy_interface_t i)
184 {
185 /* Default to unknown */
186 if (i > PHY_INTERFACE_MODE_NONE)
187 i = PHY_INTERFACE_MODE_NONE;
188
189 return phy_interface_strings[i];
190 }
191
192
193 struct phy_device;
194
195 #define MDIO_NAME_LEN 32
196
197 struct mii_dev {
198 struct list_head link;
199 char name[MDIO_NAME_LEN];
200 void *priv;
201 int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
202 int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
203 uint16_t val);
204 int (*reset)(struct mii_dev *bus);
205 struct phy_device *phymap[PHY_MAX_ADDR];
206 uint32_t phy_mask;
207 };
208
209 /* struct phy_driver: a structure which defines PHY behavior
210 *
211 * uid will contain a number which represents the PHY. During
212 * startup, the driver will poll the PHY to find out what its
213 * UID--as defined by registers 2 and 3--is. The 32-bit result
214 * gotten from the PHY will be masked to
215 * discard any bits which may change based on revision numbers
216 * unimportant to functionality
217 *
218 */
219 struct phy_driver {
220 char *name;
221 unsigned int uid;
222 unsigned int mask;
223 unsigned int mmds;
224
225 uint32_t features;
226
227 /* Called to do any driver startup necessities */
228 /* Will be called during phy_connect */
229 int (*probe)(struct phy_device *phydev);
230
231 /* Called to configure the PHY, and modify the controller
232 * based on the results. Should be called after phy_connect */
233 int (*config)(struct phy_device *phydev);
234
235 /* Called when starting up the controller */
236 int (*startup)(struct phy_device *phydev);
237
238 /* Called when bringing down the controller */
239 int (*shutdown)(struct phy_device *phydev);
240
241 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
242 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
243 uint16_t val);
244 struct list_head list;
245 };
246
247 struct phy_device {
248 /* Information about the PHY type */
249 /* And management functions */
250 struct mii_dev *bus;
251 struct phy_driver *drv;
252 void *priv;
253
254 struct eth_device *dev;
255
256 /* forced speed & duplex (no autoneg)
257 * partner speed & duplex & pause (autoneg)
258 */
259 int speed;
260 int duplex;
261
262 /* The most recently read link state */
263 int link;
264 int port;
265 phy_interface_t interface;
266
267 uint32_t advertising;
268 uint32_t supported;
269 uint32_t mmds;
270
271 int autoneg;
272 int addr;
273 int pause;
274 int asym_pause;
275 uint32_t phy_id;
276 uint32_t flags;
277 };
278
279 struct fixed_link {
280 int phy_id;
281 int duplex;
282 int link_speed;
283 int pause;
284 int asym_pause;
285 };
286
phy_read(struct phy_device * phydev,int devad,int regnum)287 static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
288 {
289 struct mii_dev *bus = phydev->bus;
290
291 return bus->read(bus, phydev->addr, devad, regnum);
292 }
293
phy_write(struct phy_device * phydev,int devad,int regnum,uint32_t val)294 static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
295 uint32_t val)
296 {
297 struct mii_dev *bus = phydev->bus;
298
299 return bus->write(bus, phydev->addr, devad, regnum, val);
300 }
301
302 #ifdef CONFIG_PHYLIB_10G
303 extern struct phy_driver gen10g_driver;
304
305 /* For now, XGMII is the only 10G interface */
is_10g_interface(phy_interface_t interface)306 static inline int is_10g_interface(phy_interface_t interface)
307 {
308 return interface == PHY_INTERFACE_MODE_XGMII;
309 }
310
311 #endif
312
313 int phy_init(void);
314 int phy_reset(struct phy_device *phydev);
315 struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
316 phy_interface_t interface);
317 void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
318 struct phy_device *phy_connect(struct mii_dev *bus, int addr,
319 struct eth_device *dev,
320 phy_interface_t interface);
321 int phy_startup(struct phy_device *phydev);
322 int phy_config(struct phy_device *phydev);
323 int phy_shutdown(struct phy_device *phydev);
324 int phy_register(struct phy_driver *drv);
325 int genphy_config_aneg(struct phy_device *phydev);
326 int genphy_restart_aneg(struct phy_device *phydev);
327 int genphy_update_link(struct phy_device *phydev);
328 int genphy_parse_link(struct phy_device *phydev);
329 int genphy_config(struct phy_device *phydev);
330 int genphy_startup(struct phy_device *phydev);
331 int genphy_shutdown(struct phy_device *phydev);
332 int gen10g_config(struct phy_device *phydev);
333 int gen10g_startup(struct phy_device *phydev);
334 int gen10g_shutdown(struct phy_device *phydev);
335 int gen10g_discover_mmds(struct phy_device *phydev);
336
337 int phy_atheros_init(void);
338 int phy_broadcom_init(void);
339 int phy_davicom_init(void);
340 int phy_et1011c_init(void);
341 int phy_lxt_init(void);
342 int phy_marvell_init(void);
343 int phy_micrel_init(void);
344 int phy_natsemi_init(void);
345 int phy_realtek_init(void);
346 int phy_smsc_init(void);
347 int phy_teranetics_init(void);
348 int phy_vitesse_init(void);
349
350 int board_phy_config(struct phy_device *phydev);
351
352 /* PHY UIDs for various PHYs that are referenced in external code */
353 #define PHY_UID_TN2020 0x00a19410
354
355 #endif /* __SUNXI_HAL_PHY_H__ */
356