1 #ifndef SUNXI_HAL_TWI_H 2 #define SUNXI_HAL_TWI_H 3 4 #include "hal_sem.h" 5 #include "hal_clk.h" 6 #include "sunxi_hal_common.h" 7 #include "hal_gpio.h" 8 #include "sunxi_hal_regulator.h" 9 #include <twi/platform_twi.h> 10 #include <twi/common_twi.h> 11 12 #ifdef __cplusplus 13 extern "C" { 14 #endif 15 16 //for debug 17 #define CONFIG_DRIVERS_TWI_DEBUG 18 #ifndef CONFIG_DRIVERS_TWI_DEBUG 19 #define TWI_INFO(fmt, arg...) hal_log_info(fmt, ##arg) 20 #else 21 #define TWI_INFO(fmt, arg...) do {}while(0) 22 #endif 23 24 #define TWI_ERR(fmt, arg...) hal_log_err(fmt, ##arg) 25 26 typedef enum 27 { 28 TWI_XFER_IDLE = 0x1, 29 TWI_XFER_START = 0x2, 30 TWI_XFER_RUNNING = 0x4, 31 } twi_xfer_status_t; 32 33 /** @brief This enum defines the HAL interface return value. */ 34 typedef enum 35 { 36 TWI_STATUS_ERROR = -4, /**< An error occurred and the transaction has failed. */ 37 //TWI_STATUS_ERROR_TIMEOUT = -4, /**< The TWI bus xfer timeout, an error occurred. */ 38 TWI_STATUS_ERROR_BUSY = -3, /**< The TWI bus is busy, an error occurred. */ 39 TWI_STATUS_INVALID_PORT_NUMBER = -2, /**< A wrong port number is given. */ 40 TWI_STATUS_INVALID_PARAMETER = -1, /**< A wrong parameter is given. */ 41 TWI_STATUS_OK = 0 /**< No error occurred during the function call. */ 42 } twi_status_t; 43 44 typedef enum 45 { 46 TWI_MASTER_0, /**< TWI master 0. */ 47 TWI_MASTER_1, /**< TWI master 1. */ 48 TWI_MASTER_2, /**< TWI master 0. */ 49 TWI_MASTER_3, /**< TWI master 1. */ 50 S_TWI_MASTER_0, /**< S_TWI master 0. */ 51 TWI_MASTER_MAX /**< max TWI master number, \<invalid\> */ 52 } twi_port_t; 53 54 /** @brief This enum defines the TWI transaction speed. */ 55 typedef enum 56 { 57 TWI_FREQUENCY_100K = 100000, /**< 100kbps. */ 58 TWI_FREQUENCY_200K = 200000, /**< 200kbps. */ 59 TWI_FREQUENCY_400K = 400000, /**< 400kbps. */ 60 } twi_frequency_t; 61 62 /** @brief This enum defines the TWI transaction speed. */ 63 typedef enum 64 { 65 ENGINE_XFER = 0, 66 TWI_DRV_XFER = 1, 67 } twi_mode_t; 68 69 typedef struct twi_msg 70 { 71 uint16_t addr; /* slave address */ 72 uint16_t flags; 73 #define TWI_M_RD 0x0001 /* read data, from slave to master 74 * TWI_M_RD is guaranteed to be 0x0001! 75 * */ 76 #define TWI_M_TEN 0x0010 /* this is a ten bit chip address */ 77 uint16_t len; /* msg length */ 78 uint8_t *buf; /* pointer to msg data */ 79 } twi_msg_t; 80 81 typedef struct sunxi_twi 82 { 83 uint8_t port; 84 uint8_t result; 85 uint8_t already_init; 86 uint8_t twi_drv_used; 87 uint8_t pkt_interval; 88 89 uint16_t slave_addr; 90 uint16_t flags; 91 92 uint32_t timeout; 93 uint32_t msgs_num; 94 uint32_t msgs_idx; 95 uint32_t msgs_ptr; 96 unsigned long base_addr; 97 uint32_t irqnum; 98 99 struct regulator_dev regulator; 100 hal_clk_t pclk; 101 hal_clk_t mclk; 102 twi_frequency_t freq; 103 104 uint32_t pinmux; 105 uint32_t pin[TWI_PIN_NUM]; 106 twi_xfer_status_t status; 107 hal_sem_t hal_sem; 108 twi_msg_t *msgs; 109 110 struct sunxi_dma_chan *dma_chan; 111 hal_sem_t dma_complete; 112 } hal_twi_t; 113 114 typedef enum 115 { 116 I2C_SLAVE = 0, 117 I2C_SLAVE_FORCE = 1, 118 I2C_TENBIT = 2, 119 I2C_RDWR = 3 120 } hal_twi_transfer_cmd_t; 121 122 //initialize twi port 123 twi_status_t hal_twi_init(twi_port_t port); 124 //uninitialize twi port 125 twi_status_t hal_twi_uninit(twi_port_t port); 126 //twi write 127 twi_status_t hal_twi_write(twi_port_t port, unsigned long pos, const void *buf, uint32_t size); 128 //twi read 129 twi_status_t hal_twi_read(twi_port_t port, unsigned long pos, void *buf, uint32_t size); 130 //twi control 131 twi_status_t hal_twi_control(twi_port_t port, hal_twi_transfer_cmd_t cmd, void *args); 132 133 #ifdef __cplusplus 134 } 135 #endif 136 137 #endif 138