1  /*
2  * Copyright (C) 2017-2024 Alibaba Group Holding Limited
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Licensed under the Apache License, Version 2.0 (the "License");
7  * you may not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  *     http://www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an "AS IS" BASIS,
14  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  */
18 
19 /******************************************************************************
20  * @file     sys_clk.h
21  * @brief    header file for setting system frequency.
22  * @version  V1.0
23  * @date     9. April 2020
24  ******************************************************************************/
25 #ifndef _SYS_CLK_H_
26 #define _SYS_CLK_H_
27 
28 #include <stdint.h>
29 #include <soc.h>
30 #include <drv/clk.h>
31 #include <drv/porting.h>
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 #define PMU_REG_BASE            (wj_pmu_reg_t *)WJ_PMU_BASE
38 
39 typedef enum {
40     IHS_CLK       = 0U,        /* internal high speed clock */
41     EHS_CLK,                   /* external high speed clock */
42     ILS_CLK,                   /* internal low  speed clock */
43     ELS_CLK,                   /* external low  speed clock */
44     PLL_CLK                    /* PLL clock */
45 } clk_src_t;
46 
47 typedef enum {
48     CPU_24MHZ     = 24000000U
49 } sys_freq_t;
50 
51 
52 /* pllclkout : ( pllclkin / 2)*( FN + Frac/4096 ) */
53 typedef struct {
54 
55     uint32_t pll_is_used;          /* pll is used */
56 
57     uint32_t pll_source;           /* select pll input source clock */
58 
59     uint32_t pll_src_clk_divider;  /* ratio between pll_srcclk clock and pll_clkin clock */
60 
61     uint32_t fn;                   /* integer value of frequency division */
62 
63     uint32_t frac;                 /* decimal value of frequency division */
64 
65 } pll_config_t;
66 
67 
68 typedef struct {
69     uint32_t system_clk;            /* system clock */
70 
71     pll_config_t pll_config;        /* pll config struct */
72 
73     uint32_t sys_clk_source;        /* select sysclk source clock */
74 
75     uint32_t rtc_clk_source;        /* select rtcclk source clock */
76 
77     uint32_t mclk_divider;          /* ratio between fs_mclk clock and mclk clock */
78 
79     uint32_t apb0_clk_divider;      /* ratio between mclk clock and apb0 clock */
80 
81     uint32_t apb1_clk_divider;      /* ratio between mclk clock and apb1 clock */
82 
83 } system_clk_config_t;
84 
85 typedef enum {
86     CLK_DIV1 = 0U,
87 } apb_div_t;
88 
89 typedef enum {
90     PLL_FN_18 = 0U,
91 } pll_fn_t;
92 
93 typedef enum {
94     UART0_CLK,
95 } clk_module_t;
96 
97 
98 /**
99   \brief       Set the system clock according to the parameter
100   \param[in]   config    system clock config.
101   \return      error code
102 */
103 csi_error_t soc_sysclk_config(system_clk_config_t *config);
104 
105 /**
106   \brief       Set iic reset
107   \param[in]   idx    iic idx.
108   \return      Null
109 */
110 void soc_reset_iic(uint32_t idx);
111 
112 #ifdef __cplusplus
113 }
114 #endif
115 
116 #endif /* _SYS_CLK_H_ */
117 
118