1 /******************************************************************************* 2 * (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved. 3 * 4 * Smartfusion2 system configuration. This file is automatically generated 5 * by the Libero tools. It contains the Smartfusion2 system configuration that 6 * was selected during the hardware configuration flow. 7 * 8 */ 9 10 #include "../../CMSIS/m2sxxx.h" 11 #include "../../CMSIS/sys_init_cfg_types.h" 12 #include "sys_config.h" 13 14 /*============================================================================== 15 * !!! WARNING !!! 16 *============================================================================== 17 * The project including this file must be linked so that the content of this 18 * file is located in internal eNVM at run time. The content of this file is 19 * used to configure the system prior to RAM content initialization. This means 20 * that the content of the data structures below will be used before the copy 21 * from LMA to VMA takes place. The LMA and VMA locations of the content of this 22 * file must be identical for the system to be seamlessly configured as part of 23 * the CMSIS boot process. 24 */ 25 26 /*============================================================================== 27 * Clock configuration 28 */ 29 /* No configuration data structure required. */ 30 31 /*============================================================================== 32 * Memory remapping configuration 33 */ 34 /* TBD. */ 35 36 /*============================================================================== 37 * MDDR configuration 38 */ 39 #if MSS_SYS_MDDR_CONFIG_BY_CORTEX 40 41 #include "sys_config_mddr_define.h" 42 43 MDDR_TypeDef * const g_m2s_mddr_addr = (MDDR_TypeDef *)0x40020800; 44 45 const ddr_subsys_cfg_t g_m2s_mddr_subsys_config = 46 { 47 /*--------------------------------------------------------------------- 48 * DDR Controller registers. 49 * All registers are 16-bit wide unless mentioned beside the definition. 50 */ 51 { 52 MDDR_DDRC_DYN_SOFT_RESET_CR, 53 MDDR_DDRC_RESERVED0, 54 MDDR_DDRC_DYN_REFRESH_1_CR, 55 MDDR_DDRC_DYN_REFRESH_2_CR, 56 MDDR_DDRC_DYN_POWERDOWN_CR, 57 MDDR_DDRC_DYN_DEBUG_CR, 58 MDDR_DDRC_MODE_CR, 59 MDDR_DDRC_ADDR_MAP_BANK_CR, 60 MDDR_DDRC_ECC_DATA_MASK_CR, 61 MDDR_DDRC_ADDR_MAP_COL_1_CR, 62 MDDR_DDRC_ADDR_MAP_COL_2_CR, 63 MDDR_DDRC_ADDR_MAP_ROW_1_CR, 64 MDDR_DDRC_ADDR_MAP_ROW_2_CR, 65 MDDR_DDRC_INIT_1_CR, 66 MDDR_DDRC_CKE_RSTN_CYCLES_1_CR, 67 MDDR_DDRC_CKE_RSTN_CYCLES_2_CR, 68 MDDR_DDRC_INIT_MR_CR, 69 MDDR_DDRC_INIT_EMR_CR, 70 MDDR_DDRC_INIT_EMR2_CR, 71 MDDR_DDRC_INIT_EMR3_CR, 72 MDDR_DDRC_DRAM_BANK_TIMING_PARAM_CR, 73 MDDR_DDRC_DRAM_RD_WR_LATENCY_CR, 74 MDDR_DDRC_DRAM_RD_WR_PRE_CR, 75 MDDR_DDRC_DRAM_MR_TIMING_PARAM_CR, 76 MDDR_DDRC_DRAM_RAS_TIMING_CR, 77 MDDR_DDRC_DRAM_RD_WR_TRNARND_TIME_CR, 78 MDDR_DDRC_DRAM_T_PD_CR, 79 MDDR_DDRC_DRAM_BANK_ACT_TIMING_CR, 80 MDDR_DDRC_ODT_PARAM_1_CR, 81 MDDR_DDRC_ODT_PARAM_2_CR, 82 MDDR_DDRC_ADDR_MAP_COL_3_CR, 83 MDDR_DDRC_MODE_REG_RD_WR_CR, 84 MDDR_DDRC_MODE_REG_DATA_CR, 85 MDDR_DDRC_PWR_SAVE_1_CR, 86 MDDR_DDRC_PWR_SAVE_2_CR, 87 MDDR_DDRC_ZQ_LONG_TIME_CR, 88 MDDR_DDRC_ZQ_SHORT_TIME_CR, 89 MDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR, 90 MDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR, 91 MDDR_DDRC_PERF_PARAM_1_CR, 92 MDDR_DDRC_HPR_QUEUE_PARAM_1_CR, 93 MDDR_DDRC_HPR_QUEUE_PARAM_2_CR, 94 MDDR_DDRC_LPR_QUEUE_PARAM_1_CR, 95 MDDR_DDRC_LPR_QUEUE_PARAM_2_CR, 96 MDDR_DDRC_WR_QUEUE_PARAM_CR, 97 MDDR_DDRC_PERF_PARAM_2_CR, 98 MDDR_DDRC_PERF_PARAM_3_CR, 99 MDDR_DDRC_DFI_RDDATA_EN_CR, 100 MDDR_DDRC_DFI_MIN_CTRLUPD_TIMING_CR, 101 MDDR_DDRC_DFI_MAX_CTRLUPD_TIMING_CR, 102 MDDR_DDRC_DFI_WR_LVL_CONTROL_1_CR, 103 MDDR_DDRC_DFI_WR_LVL_CONTROL_2_CR, 104 MDDR_DDRC_DFI_RD_LVL_CONTROL_1_CR, 105 MDDR_DDRC_DFI_RD_LVL_CONTROL_2_CR, 106 MDDR_DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR, 107 MDDR_DDRC_DYN_SOFT_RESET_ALIAS_CR, 108 MDDR_DDRC_AXI_FABRIC_PRI_ID_CR, 109 }, 110 111 /*--------------------------------------------------------------------- 112 * DDR PHY configuration registers 113 */ 114 { 115 MDDR_PHY_LOOPBACK_TEST_CR, 116 MDDR_PHY_BOARD_LOOPBACK_CR, 117 MDDR_PHY_CTRL_SLAVE_RATIO_CR, 118 MDDR_PHY_CTRL_SLAVE_FORCE_CR, 119 MDDR_PHY_CTRL_SLAVE_DELAY_CR, 120 MDDR_PHY_DATA_SLICE_IN_USE_CR, 121 MDDR_PHY_LVL_NUM_OF_DQ0_CR, 122 MDDR_PHY_DQ_OFFSET_1_CR, 123 MDDR_PHY_DQ_OFFSET_2_CR, 124 MDDR_PHY_DQ_OFFSET_3_CR, 125 MDDR_PHY_DIS_CALIB_RST_CR, 126 MDDR_PHY_DLL_LOCK_DIFF_CR, 127 MDDR_PHY_FIFO_WE_IN_DELAY_1_CR, 128 MDDR_PHY_FIFO_WE_IN_DELAY_2_CR, 129 MDDR_PHY_FIFO_WE_IN_DELAY_3_CR, 130 MDDR_PHY_FIFO_WE_IN_FORCE_CR, 131 MDDR_PHY_FIFO_WE_SLAVE_RATIO_1_CR, 132 MDDR_PHY_FIFO_WE_SLAVE_RATIO_2_CR, 133 MDDR_PHY_FIFO_WE_SLAVE_RATIO_3_CR, 134 MDDR_PHY_FIFO_WE_SLAVE_RATIO_4_CR, 135 MDDR_PHY_GATELVL_INIT_MODE_CR, 136 MDDR_PHY_GATELVL_INIT_RATIO_1_CR, 137 MDDR_PHY_GATELVL_INIT_RATIO_2_CR, 138 MDDR_PHY_GATELVL_INIT_RATIO_3_CR, 139 MDDR_PHY_GATELVL_INIT_RATIO_4_CR, 140 MDDR_PHY_LOCAL_ODT_CR, 141 MDDR_PHY_INVERT_CLKOUT_CR, 142 MDDR_PHY_RD_DQS_SLAVE_DELAY_1_CR, 143 MDDR_PHY_RD_DQS_SLAVE_DELAY_2_CR, 144 MDDR_PHY_RD_DQS_SLAVE_DELAY_3_CR, 145 MDDR_PHY_RD_DQS_SLAVE_FORCE_CR, 146 MDDR_PHY_RD_DQS_SLAVE_RATIO_1_CR, 147 MDDR_PHY_RD_DQS_SLAVE_RATIO_2_CR, 148 MDDR_PHY_RD_DQS_SLAVE_RATIO_3_CR, 149 MDDR_PHY_RD_DQS_SLAVE_RATIO_4_CR, 150 MDDR_PHY_WR_DQS_SLAVE_DELAY_1_CR, 151 MDDR_PHY_WR_DQS_SLAVE_DELAY_2_CR, 152 MDDR_PHY_WR_DQS_SLAVE_DELAY_3_CR, 153 MDDR_PHY_WR_DQS_SLAVE_FORCE_CR, 154 MDDR_PHY_WR_DQS_SLAVE_RATIO_1_CR, 155 MDDR_PHY_WR_DQS_SLAVE_RATIO_2_CR, 156 MDDR_PHY_WR_DQS_SLAVE_RATIO_3_CR, 157 MDDR_PHY_WR_DQS_SLAVE_RATIO_4_CR, 158 MDDR_PHY_WR_DATA_SLAVE_DELAY_1_CR, 159 MDDR_PHY_WR_DATA_SLAVE_DELAY_2_CR, 160 MDDR_PHY_WR_DATA_SLAVE_DELAY_3_CR, 161 MDDR_PHY_WR_DATA_SLAVE_FORCE_CR, 162 MDDR_PHY_WR_DATA_SLAVE_RATIO_1_CR, 163 MDDR_PHY_WR_DATA_SLAVE_RATIO_2_CR, 164 MDDR_PHY_WR_DATA_SLAVE_RATIO_3_CR, 165 MDDR_PHY_WR_DATA_SLAVE_RATIO_4_CR, 166 MDDR_PHY_WRLVL_INIT_MODE_CR, 167 MDDR_PHY_WRLVL_INIT_RATIO_1_CR, 168 MDDR_PHY_WRLVL_INIT_RATIO_2_CR, 169 MDDR_PHY_WRLVL_INIT_RATIO_3_CR, 170 MDDR_PHY_WRLVL_INIT_RATIO_4_CR, 171 MDDR_PHY_WR_RD_RL_CR, 172 MDDR_PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR, 173 MDDR_PHY_RDC_WE_TO_RE_DELAY_CR, 174 MDDR_PHY_USE_FIXED_RE_CR, 175 MDDR_PHY_USE_RANK0_DELAYS_CR, 176 MDDR_PHY_USE_LVL_TRNG_LEVEL_CR, 177 MDDR_PHY_DYN_CONFIG_CR, 178 MDDR_PHY_RD_WR_GATE_LVL_CR, 179 MDDR_PHY_DYN_RESET_CR 180 }, 181 182 /*--------------------------------------------------------------------- 183 * FIC-64 registers 184 * These registers are 16-bit wide and 32-bit aligned. 185 */ 186 { 187 MDDR_DDR_FIC_NB_ADDR_CR, 188 MDDR_DDR_FIC_NBRWB_SIZE_CR, 189 MDDR_DDR_FIC_WB_TIMEOUT_CR, 190 MDDR_DDR_FIC_HPD_SW_RW_EN_CR, 191 MDDR_DDR_FIC_HPD_SW_RW_INVAL_CR, 192 MDDR_DDR_FIC_SW_WR_ERCLR_CR, 193 MDDR_DDR_FIC_ERR_INT_ENABLE_CR, 194 MDDR_DDR_FIC_NUM_AHB_MASTERS_CR, 195 MDDR_DDR_FIC_LOCK_TIMEOUTVAL_1_CR, 196 MDDR_DDR_FIC_LOCK_TIMEOUTVAL_2_CR, 197 MDDR_DDR_FIC_LOCK_TIMEOUT_EN_CR 198 } 199 }; 200 201 #endif 202 203 /*============================================================================== 204 * FDDR configuration 205 */ 206 #if MSS_SYS_FDDR_CONFIG_BY_CORTEX 207 208 #include "sys_config_fddr_define.h" 209 210 FDDR_TypeDef * const g_m2s_fddr_addr = (FDDR_TypeDef *)0x40021000; 211 212 const fddr_sysreg_t g_m2s_fddr_sysreg_subsys_config = 213 { 214 0x0001u, /* PLL_CONFIG_LOW_1 */ 215 0x0002u, /* PLL_CONFIG_LOW_2 */ 216 0x0003u, /* PLL_CONFIG_HIGH */ 217 0x0004u, /* FACC_CLK_EN */ 218 0x0005u, /* FACC_MUX_CONFIG */ 219 0x0006u, /* FACC_DIVISOR_RATIO */ 220 0x0007u, /* PLL_DELAY_LINE_SEL */ 221 0x0008u, /* SOFT_RESET */ 222 0x0009u, /* IO_CALIB */ 223 0x000Au, /* INTERRUPT_ENABLE */ 224 0x000Bu, /* AXI_AHB_MODE_SEL */ 225 0x000Cu /* PHY_SELF_REF_EN */ 226 }; 227 228 const ddr_subsys_cfg_t g_m2s_fddr_subsys_config = 229 { 230 /*--------------------------------------------------------------------- 231 * DDR Controller registers. 232 * All registers are 16-bit wide unless mentioned beside the definition. 233 */ 234 { 235 FDDR_DDRC_DYN_SOFT_RESET_CR, 236 FDDR_DDRC_RESERVED0, 237 FDDR_DDRC_DYN_REFRESH_1_CR, 238 FDDR_DDRC_DYN_REFRESH_2_CR, 239 FDDR_DDRC_DYN_POWERDOWN_CR, 240 FDDR_DDRC_DYN_DEBUG_CR, 241 FDDR_DDRC_MODE_CR, 242 FDDR_DDRC_ADDR_MAP_BANK_CR, 243 FDDR_DDRC_ECC_DATA_MASK_CR, 244 FDDR_DDRC_ADDR_MAP_COL_1_CR, 245 FDDR_DDRC_ADDR_MAP_COL_2_CR, 246 FDDR_DDRC_ADDR_MAP_ROW_1_CR, 247 FDDR_DDRC_ADDR_MAP_ROW_2_CR, 248 FDDR_DDRC_INIT_1_CR, 249 FDDR_DDRC_CKE_RSTN_CYCLES_1_CR, 250 FDDR_DDRC_CKE_RSTN_CYCLES_2_CR, 251 FDDR_DDRC_INIT_MR_CR, 252 FDDR_DDRC_INIT_EMR_CR, 253 FDDR_DDRC_INIT_EMR2_CR, 254 FDDR_DDRC_INIT_EMR3_CR, 255 FDDR_DDRC_DRAM_BANK_TIMING_PARAM_CR, 256 FDDR_DDRC_DRAM_RD_WR_LATENCY_CR, 257 FDDR_DDRC_DRAM_RD_WR_PRE_CR, 258 FDDR_DDRC_DRAM_MR_TIMING_PARAM_CR, 259 FDDR_DDRC_DRAM_RAS_TIMING_CR, 260 FDDR_DDRC_DRAM_RD_WR_TRNARND_TIME_CR, 261 FDDR_DDRC_DRAM_T_PD_CR, 262 FDDR_DDRC_DRAM_BANK_ACT_TIMING_CR, 263 FDDR_DDRC_ODT_PARAM_1_CR, 264 FDDR_DDRC_ODT_PARAM_2_CR, 265 FDDR_DDRC_ADDR_MAP_COL_3_CR, 266 FDDR_DDRC_MODE_REG_RD_WR_CR, 267 FDDR_DDRC_MODE_REG_DATA_CR, 268 FDDR_DDRC_PWR_SAVE_1_CR, 269 FDDR_DDRC_PWR_SAVE_2_CR, 270 FDDR_DDRC_ZQ_LONG_TIME_CR, 271 FDDR_DDRC_ZQ_SHORT_TIME_CR, 272 FDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR, 273 FDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR, 274 FDDR_DDRC_PERF_PARAM_1_CR, 275 FDDR_DDRC_HPR_QUEUE_PARAM_1_CR, 276 FDDR_DDRC_HPR_QUEUE_PARAM_2_CR, 277 FDDR_DDRC_LPR_QUEUE_PARAM_1_CR, 278 FDDR_DDRC_LPR_QUEUE_PARAM_2_CR, 279 FDDR_DDRC_WR_QUEUE_PARAM_CR, 280 FDDR_DDRC_PERF_PARAM_2_CR, 281 FDDR_DDRC_PERF_PARAM_3_CR, 282 FDDR_DDRC_DFI_RDDATA_EN_CR, 283 FDDR_DDRC_DFI_MIN_CTRLUPD_TIMING_CR, 284 FDDR_DDRC_DFI_MAX_CTRLUPD_TIMING_CR, 285 FDDR_DDRC_DFI_WR_LVL_CONTROL_1_CR, 286 FDDR_DDRC_DFI_WR_LVL_CONTROL_2_CR, 287 FDDR_DDRC_DFI_RD_LVL_CONTROL_1_CR, 288 FDDR_DDRC_DFI_RD_LVL_CONTROL_2_CR, 289 FDDR_DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR, 290 FDDR_DDRC_DYN_SOFT_RESET_ALIAS_CR, 291 FDDR_DDRC_AXI_FABRIC_PRI_ID_CR 292 }, 293 294 /*--------------------------------------------------------------------- 295 * DDR PHY configuration registers 296 */ 297 { 298 FDDR_PHY_LOOPBACK_TEST_CR, 299 FDDR_PHY_BOARD_LOOPBACK_CR, 300 FDDR_PHY_CTRL_SLAVE_RATIO_CR, 301 FDDR_PHY_CTRL_SLAVE_FORCE_CR, 302 FDDR_PHY_CTRL_SLAVE_DELAY_CR, 303 FDDR_PHY_DATA_SLICE_IN_USE_CR, 304 FDDR_PHY_LVL_NUM_OF_DQ0_CR, 305 FDDR_PHY_DQ_OFFSET_1_CR, 306 FDDR_PHY_DQ_OFFSET_2_CR, 307 FDDR_PHY_DQ_OFFSET_3_CR, 308 FDDR_PHY_DIS_CALIB_RST_CR, 309 FDDR_PHY_DLL_LOCK_DIFF_CR, 310 FDDR_PHY_FIFO_WE_IN_DELAY_1_CR, 311 FDDR_PHY_FIFO_WE_IN_DELAY_2_CR, 312 FDDR_PHY_FIFO_WE_IN_DELAY_3_CR, 313 FDDR_PHY_FIFO_WE_IN_FORCE_CR, 314 FDDR_PHY_FIFO_WE_SLAVE_RATIO_1_CR, 315 FDDR_PHY_FIFO_WE_SLAVE_RATIO_2_CR, 316 FDDR_PHY_FIFO_WE_SLAVE_RATIO_3_CR, 317 FDDR_PHY_FIFO_WE_SLAVE_RATIO_4_CR, 318 FDDR_PHY_GATELVL_INIT_MODE_CR, 319 FDDR_PHY_GATELVL_INIT_RATIO_1_CR, 320 FDDR_PHY_GATELVL_INIT_RATIO_2_CR, 321 FDDR_PHY_GATELVL_INIT_RATIO_3_CR, 322 FDDR_PHY_GATELVL_INIT_RATIO_4_CR, 323 FDDR_PHY_LOCAL_ODT_CR, 324 FDDR_PHY_INVERT_CLKOUT_CR, 325 FDDR_PHY_RD_DQS_SLAVE_DELAY_1_CR, 326 FDDR_PHY_RD_DQS_SLAVE_DELAY_2_CR, 327 FDDR_PHY_RD_DQS_SLAVE_DELAY_3_CR, 328 FDDR_PHY_RD_DQS_SLAVE_FORCE_CR, 329 FDDR_PHY_RD_DQS_SLAVE_RATIO_1_CR, 330 FDDR_PHY_RD_DQS_SLAVE_RATIO_2_CR, 331 FDDR_PHY_RD_DQS_SLAVE_RATIO_3_CR, 332 FDDR_PHY_RD_DQS_SLAVE_RATIO_4_CR, 333 FDDR_PHY_WR_DQS_SLAVE_DELAY_1_CR, 334 FDDR_PHY_WR_DQS_SLAVE_DELAY_2_CR, 335 FDDR_PHY_WR_DQS_SLAVE_DELAY_3_CR, 336 FDDR_PHY_WR_DQS_SLAVE_FORCE_CR, 337 FDDR_PHY_WR_DQS_SLAVE_RATIO_1_CR, 338 FDDR_PHY_WR_DQS_SLAVE_RATIO_2_CR, 339 FDDR_PHY_WR_DQS_SLAVE_RATIO_3_CR, 340 FDDR_PHY_WR_DQS_SLAVE_RATIO_4_CR, 341 FDDR_PHY_WR_DATA_SLAVE_DELAY_1_CR, 342 FDDR_PHY_WR_DATA_SLAVE_DELAY_2_CR, 343 FDDR_PHY_WR_DATA_SLAVE_DELAY_3_CR, 344 FDDR_PHY_WR_DATA_SLAVE_FORCE_CR, 345 FDDR_PHY_WR_DATA_SLAVE_RATIO_1_CR, 346 FDDR_PHY_WR_DATA_SLAVE_RATIO_2_CR, 347 FDDR_PHY_WR_DATA_SLAVE_RATIO_3_CR, 348 FDDR_PHY_WR_DATA_SLAVE_RATIO_4_CR, 349 FDDR_PHY_WRLVL_INIT_MODE_CR, 350 FDDR_PHY_WRLVL_INIT_RATIO_1_CR, 351 FDDR_PHY_WRLVL_INIT_RATIO_2_CR, 352 FDDR_PHY_WRLVL_INIT_RATIO_3_CR, 353 FDDR_PHY_WRLVL_INIT_RATIO_4_CR, 354 FDDR_PHY_WR_RD_RL_CR, 355 FDDR_PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR, 356 FDDR_PHY_RDC_WE_TO_RE_DELAY_CR, 357 FDDR_PHY_USE_FIXED_RE_CR, 358 FDDR_PHY_USE_RANK0_DELAYS_CR, 359 FDDR_PHY_USE_LVL_TRNG_LEVEL_CR, 360 FDDR_PHY_DYN_CONFIG_CR, 361 FDDR_PHY_RD_WR_GATE_LVL_CR, 362 FDDR_PHY_DYN_RESET_CR, 363 }, 364 365 /*--------------------------------------------------------------------- 366 * FIC-64 registers 367 * These registers are 16-bit wide and 32-bit aligned. 368 */ 369 { 370 FDDR_DDR_FIC_NB_ADDR_CR, 371 FDDR_DDR_FIC_NBRWB_SIZE_CR, 372 FDDR_DDR_FIC_WB_TIMEOUT_CR, 373 FDDR_DDR_FIC_HPD_SW_RW_EN_CR, 374 FDDR_DDR_FIC_HPD_SW_RW_INVAL_CR, 375 FDDR_DDR_FIC_SW_WR_ERCLR_CR, 376 FDDR_DDR_FIC_ERR_INT_ENABLE_CR, 377 FDDR_DDR_FIC_NUM_AHB_MASTERS_CR, 378 FDDR_DDR_FIC_LOCK_TIMEOUTVAL_1_CR, 379 FDDR_DDR_FIC_LOCK_TIMEOUTVAL_2_CR, 380 FDDR_DDR_FIC_LOCK_TIMEOUT_EN_CR 381 } 382 }; 383 384 #endif 385 386