1 /** @file sys_core.h 2 * @brief System Core Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Core Interface Functions 8 * . 9 * which are relevant for the System driver. 10 */ 11 12 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 13 14 #ifndef __SYS_CORE_H__ 15 #define __SYS_CORE_H__ 16 17 #include "sys_common.h" 18 19 /* USER CODE BEGIN (0) */ 20 /* USER CODE END */ 21 22 23 /* System Core Interface Functions */ 24 25 /** @fn void _coreInitRegisters_(void) 26 * @brief Initialize Core register 27 */ 28 void _coreInitRegisters_(void); 29 30 /** @fn void _coreInitStackPointer_(void) 31 * @brief Initialize Core stack pointer 32 */ 33 void _coreInitStackPointer_(void); 34 35 /** @fn void _getCPSRValue_(void) 36 * @brief Get CPSR Value 37 */ 38 uint32 _getCPSRValue_(void); 39 40 /** @fn void _gotoCPUIdle_(void) 41 * @brief Take CPU to Idle state 42 */ 43 void _gotoCPUIdle_(void); 44 45 /** @fn void _coreEnableIrqVicOffset_(void) 46 * @brief Enable Irq offset propagation via Vic controller 47 */ 48 void _coreEnableIrqVicOffset_(void); 49 50 /** @fn void _coreEnableVfp_(void) 51 * @brief Enable vector floating point unit 52 */ 53 void _coreEnableVfp_(void); 54 55 /** @fn void _coreEnableEventBusExport_(void) 56 * @brief Enable event bus export for external monitoring modules 57 * @note It is required to enable event bus export to process ecc issues. 58 * 59 * This function enables event bus exports to external monitoring modules 60 * like tightly coupled RAM wrapper, Flash wrapper and error signaling module. 61 */ 62 void _coreEnableEventBusExport_(void); 63 64 /** @fn void _coreDisableEventBusExport_(void) 65 * @brief Disable event bus export for external monitoring modules 66 * 67 * This function disables event bus exports to external monitoring modules 68 * like tightly coupled RAM wrapper, Flash wrapper and error signaling module. 69 */ 70 void _coreDisableEventBusExport_(void); 71 72 /** @fn void _coreEnableRamEcc_(void) 73 * @brief Enable external ecc error for RAM odd and even bank 74 * @note It is required to enable event bus export to process ecc issues. 75 */ 76 void _coreEnableRamEcc_(void); 77 78 /** @fn void _coreDisableRamEcc_(void) 79 * @brief Disable external ecc error for RAM odd and even bank 80 */ 81 void _coreDisableRamEcc_(void); 82 83 /** @fn void _coreEnableFlashEcc_(void) 84 * @brief Enable external ecc error for the Flash 85 * @note It is required to enable event bus export to process ecc issues. 86 */ 87 void _coreEnableFlashEcc_(void); 88 89 /** @fn void _coreDisableFlashEcc_(void) 90 * @brief Disable external ecc error for the Flash 91 */ 92 void _coreDisableFlashEcc_(void); 93 94 /** @fn uint32 _coreGetDataFault_(void) 95 * @brief Get core data fault status register 96 * @return The function will return the data fault status register value: 97 * - bit [10,3..0]: 98 * - 0b00001: Alignment -> address is valid 99 * - 0b00000: Background -> address is valid 100 * - 0b01101: Permission -> address is valid 101 * - 0b01000: Precise External Abort -> address is valid 102 * - 0b10110: Imprecise External Abort -> address is unpredictable 103 * - 0b11001: Precise ECC Error -> address is valid 104 * - 0b11000: Imprecise ECC Error -> address is unpredictable 105 * - 0b00010: Debug -> address is unchanged 106 * - bit [11]: 107 * - 0: Read 108 * - 1: Write 109 * - bit [12]: 110 * - 0: AXI Decode Error (DECERR) 111 * - 1: AXI Slave Error (SLVERR) 112 */ 113 uint32 _coreGetDataFault_(void); 114 115 /** @fn void _coreClearDataFault_(void) 116 * @brief Clear core data fault status register 117 */ 118 void _coreClearDataFault_(void); 119 120 /** @fn uint32 _coreGetInstructionFault_(void) 121 * @brief Get core instruction fault status register 122 * @return The function will return the instruction fault status register value: 123 * - bit [10,3..0]: 124 * - 0b00001: Alignment -> address is valid 125 * - 0b00000: Background -> address is valid 126 * - 0b01101: Permission -> address is valid 127 * - 0b01000: Precise External Abort -> address is valid 128 * - 0b10110: Imprecise External Abort -> address is unpredictable 129 * - 0b11001: Precise ECC Error -> address is valid 130 * - 0b11000: Imprecise ECC Error -> address is unpredictable 131 * - 0b00010: Debug -> address is unchanged 132 * - bit [12]: 133 * - 0: AXI Decode Error (DECERR) 134 * - 1: AXI Slave Error (SLVERR) 135 */ 136 uint32 _coreGetInstructionFault_(void); 137 138 /** @fn void _coreClearInstructionFault_(void) 139 * @brief Clear core instruction fault status register 140 */ 141 void _coreClearInstructionFault_(void); 142 143 /** @fn uint32 _coreGetDataFaultAddress_(void) 144 * @brief Get core data fault address register 145 * @return The function will return the data fault address: 146 */ 147 uint32 _coreGetDataFaultAddress_(void); 148 149 /** @fn void _coreClearDataFaultAddress_(void) 150 * @brief Clear core data fault address register 151 */ 152 void _coreClearDataFaultAddress_(void); 153 154 /** @fn uint32 _coreGetInstructionFaultAddress_(void) 155 * @brief Get core instruction fault address register 156 * @return The function will return the instruction fault address: 157 */ 158 uint32 _coreGetInstructionFaultAddress_(void); 159 160 /** @fn void _coreClearInstructionFaultAddress_(void) 161 * @brief Clear core instruction fault address register 162 */ 163 void _coreClearInstructionFaultAddress_(void); 164 165 /** @fn uint32 _coreGetAuxiliaryDataFault_(void) 166 * @brief Get core auxiliary data fault status register 167 * @return The function will return the auxiliary data fault status register value: 168 * - bit [13..5]: 169 * - Index value for access giving error 170 * - bit [21]: 171 * - 0: Unrecoverable error 172 * - 1: Recoverable error 173 * - bit [23..22]: 174 * - 0: Side cache 175 * - 1: Side ATCM (Flash) 176 * - 2: Side BTCM (RAM) 177 * - 3: Reserved 178 * - bit [27..24]: 179 * - Cache way or way in which error occurred 180 */ 181 uint32 _coreGetAuxiliaryDataFault_(void); 182 183 /** @fn void _coreClearAuxiliaryDataFault_(void) 184 * @brief Clear core auxiliary data fault status register 185 */ 186 void _coreClearAuxiliaryDataFault_(void); 187 188 /** @fn uint32 _coreGetAuxiliaryInstructionFault_(void) 189 * @brief Get core auxiliary instruction fault status register 190 * @return The function will return the auxiliary instruction fault status register value: 191 * - bit [13..5]: 192 * - Index value for access giving error 193 * - bit [21]: 194 * - 0: Unrecoverable error 195 * - 1: Recoverable error 196 * - bit [23..22]: 197 * - 0: Side cache 198 * - 1: Side ATCM (Flash) 199 * - 2: Side BTCM (RAM) 200 * - 3: Reserved 201 * - bit [27..24]: 202 * - Cache way or way in which error occurred 203 */ 204 uint32 _coreGetAuxiliaryInstructionFault_(void); 205 206 /** @fn void _coreClearAuxiliaryInstructionFault_(void) 207 * @brief Clear core auxiliary instruction fault status register 208 */ 209 void _coreClearAuxiliaryInstructionFault_(void); 210 211 /** @fn void _disable_interrupt_(void) 212 * @brief Disable IRQ and FIQ Interrupt mode in CPSR register 213 * 214 * This function disables IRQ and FIQ Interrupt mode in CPSR register. 215 */ 216 void _disable_interrupt_(void); 217 218 /** @fn void _disable_IRQ_interrupt_(void) 219 * @brief Disable IRQ Interrupt mode in CPSR register 220 * 221 * This function disables IRQ Interrupt mode in CPSR register. 222 */ 223 void _disable_IRQ_interrupt_(void); 224 225 /** @fn void _disable_FIQ_interrupt_(void) 226 * @brief Disable FIQ Interrupt mode in CPSR register 227 * 228 * This function disables IRQ Interrupt mode in CPSR register. 229 */ 230 void _disable_FIQ_interrupt_(void); 231 232 /** @fn void _enable_interrupt_(void) 233 * @brief Enable IRQ and FIQ Interrupt mode in CPSR register 234 * 235 * This function Enables IRQ and FIQ Interrupt mode in CPSR register. 236 * User must call this function to enable Interrupts in non-OS environments. 237 */ 238 void _enable_interrupt_(void); 239 240 /** @fn void _esmCcmErrorsClear_(void) 241 * @brief Clears ESM Error caused due to CCM Errata in RevA Silicon 242 * 243 * This function Clears ESM Error caused due to CCM Errata 244 * in RevA Silicon immediately after powerup. 245 */ 246 void _esmCcmErrorsClear_(void); 247 248 /** @fn void _errata_CORTEXR4_66_(void) 249 * @brief Work Around for Errata CORTEX-R4#66 250 * 251 * This function Disable out-of-order completion for divide 252 * instructions in Auxiliary Control register. 253 */ 254 void _errata_CORTEXR4_66_(void); 255 256 /** @fn void _errata_CORTEXR4_57_(void) 257 * @brief Work Around for Errata CORTEX-R4#57 258 * 259 * Disable out-of-order single-precision floating point 260 * multiply-accumulate instruction completion. 261 */ 262 void _errata_CORTEXR4_57_(void); 263 264 #endif 265