1 /** @file sys_selftest.h 2 * @brief System Memory Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Efuse Self Test Functions 8 * . 9 * which are relevant for the System driver. 10 */ 11 12 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 13 14 #ifndef __sys_selftest_H__ 15 #define __sys_selftest_H__ 16 17 #include "reg_pbist.h" 18 #include "reg_stc.h" 19 #include "reg_efc.h" 20 #include "sys_core.h" 21 #include "system.h" 22 #include "sys_vim.h" 23 #include "adc.h" 24 #include "can.h" 25 #include "mibspi.h" 26 #include "het.h" 27 #include "htu.h" 28 #include "esm.h" 29 30 /* USER CODE BEGIN (0) */ 31 /* USER CODE END */ 32 33 #define flash1bitError (*(volatile uint32 *)(0xF00803F0U)) 34 #define flash2bitError (*(volatile uint32 *)(0xF00803F8U)) 35 36 #define tcramA1bitError (*(volatile uint32 *)(0x08400000U)) 37 #define tcramA2bitError (*(volatile uint32 *)(0x08400010U)) 38 39 #define tcramB1bitError (*(volatile uint32 *)(0x08400008U)) 40 #define tcramB2bitError (*(volatile uint32 *)(0x08400018U)) 41 42 #define tcramA1bit (*(volatile uint32 *)(0x08000000U)) 43 #define tcramA2bit (*(volatile uint32 *)(0x08000010U)) 44 45 #define tcramB1bit (*(volatile uint32 *)(0x08000008U)) 46 #define tcramB2bit (*(volatile uint32 *)(0x08000018U)) 47 48 #define flashBadECC (*(volatile uint32 *)(0x20040000U)) 49 50 #define CCMSR (*(volatile uint32 *)(0xFFFFF600U)) 51 #define CCMKEYR (*(volatile uint32 *)(0xFFFFF604U)) 52 53 54 #define DMA_PARCR (*(volatile uint32 *)(0xFFFFF1A8U)) 55 #define DMA_PARADDR (*(volatile uint32 *)(0xFFFFF1ACU)) 56 57 #define DMARAMLOC (*(volatile uint32 *)(0xFFF80000U)) 58 #define DMARAMPARLOC (*(volatile uint32 *)(0xFFF80A00U)) 59 60 61 #ifndef __PBIST_H__ 62 #define __PBIST_H__ 63 64 /** @enum pbistPort 65 * @brief Alias names for pbist Port number 66 * 67 * This enumeration is used to provide alias names for the pbist Port number 68 * - PBIST_PORT0 69 * - PBIST_PORT1 70 */ 71 enum pbistPort 72 { 73 PBIST_PORT0 = 0U, /**< Alias for PBIST Port 0 */ 74 PBIST_PORT1 = 1U /**< Alias for PBIST Port 1 */ 75 }; 76 /** @enum pbistAlgo 77 * @brief Alias names for pbist Algorithm 78 * 79 * This enumeration is used to provide alias names for the pbist Algorithm 80 * - PBIST_TripleReadSlow 81 * - PBIST_TripleReadFast 82 * - PBIST_March13N_DP 83 * - PBIST_March13N_SP 84 * - PBIST_DOWN1a_DP 85 * - PBIST_DOWN1a_SP 86 * - PBIST_MapColumn_DP 87 * - PBIST_MapColumn_SP 88 * - PBIST_Precharge_DP 89 * - PBIST_Precharge_SP 90 * - PBIST_DTXN2a_DP 91 * - PBIST_DTXN2a_SP 92 * - PBIST_PMOSOpen_DP 93 * - PBIST_PMOSOpen_SP 94 * - PBIST_PPMOSOpenSlice1_DP 95 * - PBIST_PPMOSOpenSlice1_SP 96 * - PBIST_PPMOSOpenSlice2_DP 97 * - PBIST_PPMOSOpenSlice2_SP 98 99 */ 100 enum pbistAlgo 101 { 102 PBIST_TripleReadSlow = 0x00000001U, 103 PBIST_TripleReadFast = 0x00000002U, 104 PBIST_March13N_DP = 0x00000004U, 105 PBIST_March13N_SP = 0x00000008U, 106 PBIST_DOWN1a_DP = 0x00000010U, 107 PBIST_DOWN1a_SP = 0x00000020U, 108 PBIST_MapColumn_DP = 0x00000040U, 109 PBIST_MapColumn_SP = 0x00000080U, 110 PBIST_Precharge_DP = 0x00000100U, 111 PBIST_Precharge_SP = 0x00000200U, 112 PBIST_DTXN2a_DP = 0x00000400U, 113 PBIST_DTXN2a_SP = 0x00000800U, 114 PBIST_PMOSOpen_DP = 0x00001000U, 115 PBIST_PMOSOpen_SP = 0x00002000U, 116 PBIST_PPMOSOpenSlice1_DP = 0x00004000U, 117 PBIST_PPMOSOpenSlice1_SP = 0x00008000U, 118 PBIST_PPMOSOpenSlice2_DP = 0x00010000U, 119 PBIST_PPMOSOpenSlice2_SP = 0x00020000U 120 }; 121 /* PBIST configuration registers */ 122 typedef struct pbist_config_reg 123 { 124 uint32 CONFIG_RAMT; 125 uint32 CONFIG_DLR; 126 uint32 CONFIG_PACT; 127 uint32 CONFIG_PBISTID; 128 uint32 CONFIG_OVER; 129 uint32 CONFIG_FSRDL1; 130 uint32 CONFIG_ROM; 131 uint32 CONFIG_ALGO; 132 uint32 CONFIG_RINFOL; 133 uint32 CONFIG_RINFOU; 134 } pbist_config_reg_t; 135 136 /* PBIST congiruration registers initial value */ 137 #define PBIST_RAMT_CONFIGVALUE 0U 138 #define PBIST_DLR_CONFIGVALUE 0U 139 #define PBIST_PACT_CONFIGVALUE 0U 140 #define PBIST_PBISTID_CONFIGVALUE 0U 141 #define PBIST_OVER_CONFIGVALUE 0U 142 #define PBIST_FSRDL1_CONFIGVALUE 0U 143 #define PBIST_ROM_CONFIGVALUE 0U 144 #define PBIST_ALGO_CONFIGVALUE 0U 145 #define PBIST_RINFOL_CONFIGVALUE 0U 146 #define PBIST_RINFOU_CONFIGVALUE 0U 147 148 149 /* USER CODE BEGIN (1) */ 150 /* USER CODE END */ 151 152 /** @fn void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data) 153 * @brief Memory Port 0 test fail notification 154 * @param[in] groupSelect Failing Ram group select: 155 * @param[in] dataSelect Failing Ram data select: 156 * @param[in] address Failing Ram offset: 157 * @param[in] data Failing data at address: 158 * 159 * @note This function has to be provide by the user. 160 */ 161 void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data); 162 163 /** @fn void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data) 164 * @brief Memory Port 1 test fail notification 165 * @param[in] groupSelect Failing Ram group select: 166 * @param[in] dataSelect Failing Ram data select: 167 * @param[in] address Failing Ram offset: 168 * @param[in] data Failing data at address: 169 * 170 * @note This function has to be provide by the user. 171 */ 172 void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data); 173 174 void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type); 175 #endif 176 177 #ifndef __STC_H__ 178 #define __STC_H__ 179 180 /* STC General Definitions */ 181 182 /* STC Test Intervals supported in the Device */ 183 #define STC_INTERVAL 24U 184 #define STC_MAX_TIMEOUT 0xFFFFFFFFU 185 186 187 188 /* Configuration registers */ 189 typedef struct stc_config_reg 190 { 191 uint32 CONFIG_STCGCR0; 192 uint32 CONFIG_STCGCR1; 193 uint32 CONFIG_STCTPR; 194 uint32 CONFIG_STCSCSCR; 195 } stc_config_reg_t; 196 197 /* Configuration registers initial value */ 198 #define STC_STCGCR0_CONFIGVALUE 0xFFFF0000U 199 #define STC_STCGCR1_CONFIGVALUE 0x5U 200 #define STC_STCTPR_CONFIGVALUE 0xFFFFFFFFU 201 #define STC_STCSCSCR_CONFIGVALUE 0x5U 202 203 void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type); 204 205 #endif 206 207 #ifndef __EFC_H__ 208 #define __EFC_H__ 209 210 #define INPUT_ENABLE 0x0000000FU 211 #define INPUT_DISABLE 0x00000000U 212 213 #define SYS_WS_READ_STATES 0x00000000U 214 215 216 #define SYS_REPAIR_EN_0 0x00000000U 217 #define SYS_REPAIR_EN_3 0x00000100U 218 #define SYS_REPAIR_EN_5 0x00000200U 219 220 #define SYS_DEID_AUTOLOAD_EN 0x00000400U 221 222 #define EFC_FDI_EN 0x00000800U 223 #define EFC_FDI_DIS 0x00000000U 224 225 #define SYS_ECC_OVERRIDE_EN 0x00001000U 226 #define SYS_ECC_OVERRIDE_DIS 0x00000000U 227 228 #define SYS_ECC_SELF_TEST_EN 0x00002000U 229 #define SYS_ECC_SELF_TEST_DIS 0x00000000U 230 231 #define OUTPUT_ENABLE 0x0003C000U 232 #define OUTPUT_DISABLE 0x00000000U 233 234 /*********** OUTPUT **************/ 235 236 #define EFC_AUTOLOAD_ERROR_EN 0x00040000U 237 #define EFC_INSTRUCTION_ERROR_EN 0x00080000U 238 #define EFC_INSTRUCTION_INFO_EN 0x00100000U 239 #define EFC_SELF_TEST_ERROR_EN 0x00200000U 240 241 242 #define EFC_AUTOLOAD_ERROR_DIS 0x00000000U 243 #define EFC_INSTRUCTION_ERROR_DIS 0x00000000U 244 #define EFC_INSTRUCTION_INFO_DIS 0x00000000U 245 #define EFC_SELF_TEST_ERROR_DIS 0x00000000U 246 247 #define DISABLE_READ_ROW0 0x00800000U 248 249 /********************************************************************/ 250 251 #define SYS_REPAIR_0 0x00000010U 252 #define SYS_REPAIR_3 0x00000010U 253 #define SYS_REPAIR_5 0x00000020U 254 255 #define SYS_DEID_AUTOLOAD 0x00000040U 256 #define SYS_FCLRZ 0x00000080U 257 #define EFC_READY 0x00000100U 258 #define SYS_ECC_OVERRIDE 0x00000200U 259 #define EFC_AUTOLOAD_ERROR 0x00000400U 260 #define EFC_INSTRUCTION_ERROR 0x00000800U 261 #define EFC_INSTRUCTION_INFO 0x00001000U 262 #define SYS_ECC_SELF_TEST 0x00002000U 263 #define EFC_SELF_TEST_ERROR 0x00004000U 264 #define EFC_SELF_TEST_DONE 0x00008000U 265 266 /************** 0x3C error status register ******************************************************/ 267 268 #define TIME_OUT 0x01 269 #define AUTOLOAD_NO_FUSEROM_DATA 0x02U 270 #define AUTOLOAD_SIGN_FAIL 0x03U 271 #define AUTOLOAD_PROG_INTERRUPT 0x04U 272 #define AUTOLOAD_TWO_BIT_ERR 0x05U 273 #define PROGRAME_WR_P_SET 0x06U 274 #define PROGRAME_MNY_DATA_ITERTN 0x07U 275 #define PROGRAME_MNY_CNTR_ITERTN 0x08U 276 #define UN_PROGRAME_BIT_SET 0x09U 277 #define REDUNDANT_REPAIR_ROW 0x0AU 278 #define PROGRAME_MNY_CRA_ITERTN 0x0BU 279 #define PROGRAME_SAME_DATA 0x0CU 280 #define PROGRAME_CMP_SKIP 0x0DU 281 #define PROGRAME_ABORT 0x0EU 282 #define PROGRAME_INCORRECT_KEY 0x0FU 283 #define FUSEROM_LASTROW_STUCK 0x10U 284 #define AUTOLOAD_SINGLE_BIT_ERR 0x15U 285 #define DUMPWORD_TWO_BIT_ERR 0x16U 286 #define DUMPWORD_ONE_BIT_ERR 0x17U 287 #define SELF_TEST_ERROR 0x18U 288 289 #define INSTRUCTION_DONE 0x20U 290 291 /************** Efuse Instruction set ******************************************************/ 292 293 #define TEST_UNPROGRAME_ROM 0x01000000U 294 #define PROGRAME_CRA 0x02000000U 295 #define DUMP_WORD 0x04000000U 296 #define LOAD_FUSE_SCAN_CHAIN 0x05000000U 297 #define PROGRAME_DATA 0x07000000U 298 #define RUN_AUTOLOAD_8 0x08000000U 299 #define RUN_AUTOLOAD_A 0x0A000000U 300 301 /* Configuration registers */ 302 typedef struct efc_config_reg 303 { 304 uint32 CONFIG_BOUNDARY; 305 uint32 CONFIG_PINS; 306 uint32 CONFIG_SELFTESTCYCLES; 307 uint32 CONFIG_SELFTESTSIGN; 308 }efc_config_reg_t; 309 310 /* Configuration registers initial value */ 311 #define EFC_BOUNDARY_CONFIGVALUE 0x0000200FU 312 #define EFC_PINS_CONFIGVALUE 0x000082E0U 313 #define EFC_SELFTESTCYCLES_CONFIGVALUE 0x00000258U 314 #define EFC_SELFTESTSIGN_CONFIGVALUE 0x5362F97FU 315 316 void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type); 317 #endif 318 319 /* safety Init Interface Functions */ 320 void ccmSelfCheck(void); 321 void ccmFail(uint32 x); 322 323 void stcSelfCheck(void); 324 void stcSelfCheckFail(void); 325 void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test); 326 void cpuSelfTestFail(void); 327 328 void memoryInit(uint32 ram); 329 330 void pbistSelfCheck(void); 331 void pbistRun(uint32 raminfoL, uint32 algomask); 332 void pbistStop(void); 333 void pbistSelfCheckFail(void); 334 boolean pbistIsTestCompleted(void); 335 boolean pbistIsTestPassed(void); 336 boolean pbistPortTestStatus(uint32 port); 337 338 void efcCheck(void); 339 void efcSelfTest(void); 340 boolean efcStuckZeroTest(void); 341 boolean checkefcSelfTest(void); 342 void efcClass1Error(void); 343 void efcClass2Error(void); 344 345 void fmcBus2Check(void); 346 void fmcECCcheck(void); 347 void fmcClass1Error(void); 348 void fmcClass2Error(void); 349 350 void checkB0RAMECC(void); 351 void checkB1RAMECC(void); 352 void tcramClass1Error(void); 353 void tcramClass2Error(void); 354 355 void checkFlashECC(void); 356 void flashClass1Error(void); 357 void flashClass2Error(void); 358 359 void vimParityCheck(void); 360 void dmaParityCheck(void); 361 void adc1ParityCheck(void); 362 void adc2ParityCheck(void); 363 void het1ParityCheck(void); 364 void htu1ParityCheck(void); 365 void het2ParityCheck(void); 366 void htu2ParityCheck(void); 367 void can1ParityCheck(void); 368 void can2ParityCheck(void); 369 void can3ParityCheck(void); 370 void mibspi1ParityCheck(void); 371 void mibspi3ParityCheck(void); 372 void mibspi5ParityCheck(void); 373 374 /* USER CODE BEGIN (2) */ 375 /* USER CODE END */ 376 377 /* Configuration registers */ 378 typedef struct ccmr4_config_reg 379 { 380 uint32 CONFIG_CCMKEYR; 381 }ccmr4_config_reg_t; 382 383 /* Configuration registers initial value */ 384 #define CCMR4_CCMKEYR_CONFIGVALUE 0U 385 386 void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type); 387 #endif 388