1 /* Copyright (c) 2023, Canaan Bright Sight Co., Ltd 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are met: 5 * 1. Redistributions of source code must retain the above copyright 6 * notice, this list of conditions and the following disclaimer. 7 * 2. Redistributions in binary form must reproduce the above copyright 8 * notice, this list of conditions and the following disclaimer in the 9 * documentation and/or other materials provided with the distribution. 10 * 11 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 12 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 13 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 15 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 16 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 17 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 23 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #ifndef __SYSCTL_CLK_H__ 27 #define __SYSCTL_CLK_H__ 28 29 #include <stdint.h> 30 #include <stdbool.h> 31 32 /* See TRM 2.2.4 Table 2-2-9 */ 33 typedef struct sysctl_clk { 34 volatile uint32_t cpu0_clk_cfg; /* 0x00 */ 35 volatile uint32_t reserved_0; /* 0x04 */ 36 volatile uint32_t reserved_1; /* 0x08 */ 37 volatile uint32_t reserved_2; /* 0x0c */ 38 volatile uint32_t pmu_clk_cfg; /* 0x10 */ 39 volatile uint32_t reserved0[1]; /* 0x14 */ 40 volatile uint32_t hs_clken_cfg; /* 0x18 */ 41 volatile uint32_t hs_sdclk_cfg; /* 0x1c */ 42 volatile uint32_t hs_spi_cfg; /* 0x20 */ 43 volatile uint32_t ls_clken_cfg0; /* 0x24 */ 44 volatile uint32_t ls_clken_cfg1; /* 0x28 */ 45 volatile uint32_t uart_i2c_clkdiv_cfg; /* 0x2c */ 46 volatile uint32_t ls_clkdiv_cfg; /* 0x30 */ 47 volatile uint32_t reserved_3; /* 0x34 */ 48 volatile uint32_t reserved_4; /* 0x38 */ 49 volatile uint32_t reserved_5; /* 0x3c */ 50 volatile uint32_t reserved_6; /* 0x40 */ 51 volatile uint32_t reserved_7; /* 0x44 */ 52 volatile uint32_t reserved1[2]; /* 0x48 0x4c */ 53 volatile uint32_t sysctl_clken_cfg; /* 0x50 */ 54 volatile uint32_t timer_clk_cfg; /* 0x54 */ 55 volatile uint32_t sysctl_clk_div_cfg; /* 0x58 */ 56 volatile uint32_t shrm_clk_cfg; /* 0x5c */ 57 volatile uint32_t ddr_clk_cfg; /* 0x60 */ 58 volatile uint32_t reserved_8; /* 0x64 */ 59 volatile uint32_t reserved_9; /* 0x68 */ 60 volatile uint32_t reserved_10; /* 0x6c */ 61 volatile uint32_t reserved_11; /* 0x70 */ 62 volatile uint32_t reserved_12; /* 0x74 */ 63 volatile uint32_t reserved_13; /* 0x78 */ 64 volatile uint32_t reserved2[1]; /* 0x7c */ 65 volatile uint32_t sec_clk_div; /* 0x80 */ 66 volatile uint32_t reserved3[31]; /* 0x84 0x88 0x8c 0x90 0x94 0x98 0x9c 0xa0-0xac 0xb0-0xbc 0xc0-0xcc 0xd0-0xdc 0xe0-0xec 0xf0-0xfc*/ 67 volatile uint32_t usb_test_clk_div; /* 0x100 */ 68 volatile uint32_t dphy_test_clk_div; /* 0x104 */ 69 volatile uint32_t spi2axi_clk_div; /* 0x108 */ 70 } sysctl_clk_t; 71 72 /* 73 * Clock Tree and clock node table 74 * 75 * Abbreviations: 76 * - D: DIV 77 * - G: GATE 78 * - M: MUX 79 * - fD: fraDIV 80 */ 81 typedef enum { 82 /* 83 * First level is sysctl_boot / sysctrl_root module, which 84 * is composed of osc24m, pll[0|1|2|3], pll[0|1|2|3]_[div2|div3|div4] (pllx 85 * outputs 4 signals, namely pllx, div2, div3, and div4). 86 * Plus timerx_pulse_in, which is an external pulse input through the soc 87 * pin (pinmux) as a source of timer clock. 88 * 89 * - osc24m: fixed-clock 90 * - pll[0|1|2|3]: clock generated by PLL 91 * - pll[0|1|2|3]_[div2|div3|div4]: fixed-clock 92 * - timerx_pulse_in: fixed-clock, maxsize is 1MHz 93 * 94 * osc24m ---+--> pll0 ---+--------> pll0 ------->+ 95 * | +--(D2)--> pll0_div2 -->| 96 * | +--(D3)--> pll0_div3 -->| 97 * | +--(D4)--> pll0_div4 -->| 98 * | | 99 * +--> pll1 ---+--------> pll1 ------->| 100 * | +--(D2)--> pll1_div2 -->| 101 * | +--(D3)--> pll1_div3 -->| 102 * | +--(D4)--> pll1_div4 -->| 103 * | +--> sysctl_clock 104 * +--> pll2 ---+--------> pll2 ------->| 105 * | +--(D2)--> pll2_div2 -->| 106 * | +--(D3)--> pll2_div3 -->| 107 * | +--(D4)--> pll2_div4 -->| 108 * | | 109 * +--> pll3 ---+--------> pll3 ------->| 110 * | +--(D2)--> pll3_div2 -->| 111 * | +--(D3)--> pll3_div3 -->| 112 * | +--(D4)--> pll3_div4 -->| 113 * | | 114 * +----------------------------------->+ 115 * | 116 * timerx_pulse_in ------------------------------>+ 117 */ 118 SYSCTL_CLK_ROOT_OSC_IN = 0, /* 24M */ 119 SYSCTL_CLK_ROOT_TIMERX_PULSE_IN, /* 50M */ 120 SYSCTL_CLK_ROOT_PLL0, /* 1.6G */ 121 SYSCTL_CLK_ROOT_PLL0_DIV_2, /* 800M */ 122 SYSCTL_CLK_ROOT_PLL0_DIV_3, /* 533M */ 123 SYSCTL_CLK_ROOT_PLL0_DIV_4, /* 400M */ 124 SYSCTL_CLK_ROOT_PLL1, /* 2.376G */ 125 SYSCTL_CLK_ROOT_PLL1_DIV_2, /* 1.188G */ 126 SYSCTL_CLK_ROOT_PLL1_DIV_3, /* 792M */ 127 SYSCTL_CLK_ROOT_PLL1_DIV_4, /* 594M */ 128 SYSCTL_CLK_ROOT_PLL2, /* 2.667G */ 129 SYSCTL_CLK_ROOT_PLL2_DIV_2, /* 1.3335G */ 130 SYSCTL_CLK_ROOT_PLL2_DIV_3, /* 889M */ 131 SYSCTL_CLK_ROOT_PLL2_DIV_4, /* 666.75M */ 132 SYSCTL_CLK_ROOT_PLL3, /* 1.6G */ 133 SYSCTL_CLK_ROOT_PLL3_DIV_2, /* 800M */ 134 SYSCTL_CLK_ROOT_PLL3_DIV_3, /* 533M */ 135 SYSCTL_CLK_ROOT_PLL3_DIV_4, /* 400M */ 136 SYSCTL_CLK_ROOT_MAX, 137 138 /* 139 * Second level is sysctl_clock module, which is composed of several clock sub-trees 140 * - CPU0: aclk/pliclk/pclk 141 * - pmu system: pclk 142 * - HS (High Speed) system: hs/sdx/ssix/usbx 143 * - LS (Low Speed) system : ls/uartx/i2cx/gpio/pwm/jamlinkx/audio/adc/codec 144 * - System Control (such as wdt, timer, iomux, mailbox): sysctl/wdtx/timer/iomux/mailbox/hdi/stc/ts 145 * - Timer: timerx 146 * - shrm (share memory) system: shrm/decompress/gsdma/nonai2d/pdma 147 * - sec (security) system: aclk/fixclk/pclk 148 * - usb test mode: clk480/clk100 149 * - dphy dft mode clock: dphy_test_clk 150 * - spi2axi clock: aclk 151 */ 152 153 /* 154 * cpu0 clock tree: 155 * 156 * pll0_div2 --(DG)--> cpu0_src --+--(DG)--> cpu0_plic 157 * |--(D)---> cpu0_aclk 158 * +--(G)---> cpu0_noc_ddrcp4 159 * pll0_div4 --(DG)--> cpu0_pclk 160 */ 161 162 /* root node: pll0_div2 */ 163 SYSCTL_CLK_CPU0_SRC, /* cpu0 core，defualt 800MHz ---> select pll0_div_2 */ 164 SYSCTL_CLK_CPU0_PLIC, /* cpu0 plic clk，400MHz */ 165 SYSCTL_CLK_CPU0_ACLK, /* cpu0 axi clk，400MHz */ 166 SYSCTL_CLK_CPU0_NOC_DDRCP4, /* ddrc axi4clk & noc AXI clock，400MHz */ 167 /* root node: pll0_div4 */ 168 SYSCTL_CLK_CPU0_PCLK, /* cpu0 apb pclk，200MHz */ 169 170 /* 171 * pmu system clock tree: 172 * 173 * osc24m -->(G)--> pmu_pclk 174 * 175 * - pmu_pclk: pmu apb clk gate 176 */ 177 SYSCTL_CLK_PMU_PCLK, 178 179 /* 180 * High-Speed system clock tree 181 * 182 * pll0_div4 --+--(D)--> hs_hclk_high_src --+--(G)----> hs_hclk_high_gate 183 * | | 184 * | +--(DG)--> hs_hclk_src --+--(G)--> sd0_ahb_gate 185 * | |--(G)--> sd1_ahb_gate 186 * | |--(G)--> ssi1_ahb_gate 187 * | |--(G)--> ssi2_ahb_gate 188 * | |--(G)--> usb0_ahb_gate 189 * | +--(G)--> usb1_ahb_gate 190 * | 191 * +--(DG)--> ssi0_axi 192 * |--(DG)--> ssi1 193 * |--(DG)--> ssi2 194 * +--(DG)--> qspi_axi_src --+--(G)--> ssi1_aclk_gate 195 * | | 196 * | +--(G)--> ssi2_aclk_gate 197 * | 198 * +--(DG)--> sd_card_src --+--(G)--> sd0_card_gate 199 * | 200 * +--(G)--> sd1_card_gate 201 * 202 * pll0_div2 --\ 203 * (M)--(G)--> ssi0 204 * pll2_div4 --/ 205 * 206 * 207 * pll2_div4 --(DG)--> sd_axi_src --+--(G)--> sd0_axi_gate 208 * |--(G)--> sd1_axi_gate 209 * |--(G)--> sd0_base_gate 210 * +--(G)--> sd1_base_gate 211 * 212 * 213 * 214 * osc24m -----------------------------------------\ 215 * (M)--+--(G)--> usb0_ref_gate 216 * pll0 --(D)--> pll0_div16 --(D)--> usb_ref_50m --/ | 217 * +--(G)--> usb1_ref_gate 218 * 219 * 220 * osc24m --(DG)--> sd_timer_src --+--(G)--> sd0_timer_gate 221 * | 222 * +--(G)--> sd1_timer_gate 223 */ 224 225 /* root node: pll0_div4, through hs_hclk_high_src */ 226 SYSCTL_CLK_HS_HCLK_HIGH_SRC, 227 SYSCTL_CLK_HS_HCLK_HIGH_GATE, 228 SYSCTL_CLK_HS_HCLK_SRC, 229 SYSCTL_CLK_SD0_AHB_GATE, 230 SYSCTL_CLK_SD1_AHB_GATE, 231 SYSCTL_CLK_USB0_AHB_GATE, 232 SYSCTL_CLK_USB1_AHB_GATE, 233 SYSCTL_CLK_SSI1_AHB_GATE, 234 SYSCTL_CLK_SSI2_AHB_GATE, 235 236 /* root node: pll0_div4 */ 237 SYSCTL_CLK_SSI0_AXI, 238 SYSCTL_CLK_SSI1, 239 SYSCTL_CLK_SSI2, 240 SYSCTL_CLK_QSPI_AXI_SRC, 241 SYSCTL_CLK_SSI1_ACLK_GATE, 242 SYSCTL_CLK_SSI2_ACLK_GATE, 243 244 /*root node: pll0_div4, through sd_card_src */ 245 SYSCTL_CLK_SD_CARD_SRC, 246 SYSCTL_CLK_SD0_CARD_GATE, 247 SYSCTL_CLK_SD1_CARD_GATE, 248 249 /* root node: pll0_div2 MUX pll2_div4 */ 250 SYSCTL_CLK_SSI0, /* ospi core clk */ 251 252 /* root node: pll2_div4 */ 253 SYSCTL_CLK_SD_AXI_SRC, 254 SYSCTL_CLK_SD0_AXI_GATE, 255 SYSCTL_CLK_SD1_AXI_GATE, 256 SYSCTL_CLK_SD0_BASE_GATE, 257 SYSCTL_CLK_SD1_BASE_GATE, 258 259 /* root node: pll0_div16 */ 260 SYSCTL_CLK_PLL0_DIV16, 261 SYSCTL_CLK_USB_REF_50M, /* usbx reference clk */ 262 SYSCTL_CLK_USB0_REF_GATE, 263 SYSCTL_CLK_USB1_REF_GATE, 264 265 /* root node: osc24m */ 266 SYSCTL_CLK_SD_TIMER_SRC, 267 SYSCTL_CLK_SD0_TIMER_GATE, 268 SYSCTL_CLK_SD1_TIMER_GATE, 269 270 /* Low-Speed system clock tree 271 * 272 * pll0_div4 --(DG)--+--> ls_apb_src --+--(G) --> uart0_apb_gate 273 * | +--(G) --> uart1_apb_gate 274 * | +--(G) --> uart2_apb_gate 275 * | +--(G) --> uart3_apb_gate 276 * | +--(G) --> uart4_apb_gate 277 * | +--(G) --> i2c0_apb_gate 278 * | +--(G) --> i2c1_apb_gate 279 * | +--(G) --> i2c2_apb_gate 280 * | +--(G) --> i2c3_apb_gate 281 * | +--(G) --> i2c4_apb_gate 282 * | +--(G) --> gpio_apb_gate 283 * | +--(G) --> pwm_apb_gate 284 * | +--(G) --> jamlink0_apb_gate 285 * | +--(G) --> jamlink1_apb_gate 286 * | +--(G) --> jamlink2_apb_gate 287 * | +--(G) --> jamlink3_apb_gate 288 * | +--(G) --> audio_apb_gate 289 * | +--(G) --> adc_apb_gate 290 * | +--(G) --> codec_apb_gate 291 * | 292 * +--(DG)--> i2c0_core 293 * +--(DG)--> i2c1_core 294 * +--(DG)--> i2c2_core 295 * +--(DG)--> i2c3_core 296 * +--(DG)--> i2c4_core 297 * +--(DG)--> codec_adc 298 * +--(DG)--> codec_dac 299 * +--(DG)--> audio_dev 300 * +--(DG)--> pdm 301 * +--(DG)--> adc 302 * 303 * pll0 --(D)--> pll0_div16 --+--(DG)--> uart0_core 304 * +--(DG)--> uart1_core 305 * +--(DG)--> uart2_core 306 * +--(DG)--> uart3_core 307 * +--(DG)--> uart4_core 308 * 309 * pll0 --(D)--> pll0_div16 --(D)--> jamlink_CO_div --+--(G)--> jamlink0_CO_gate 310 * +--(G)--> jamlink1_CO_gate 311 * +--(G)--> jamlink2_CO_gate 312 * +--(G)--> jamlink3_CO_gate 313 * 314 * osc24m --(DG)--> gpio_debounce 315 */ 316 317 /* root node: pll0_div4, through ls_apb_src */ 318 SYSCTL_CLK_LS_APB_SRC, 319 SYSCTL_CLK_UART0_APB_GATE, 320 SYSCTL_CLK_UART1_APB_GATE, 321 SYSCTL_CLK_UART2_APB_GATE, 322 SYSCTL_CLK_UART3_APB_GATE, 323 SYSCTL_CLK_UART4_APB_GATE, 324 SYSCTL_CLK_I2C0_APB_GATE, 325 SYSCTL_CLK_I2C1_APB_GATE, 326 SYSCTL_CLK_I2C2_APB_GATE, 327 SYSCTL_CLK_I2C3_APB_GATE, 328 SYSCTL_CLK_I2C4_APB_GATE, 329 SYSCTL_CLK_GPIO_APB_GATE, 330 SYSCTL_CLK_PWM_APB_GATE, 331 SYSCTL_CLK_JAMLINK0_APB_GATE, 332 SYSCTL_CLK_JAMLINK1_APB_GATE, 333 SYSCTL_CLK_JAMLINK2_APB_GATE, 334 SYSCTL_CLK_JAMLINK3_APB_GATE, 335 SYSCTL_CLK_AUDIO_APB_GATE, 336 SYSCTL_CLK_ADC_APB_GATE, 337 SYSCTL_CLK_CODEC_APB_GATE, 338 339 /* root node: pll0_div4 */ 340 SYSCTL_CLK_I2C0_CORE, 341 SYSCTL_CLK_I2C1_CORE, 342 SYSCTL_CLK_I2C2_CORE, 343 SYSCTL_CLK_I2C3_CORE, 344 SYSCTL_CLK_I2C4_CORE, 345 SYSCTL_CLK_CODEC_ADC, 346 SYSCTL_CLK_CODEC_DAC, 347 SYSCTL_CLK_AUDIO_DEV, 348 SYSCTL_CLK_PDM, 349 SYSCTL_CLK_ADC, 350 351 /* root node: pll0_div16 */ 352 SYSCTL_CLK_UART0_CORE, 353 SYSCTL_CLK_UART1_CORE, 354 SYSCTL_CLK_UART2_CORE, 355 SYSCTL_CLK_UART3_CORE, 356 SYSCTL_CLK_UART4_CORE, 357 358 /* root node: pll0_div16, through jamlink_CO_div */ 359 SYSCTL_CLK_JAMLINK_CO_DIV, 360 SYSCTL_CLK_JAMLINK0_CO_GATE, 361 SYSCTL_CLK_JAMLINK1_CO_GATE, 362 SYSCTL_CLK_JAMLINK2_CO_GATE, 363 SYSCTL_CLK_JAMLINK3_CO_GATE, 364 365 /* root node: osc24m */ 366 SYSCTL_CLK_GOIP_DEBOUNCE, 367 368 /* 369 * System Control clock tree 370 * 371 * pll0_div16 --> sysctl_apb_src --+--(G)--> wdt0_apb_gate 372 * +--(G)--> wdt1_apb_gate 373 * +--(G)--> timer_apb_gate 374 * +--(G)--> iomux_apb_gate 375 * +--(G)--> mailbox_apb_gate 376 * 377 * pll0_div4 --(DG)--> hdi_core 378 * 379 * pll1_div4 --(DG)--> timestamp 380 * 381 * osc24m --(D)--> temp_sensor 382 * 383 * osc24m --+--(DG)--> wdt0 384 * | 385 * +--(DG)--> wdt1 386 */ 387 388 /* root node: pll0_div16, through sysctl_apb_src */ 389 SYSCTL_CLK_SYSCTRL_APB_SRC, 390 SYSCTL_CLK_WDT0_APB_GATE, 391 SYSCTL_CLK_WDT1_APB_GATE, 392 SYSCTL_CLK_TIMER_APB_GATE, 393 SYSCTL_CLK_IOMUX_APB_GATE, 394 SYSCTL_CLK_MAILBOX_APB_GATE, 395 396 /* root node: pll0_div4 */ 397 SYSCTL_CLK_HDI_CORE, 398 399 /* root node: pll1_div4 */ 400 SYSCTL_CLK_TIMESTAMP, 401 402 /* root node: osc24m */ 403 SYSCTL_CLK_TEMP_SENSOR, 404 405 /* root node: osc24m */ 406 SYSCTL_CLK_WDT0, 407 SYSCTL_CLK_WDT1, 408 409 /* 410 * timer clock tree 411 * 412 * pll0_div16 --(D)--> timer0_src --\ 413 * (M)--(G)-->timer0 414 * timerx_pulse_in -----------------/ 415 * 416 * pll0_div16 --(D)--> timer1_src --\ 417 * (M)--(G)-->timer1 418 * timerx_pulse_in -----------------/ 419 * 420 * pll0_div16 --(D)--> timer2_src --\ 421 * (M)--(G)-->timer2 422 * timerx_pulse_in -----------------/ 423 * 424 * pll0_div16 --(D)--> timer3_src --\ 425 * (M)--(G)-->timer3 426 * timerx_pulse_in -----------------/ 427 * 428 * pll0_div16 --(D)--> timer4_src --\ 429 * (M)--(G)-->timer4 430 * timerx_pulse_in -----------------/ 431 * 432 * pll0_div16 --(D)--> timer5_src --\ 433 * (M)--(G)-->timer5 434 * timerx_pulse_in -----------------/ 435 */ 436 437 /* root node: pll0_div16 & timerx_pulse_in */ 438 SYSCTL_CLK_TIMERX_PULSE_IN, 439 SYSCTL_CLK_TIMER0_SRC, 440 SYSCTL_CLK_TIMER0, 441 SYSCTL_CLK_TIMER1_SRC, 442 SYSCTL_CLK_TIMER1, 443 SYSCTL_CLK_TIMER2_SRC, 444 SYSCTL_CLK_TIMER2, 445 SYSCTL_CLK_TIMER3_SRC, 446 SYSCTL_CLK_TIMER3, 447 SYSCTL_CLK_TIMER4_SRC, 448 SYSCTL_CLK_TIMER4, 449 SYSCTL_CLK_TIMER5_SRC, 450 SYSCTL_CLK_TIMER5, 451 452 /* 453 * shrm system clock tree 454 * 455 * pll0_div2 --\ 456 * (M)--(G)--> shrm_src --+--(D)--> shrm_div2 --(G)--> shrm_axi_slave 457 * pll3_div2 --/ | 458 * +--(G)--> decompress_axi 459 * 460 * pll0_div4 -->(DG)--> shrm_apb 461 * 462 * pll0_div4 -->(G)--> shrm_axi_src --+--(G)--> gsdma_axi_gate 463 * +--(G)--> nonai2d_axi_gate 464 * +--(G)--> peri_dma_axi_gate 465 */ 466 467 /* root node: pll0_div2 & pll3_div2 */ 468 SYSCTL_CLK_SHRM_SRC, 469 SYSCTL_CLK_SHRM_DIV2, 470 SYSCTL_CLK_SHRM_AXIS_SLAVE, 471 SYSCTL_CLK_DECOMPRESS_AXI, 472 473 /* root node: pll0_div4 */ 474 SYSCTL_CLK_SHRM_APB, 475 476 /* root node: pll0_div4, through shrm_axi_src */ 477 SYSCTL_CLK_SHRM_AXI_SRC, 478 SYSCTL_CLK_GSDMA_AXI_GATE, 479 SYSCTL_CLK_NONAI2D_AXI_GATE, 480 SYSCTL_CLK_PERI_DMA_AXI_GATE, 481 482 /* 483 * Security system clock tree 484 * 485 * pll0_div4 --(DG)--> sec_apb 486 * 487 * pll1_div4 --+--(DG)--> sec_fix 488 * | 489 * +--(DG)--> sec_axi 490 */ 491 492 /* root node: pll0_div4 */ 493 SYSCTL_CLK_SEC_APB, 494 495 /* root node: pll1_div4 */ 496 SYSCTL_CLK_SEC_FIX, 497 SYSCTL_CLK_SEC_AXI, 498 499 /* 500 * usb test mode clock tree 501 * 502 * pll1 --(DG)--> usb_480m 503 * 504 * pll0_div4 --(DG)--> usb_100m 505 */ 506 507 /* root node: pll1 */ 508 SYSCTL_CLK_USB_480M, 509 510 /* root node: pll0_div4 */ 511 SYSCTL_CLK_USB_100M, 512 513 /* 514 * dphy dft mode clock tree 515 * 516 * pll0 --(DG)--> dphy_dft_mode 517 */ 518 519 /* root node: pll0 */ 520 SYSCTL_CLK_DPHY_DFT_MODE, 521 522 /* 523 * spi2axi clock tree 524 * 525 * pll0_div4 --(DG)--> spi2axi_axi 526 */ 527 528 /* root node: pll0_div4 */ 529 SYSCTL_CLK_SPI2AXI_AXI, 530 531 SYSCTL_CLK_NODE_MAX, 532 } sysctl_clk_node_e; 533 534 #define SYSCTL_READ_ENABLE (1 << 0) 535 #define SYSCTL_READ_DISABLE (0 << 0) 536 #define SYSCTL_WRITE_ENABLE (1 << 1) 537 #define SYSCTL_WRITE_DISABLE (0 << 1) 538 539 /* 540 * API for root clock. 24M, PLL0-3, these 5 clocks are root clocks 541 * It is assumed here that the big core has read and write permissions to the 542 * root clock, so the properties of clk are not judged in these APIs, 543 * because these APIs are only for the root clock. 544 */ 545 546 /* 547 * Get the bypass status of the PLL. 548 * If it is bypas, the PLL output is 24M OSC clock. 549 */ 550 bool sysctl_boot_get_root_clk_bypass(sysctl_clk_node_e clk); 551 void sysctl_boot_set_root_clk_bypass(sysctl_clk_node_e clk, bool enable); 552 553 /* Enable pll, enable 24M clock&pll */ 554 bool sysctl_boot_get_root_clk_en(sysctl_clk_node_e clk); 555 void sysctl_boot_set_root_clk_en(sysctl_clk_node_e clk, bool enable); 556 557 /* Get the phase-locked loop lock status */ 558 bool sysctl_boot_get_root_clk_lock(sysctl_clk_node_e clk); 559 560 /* Get the root clock frequency */ 561 uint32_t sysctl_boot_get_root_clk_freq(sysctl_clk_node_e clk); 562 563 /* 564 * Set the PLL clock frequency 565 * The formula for setting the PLL clock frequency is: 566 * pll_out_freq = (double)OSC_CLOCK_FREQ_24M * (double)(fbdiv+1) / (double)(refdiv+1) / (double)(outdiv+1) 567 */ 568 bool sysctl_boot_set_root_clk_freq(sysctl_clk_node_e clk, uint32_t fbdiv, uint32_t refdiv, uint32_t outdiv, uint32_t bwadj); 569 570 /* 571 * API for trunk and leaf nodes in the clock tree, i.e. clocks other than the five root clocks. 572 */ 573 574 /* 575 * Set the leaf node clock source on the clock tree. 576 * Please set it according to the clock tree. 577 * Many clock nodes have only one clock source, so the setting will return false. 578 */ 579 bool sysctl_clk_set_leaf_parent(sysctl_clk_node_e leaf, sysctl_clk_node_e parent); 580 581 /* Get the clock source of the leaf node in the clock tree */ 582 sysctl_clk_node_e sysctl_clk_get_leaf_parent(sysctl_clk_node_e leaf); 583 584 /* 585 * Set the clock node enable. 586 * Note: only set the enable of this clock node, and do not set the enable of 587 * the upstream clock. 588 * Difference from Linux kernel: Linux kernel clock framework will automatically 589 * set the enable of the upstream clock. The test code does not have kernel 590 * framework, so only the enable of the clock of this node is set. 591 */ 592 void sysctl_clk_set_leaf_en(sysctl_clk_node_e leaf, bool enable); 593 594 /* Get the enable status of this clock node */ 595 bool sysctl_clk_get_leaf_en(sysctl_clk_node_e leaf); 596 597 /* Set the frequency division factor of this clock node */ 598 bool sysctl_clk_set_leaf_div(sysctl_clk_node_e leaf, uint32_t numerator, uint32_t denominator); 599 600 /* Get the frequency division coefficient of this clock node */ 601 double sysctl_clk_get_leaf_div(sysctl_clk_node_e leaf); 602 603 /* 604 * Calculate clock freqency. 605 * This API searches the entire clock path, calculates the frequency division 606 * at each level starting from the clock source, and finally obtains the 607 * current clock frequency. 608 */ 609 uint32_t sysctl_clk_get_leaf_freq(sysctl_clk_node_e leaf); 610 611 #endif /* __SYSCTL_CLK_H__ */