1 /*
2 ** ###################################################################
3 ** Processors: MK64FN1M0CAJ12
4 ** MK64FN1M0VDC12
5 ** MK64FN1M0VLL12
6 ** MK64FN1M0VLQ12
7 ** MK64FN1M0VMD12
8 ** MK64FX512VDC12
9 ** MK64FX512VLL12
10 ** MK64FX512VLQ12
11 ** MK64FX512VMD12
12 **
13 ** Compilers: Keil ARM C/C++ Compiler
14 ** Freescale C/C++ for Embedded ARM
15 ** GNU C Compiler
16 ** IAR ANSI C/C++ Compiler for ARM
17 ** MCUXpresso Compiler
18 **
19 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
20 ** Version: rev. 2.9, 2016-03-21
21 ** Build: b170112
22 **
23 ** Abstract:
24 ** Provides a system configuration function and a global variable that
25 ** contains the system frequency. It configures the device and initializes
26 ** the oscillator (PLL) that is part of the microcontroller device.
27 **
28 ** Copyright (c) 2016 Freescale Semiconductor, Inc.
29 ** Copyright 2016 - 2017 NXP
30 ** Redistribution and use in source and binary forms, with or without modification,
31 ** are permitted provided that the following conditions are met:
32 **
33 ** o Redistributions of source code must retain the above copyright notice, this list
34 ** of conditions and the following disclaimer.
35 **
36 ** o Redistributions in binary form must reproduce the above copyright notice, this
37 ** list of conditions and the following disclaimer in the documentation and/or
38 ** other materials provided with the distribution.
39 **
40 ** o Neither the name of the copyright holder nor the names of its
41 ** contributors may be used to endorse or promote products derived from this
42 ** software without specific prior written permission.
43 **
44 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
45 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
46 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
47 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
48 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
51 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
53 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 **
55 ** http: www.nxp.com
56 ** mail: support@nxp.com
57 **
58 ** Revisions:
59 ** - rev. 1.0 (2013-08-12)
60 ** Initial version.
61 ** - rev. 2.0 (2013-10-29)
62 ** Register accessor macros added to the memory map.
63 ** Symbols for Processor Expert memory map compatibility added to the memory map.
64 ** Startup file for gcc has been updated according to CMSIS 3.2.
65 ** System initialization updated.
66 ** MCG - registers updated.
67 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
68 ** - rev. 2.1 (2013-10-30)
69 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
70 ** - rev. 2.2 (2013-12-09)
71 ** DMA - EARS register removed.
72 ** AIPS0, AIPS1 - MPRA register updated.
73 ** - rev. 2.3 (2014-01-24)
74 ** Update according to reference manual rev. 2
75 ** ENET, MCG, MCM, SIM, USB - registers updated
76 ** - rev. 2.4 (2014-02-10)
77 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
78 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
79 ** - rev. 2.5 (2014-02-10)
80 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
81 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
82 ** Module access macro module_BASES replaced by module_BASE_PTRS.
83 ** - rev. 2.6 (2014-08-28)
84 ** Update of system files - default clock configuration changed.
85 ** Update of startup files - possibility to override DefaultISR added.
86 ** - rev. 2.7 (2014-10-14)
87 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
88 ** - rev. 2.8 (2015-02-19)
89 ** Renamed interrupt vector LLW to LLWU.
90 ** - rev. 2.9 (2016-03-21)
91 ** Added MK64FN1M0CAJ12 part.
92 ** GPIO - renamed port instances: PTx -> GPIOx.
93 **
94 ** ###################################################################
95 */
96
97 /*!
98 * @file MK64F12
99 * @version 2.9
100 * @date 2016-03-21
101 * @brief Device specific configuration file for MK64F12 (implementation file)
102 *
103 * Provides a system configuration function and a global variable that contains
104 * the system frequency. It configures the device and initializes the oscillator
105 * (PLL) that is part of the microcontroller device.
106 */
107
108 #include <stdint.h>
109 #include "fsl_device_registers.h"
110
111
112
113 /* ----------------------------------------------------------------------------
114 -- Core clock
115 ---------------------------------------------------------------------------- */
116
117 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
118
119 /* ----------------------------------------------------------------------------
120 -- SystemInit()
121 ---------------------------------------------------------------------------- */
122
SystemInit(void)123 void SystemInit (void) {
124 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
125 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
126 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
127 #if (DISABLE_WDOG)
128 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
129 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
130 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
131 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
132 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
133 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
134 WDOG_STCTRLH_WAITEN_MASK |
135 WDOG_STCTRLH_STOPEN_MASK |
136 WDOG_STCTRLH_ALLOWUPDATE_MASK |
137 WDOG_STCTRLH_CLKSRC_MASK |
138 0x0100U;
139 #endif /* (DISABLE_WDOG) */
140
141 }
142
143 /* ----------------------------------------------------------------------------
144 -- SystemCoreClockUpdate()
145 ---------------------------------------------------------------------------- */
146
SystemCoreClockUpdate(void)147 void SystemCoreClockUpdate (void) {
148 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
149 uint16_t Divider;
150
151 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
152 /* Output of FLL or PLL is selected */
153 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
154 /* FLL is selected */
155 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
156 /* External reference clock is selected */
157 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
158 case 0x00U:
159 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
160 break;
161 case 0x01U:
162 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
163 break;
164 case 0x02U:
165 default:
166 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
167 break;
168 }
169 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
170 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
171 case 0x38U:
172 Divider = 1536U;
173 break;
174 case 0x30U:
175 Divider = 1280U;
176 break;
177 default:
178 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
179 break;
180 }
181 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
182 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
183 }
184 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
185 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
186 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
187 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
188 /* Select correct multiplier to calculate the MCG output clock */
189 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
190 case 0x00U:
191 MCGOUTClock *= 640U;
192 break;
193 case 0x20U:
194 MCGOUTClock *= 1280U;
195 break;
196 case 0x40U:
197 MCGOUTClock *= 1920U;
198 break;
199 case 0x60U:
200 MCGOUTClock *= 2560U;
201 break;
202 case 0x80U:
203 MCGOUTClock *= 732U;
204 break;
205 case 0xA0U:
206 MCGOUTClock *= 1464U;
207 break;
208 case 0xC0U:
209 MCGOUTClock *= 2197U;
210 break;
211 case 0xE0U:
212 MCGOUTClock *= 2929U;
213 break;
214 default:
215 break;
216 }
217 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
218 /* PLL is selected */
219 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
220 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
221 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
222 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
223 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
224 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
225 /* Internal reference clock is selected */
226 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
227 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
228 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
229 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
230 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
231 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
232 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
233 /* External reference clock is selected */
234 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
235 case 0x00U:
236 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
237 break;
238 case 0x01U:
239 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
240 break;
241 case 0x02U:
242 default:
243 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
244 break;
245 }
246 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
247 /* Reserved value */
248 return;
249 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
250 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
251 }
252