1 /*!
2 * @file system_apm32f10x.c
3 *
4 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
5 *
6 * @version V1.0.4
7 *
8 * @date 2022-12-01
9 *
10 * @attention
11 *
12 * Copyright (C) 2020-2022 Geehy Semiconductor
13 *
14 * You may not use this file except in compliance with the
15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16 *
17 * The program is only for reference, which is distributed in the hope
18 * that it will be useful and instructional for customers to develop
19 * their software. Unless required by applicable law or agreed to in
20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23 * and limitations under the License.
24 */
25
26 /*Includes*/
27 #include "apm32f10x.h"
28
29 /** @addtogroup CMSIS
30 @{
31 */
32
33 /** @addtogroup APM32F10x_System
34 * @brief APM32F10x system configuration
35 @{
36 */
37
38 /** @defgroup System_Macros
39 @{
40 */
41
42 //#define SYSTEM_CLOCK_HSE HSE_VALUE
43 //#define SYSTEM_CLOCK_24MHz (24000000)
44 //#define SYSTEM_CLOCK_36MHz (36000000)
45 //#define SYSTEM_CLOCK_48MHz (48000000)
46 //#define SYSTEM_CLOCK_56MHz (56000000)
47 #define SYSTEM_CLOCK_72MHz (72000000)
48 //#define SYSTEM_CLOCK_96MHz (96000000)
49
50 /* #define VECT_TAB_SRAM */
51 #define VECT_TAB_OFFSET 0x00
52
53 /**@} end of group System_Macros*/
54
55 /** @defgroup System_Variables
56 @{
57 */
58
59 #ifdef SYSTEM_CLOCK_HSE
60 uint32_t SystemCoreClock = SYSTEM_CLOCK_HSE;
61 #elif defined SYSTEM_CLOCK_24MHz
62 uint32_t SystemCoreClock = SYSTEM_CLOCK_24MHz;
63 #elif defined SYSTEM_CLOCK_36MHz
64 uint32_t SystemCoreClock = SYSTEM_CLOCK_36MHz;
65 #elif defined SYSTEM_CLOCK_48MHz
66 uint32_t SystemCoreClock = SYSTEM_CLOCK_48MHz;
67 #elif defined SYSTEM_CLOCK_56MHz
68 uint32_t SystemCoreClock = SYSTEM_CLOCK_56MHz;
69 #elif defined SYSTEM_CLOCK_72MHz
70 uint32_t SystemCoreClock = SYSTEM_CLOCK_72MHz;
71 #else
72 uint32_t SystemCoreClock = SYSTEM_CLOCK_96MHz;
73 #endif
74
75 /**@} end of group System_Variables */
76
77 /** @defgroup System_Functions
78 @{
79 */
80
81 static void SystemClockConfig(void);
82
83 #ifdef SYSTEM_CLOCK_HSE
84 static void SystemClockHSE(void);
85 #elif defined SYSTEM_CLOCK_24MHz
86 static void SystemClock24M(void);
87 #elif defined SYSTEM_CLOCK_36MHz
88 static void SystemClock36M(void);
89 #elif defined SYSTEM_CLOCK_48MHz
90 static void SystemClock48M(void);
91 #elif defined SYSTEM_CLOCK_56MHz
92 static void SystemClock56M(void);
93 #elif defined SYSTEM_CLOCK_72MHz
94 static void SystemClock72M(void);
95 #elif defined SYSTEM_CLOCK_96MHz
96 static void SystemClock96M(void);
97 #endif
98
99 /*!
100 * @brief Setup the microcontroller system
101 *
102 * @param None
103 *
104 * @retval None
105 *
106 */
SystemInit(void)107 void SystemInit(void)
108 {
109 /* Set HSIEN bit */
110 RCM->CTRL_B.HSIEN = BIT_SET;
111
112 #ifdef APM32F10X_CL
113 RCM->CFG &= (uint32_t) 0xF0FF0000;
114 #else
115 /* Reset SCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */
116 RCM->CFG &= (uint32_t) 0xF8FF0000;
117 #endif /* APM32F10X_CL */
118
119 /* Reset HSEEN, CSSEN and PLLEN bits */
120 RCM->CTRL &= (uint32_t) 0xFEF6FFFF;
121 /* Reset HSEBCFG bit */
122 RCM->CTRL_B.HSEBCFG = BIT_RESET;
123 /* Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */
124 RCM->CFG &= (uint32_t) 0xFF80FFFF;
125
126 #ifdef APM32F10X_CL
127 /* Reset PLL2ON and PLL3ON bits */
128 RCM->CTRL &= (uint32_t) 0xEBFFFFFF;
129 /* Disable all interrupts and clear pending bits */
130 RCM->INT = 0x00FF0000;
131 /* Reset CFG2 register */
132 RCM->CFG2 = 0x00000000;
133 #else
134 /* Disable all interrupts and clear pending bits */
135 RCM->INT = 0x009F0000;
136 #endif /* APM32F10X_CL */
137
138 SystemClockConfig();
139
140 #ifdef VECT_TAB_SRAM
141 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET;
142 #else
143 SCB->VTOR = FMC_BASE | VECT_TAB_OFFSET;
144 #endif
145 }
146
147 /*!
148 * @brief Update SystemCoreClock variable according to Clock Register Values
149 * The SystemCoreClock variable contains the core clock (HCLK)
150 *
151 * @param None
152 *
153 * @retval None
154 *
155 */
SystemCoreClockUpdate(void)156 void SystemCoreClockUpdate(void)
157 {
158 #ifdef APM32F10X_CL
159 uint32_t sysClock, pllMull, pllSource, pll2Mull, pllPsc1, pllPsc2;
160 #else
161 uint32_t sysClock, pllMull, pllSource;
162 #endif
163
164 /* get sys clock */
165 sysClock = RCM->CFG_B.SCLKSEL;
166
167 switch (sysClock)
168 {
169 /* sys clock is HSI */
170 case 0:
171 sysClock = HSI_VALUE;
172 break;
173
174 /* sys clock is HSE */
175 case 1:
176 sysClock = HSE_VALUE;
177 break;
178
179 /* sys clock is PLL */
180 case 2:
181 #ifdef APM32F10X_CL
182 /* NOTE : PLL is the same as PLL1 */
183 pllSource = RCM->CFG_B.PLL1SRCSEL;
184
185 /* PLL entry clock source is HSE */
186 if (pllSource)
187 {
188 /* PLLPSC1 prescaler factor */
189 pllPsc1 = (RCM->CFG2_B.PLLPSC1 + 1);
190
191 /* PLL entry clock source is PLL2 */
192 if (RCM->CFG2_B.PLLPSC1SRC)
193 {
194 pll2Mull = (RCM->CFG2_B.PLL2MUL != 15) ? (RCM->CFG2_B.PLL2MUL + 2) : 20;
195 pllPsc2 = RCM->CFG2_B.PLLPSC2 + 1;
196
197 pllSource = ((HSE_VALUE / pllPsc2) * pll2Mull) / pllPsc1;
198 }
199 /* PLL entry clock source is HSE */
200 else
201 {
202 pllSource = HSE_VALUE / pllPsc1;
203 }
204 }
205 /* PLL entry clock source is HSI/2 */
206 else
207 {
208 pllSource = HSI_VALUE >> 1;
209 }
210
211 pllMull = RCM->CFG_B.PLL1MULCFG;
212 if (pllMull == 13)
213 {
214 /* For 6.5 multiplication factor */
215 sysClock = pllSource * pllMull / 2;
216 }
217 else
218 {
219 sysClock = pllSource * (pllMull + 2);
220 }
221 #else
222 pllMull = RCM->CFG_B.PLL1MULCFG + 2;
223 pllSource = RCM->CFG_B.PLL1SRCSEL;
224
225 /* PLL entry clock source is HSE */
226 if (pllSource == BIT_SET)
227 {
228 sysClock = HSE_VALUE * pllMull;
229
230 /* HSE clock divided by 2 */
231 if (pllSource == RCM->CFG_B.PLLHSEPSC)
232 {
233 sysClock >>= 1;
234 }
235 }
236 /* PLL entry clock source is HSI/2 */
237 else
238 {
239 sysClock = (HSI_VALUE >> 1) * pllMull;
240 }
241 #endif
242 break;
243
244 default:
245 sysClock = HSI_VALUE;
246 break;
247 }
248
249 SystemCoreClock = sysClock;
250 }
251
252 /*!
253 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers
254 *
255 * @param None
256 *
257 * @retval None
258 *
259 */
SystemClockConfig(void)260 static void SystemClockConfig(void)
261 {
262 #ifdef SYSTEM_CLOCK_HSE
263 SystemClockHSE();
264 #elif defined SYSTEM_CLOCK_24MHz
265 SystemClock24M();
266 #elif defined SYSTEM_CLOCK_36MHz
267 SystemClock36M();
268 #elif defined SYSTEM_CLOCK_48MHz
269 SystemClock48M();
270 #elif defined SYSTEM_CLOCK_56MHz
271 SystemClock56M();
272 #elif defined SYSTEM_CLOCK_72MHz
273 SystemClock72M();
274 #elif defined SYSTEM_CLOCK_96MHz
275 SystemClock96M();
276 #endif
277 }
278
279 #if defined SYSTEM_CLOCK_HSE
280 /*!
281 * @brief Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers
282 *
283 * @param None
284 *
285 * @retval None
286 *
287 */
SystemClockHSE(void)288 static void SystemClockHSE(void)
289 {
290 __IO uint32_t i;
291
292 RCM->CTRL_B.HSEEN = BIT_SET;
293
294 for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
295 {
296 if (RCM->CTRL_B.HSERDYFLG)
297 {
298 break;
299 }
300 }
301
302 if (RCM->CTRL_B.HSERDYFLG)
303 {
304 /* Enable Prefetch Buffer */
305 FMC->CTRL1_B.PBEN = BIT_SET;
306
307 #ifdef APM32F10X_CL
308
309 if (HSE_VALUE <= 24000000)
310 {
311 /* Flash 0 wait state */
312 FMC->CTRL1_B.WS = 0;
313 }
314 else
315 {
316 /* Flash 1 wait state */
317 FMC->CTRL1_B.WS = 1;
318 }
319
320 #else
321 /* Flash 0 wait state */
322 FMC->CTRL1_B.WS = 0;
323 #endif /* APM32F10X_CL */
324
325 /* HCLK = SYSCLK */
326 RCM->CFG_B.AHBPSC = 0X00;
327 /* PCLK2 = HCLK */
328 RCM->CFG_B.APB2PSC = 0;
329 /* PCLK1 = HCLK */
330 RCM->CFG_B.APB1PSC = 0;
331
332 /* Select HSE as system clock source */
333 RCM->CFG_B.SCLKSEL = 1;
334
335 /* Wait till HSE is used as system clock source */
336 while (RCM->CFG_B.SCLKSELSTS != 0x01);
337 }
338 }
339
340 #elif defined SYSTEM_CLOCK_24MHz
341 /*!
342 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers
343 *
344 * @param None
345 *
346 * @retval None
347 *
348 */
SystemClock24M(void)349 static void SystemClock24M(void)
350 {
351 __IO uint32_t i;
352
353 RCM->CTRL_B.HSEEN = BIT_SET;
354
355 for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
356 {
357 if (RCM->CTRL_B.HSERDYFLG)
358 {
359 break;
360 }
361 }
362
363 if (RCM->CTRL_B.HSERDYFLG)
364 {
365 /* Enable Prefetch Buffer */
366 FMC->CTRL1_B.PBEN = BIT_SET;
367 /* Flash 0 wait state */
368 FMC->CTRL1_B.WS = 0;
369
370 /* HCLK = SYSCLK */
371 RCM->CFG_B.AHBPSC = 0X00;
372 /* PCLK2 = HCLK */
373 RCM->CFG_B.APB2PSC = 0;
374 /* PCLK1 = HCLK */
375 RCM->CFG_B.APB1PSC = 0;
376
377 #ifdef APM32F10X_CL
378 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */
379 /* PLL configuration: PLLCLK = (PLL2 / 10) * 6 = 24 MHz */
380
381 RCM->CFG2_B.PLLPSC2 = 4;
382 RCM->CFG2_B.PLL2MUL = 0x06;
383
384 RCM->CFG2_B.PLLPSC1SRC = 1;
385 RCM->CFG2_B.PLLPSC1 = 9;
386
387 /* Enable PLL2 */
388 RCM->CTRL_B.PLL2EN = 1;
389 /* Wait till PLL2 is ready */
390 while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET);
391
392 RCM->CFG_B.PLL1SRCSEL = 1;
393 RCM->CFG_B.PLL1MULCFG = 4;
394 #else
395 /* PLL configuration: PLLCLK = (HSE / 2) * 6 = 24 MHz */
396 /* PLL: (HSE / 2) * 6 */
397 RCM->CFG_B.PLL1SRCSEL = 1;
398 RCM->CFG_B.PLLHSEPSC = 1;
399 RCM->CFG_B.PLL1MULCFG = 4;
400 #endif /* APM32F10X_CL */
401
402 /* Enable PLL */
403 RCM->CTRL_B.PLL1EN = 1;
404
405 /* Wait PLL Ready */
406 while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET);
407
408 /* Select PLL as system clock source */
409 RCM->CFG_B.SCLKSEL = 2;
410
411 /* Wait till PLL is used as system clock source */
412 while (RCM->CFG_B.SCLKSELSTS != 0x02);
413 }
414 }
415
416 #elif defined SYSTEM_CLOCK_36MHz
417 /*!
418 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 and PCLK1 prescalers
419 *
420 * @param None
421 *
422 * @retval None
423 *
424 */
SystemClock36M(void)425 static void SystemClock36M(void)
426 {
427 __IO uint32_t i;
428
429 RCM->CTRL_B.HSEEN = BIT_SET;
430
431 for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
432 {
433 if (RCM->CTRL_B.HSERDYFLG)
434 {
435 break;
436 }
437 }
438
439 if (RCM->CTRL_B.HSERDYFLG)
440 {
441 /* Enable Prefetch Buffer */
442 FMC->CTRL1_B.PBEN = BIT_SET;
443 /* Flash 1 wait state */
444 FMC->CTRL1_B.WS = 1;
445
446 /* HCLK = SYSCLK */
447 RCM->CFG_B.AHBPSC = 0X00;
448 /* PCLK2 = HCLK */
449 RCM->CFG_B.APB2PSC = 0;
450 /* PCLK1 = HCLK */
451 RCM->CFG_B.APB1PSC = 0;
452
453 #ifdef APM32F10X_CL
454 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */
455 /* PLL configuration: PLLCLK = (PLL2 / 10) * 9 = 36 MHz */
456
457 RCM->CFG2_B.PLLPSC2 = 4;
458 RCM->CFG2_B.PLL2MUL = 0x06;
459
460 RCM->CFG2_B.PLLPSC1SRC = 1;
461 RCM->CFG2_B.PLLPSC1 = 9;
462
463 /* Enable PLL2 */
464 RCM->CTRL_B.PLL2EN = 1;
465 /* Wait till PLL2 is ready */
466 while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET);
467
468 RCM->CFG_B.PLL1SRCSEL = 1;
469 RCM->CFG_B.PLL1MULCFG = 7;
470 #else
471 /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
472 /* PLL: (HSE / 2) * 9 */
473 RCM->CFG_B.PLL1SRCSEL = 1;
474 RCM->CFG_B.PLLHSEPSC = 1;
475 RCM->CFG_B.PLL1MULCFG = 7;
476 #endif
477
478 /* Enable PLL */
479 RCM->CTRL_B.PLL1EN = 1;
480
481 /* Wait PLL Ready */
482 while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET);
483
484 /* Select PLL as system clock source */
485 RCM->CFG_B.SCLKSEL = 2;
486
487 /* Wait till PLL is used as system clock source */
488 while (RCM->CFG_B.SCLKSELSTS != 0x02);
489 }
490 }
491
492 #elif defined SYSTEM_CLOCK_48MHz
493 /*!
494 * @brief Sets System clock frequency to 46MHz and configure HCLK, PCLK2 and PCLK1 prescalers
495 *
496 * @param None
497 *
498 * @retval None
499 *
500 */
SystemClock48M(void)501 static void SystemClock48M(void)
502 {
503 __IO uint32_t i;
504
505 RCM->CTRL_B.HSEEN = BIT_SET;
506
507 for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
508 {
509 if (RCM->CTRL_B.HSERDYFLG)
510 {
511 break;
512 }
513 }
514
515 if (RCM->CTRL_B.HSERDYFLG)
516 {
517 /* Enable Prefetch Buffer */
518 FMC->CTRL1_B.PBEN = BIT_SET;
519 /* Flash 1 wait state */
520 FMC->CTRL1_B.WS = 1;
521
522 /* HCLK = SYSCLK */
523 RCM->CFG_B.AHBPSC = 0X00;
524 /* PCLK2 = HCLK */
525 RCM->CFG_B.APB2PSC = 0;
526 /* PCLK1 = HCLK / 2 */
527 RCM->CFG_B.APB1PSC = 4;
528
529 #ifdef APM32F10X_CL
530 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */
531 /* PLL configuration: PLLCLK = (PLL2 / 5) * 6 = 48 MHz */
532
533 RCM->CFG2_B.PLLPSC2 = 4;
534 RCM->CFG2_B.PLL2MUL = 0x06;
535
536 RCM->CFG2_B.PLLPSC1SRC = 1;
537 RCM->CFG2_B.PLLPSC1 = 0x4;
538
539 /* Enable PLL2 */
540 RCM->CTRL_B.PLL2EN = 1;
541 /* Wait till PLL2 is ready */
542 while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET);
543
544 RCM->CFG_B.PLL1SRCSEL = 1;
545 RCM->CFG_B.PLL1MULCFG = 4;
546 #else
547 /* PLL: HSE * 6 */
548 RCM->CFG_B.PLL1SRCSEL = 1;
549 RCM->CFG_B.PLL1MULCFG = 4;
550 #endif
551
552 /* Enable PLL */
553 RCM->CTRL_B.PLL1EN = 1;
554
555 /* Wait PLL Ready */
556 while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET);
557
558 /* Select PLL as system clock source */
559 RCM->CFG_B.SCLKSEL = 2;
560
561 /* Wait till PLL is used as system clock source */
562 while (RCM->CFG_B.SCLKSELSTS != 0x02);
563 }
564 }
565
566 #elif defined SYSTEM_CLOCK_56MHz
567 /*!
568 * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers
569 *
570 * @param None
571 *
572 * @retval None
573 *
574 */
SystemClock56M(void)575 static void SystemClock56M(void)
576 {
577 __IO uint32_t i;
578
579 RCM->CTRL_B.HSEEN = BIT_SET;
580
581 for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
582 {
583 if (RCM->CTRL_B.HSERDYFLG)
584 {
585 break;
586 }
587 }
588
589 if (RCM->CTRL_B.HSERDYFLG)
590 {
591 /* Enable Prefetch Buffer */
592 FMC->CTRL1_B.PBEN = BIT_SET;
593 /* Flash 2 wait state */
594 FMC->CTRL1_B.WS = 2;
595
596 /* HCLK = SYSCLK */
597 RCM->CFG_B.AHBPSC = 0X00;
598 /* PCLK2 = HCLK */
599 RCM->CFG_B.APB2PSC = 0;
600 /* PCLK1 = HCLK / 2 */
601 RCM->CFG_B.APB1PSC = 4;
602
603 #ifdef APM32F10X_CL
604 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */
605 /* PLL configuration: PLLCLK = (PLL2 / 5) * 7 = 56 MHz */
606
607 RCM->CFG2_B.PLLPSC2 = 4;
608 RCM->CFG2_B.PLL2MUL = 0x06;
609
610 RCM->CFG2_B.PLLPSC1SRC = 1;
611 RCM->CFG2_B.PLLPSC1 = 0x4;
612
613 /* Enable PLL2 */
614 RCM->CTRL_B.PLL2EN = 1;
615 /* Wait till PLL2 is ready */
616 while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET);
617
618 RCM->CFG_B.PLL1SRCSEL = 1;
619 RCM->CFG_B.PLL1MULCFG = 5;
620 #else
621 /* PLL: HSE * 7 */
622 RCM->CFG_B.PLL1SRCSEL = 1;
623 RCM->CFG_B.PLL1MULCFG = 5;
624 #endif
625
626 /* Enable PLL */
627 RCM->CTRL_B.PLL1EN = 1;
628
629 /* Wait PLL Ready */
630 while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET);
631
632 /* Select PLL as system clock source */
633 RCM->CFG_B.SCLKSEL = 2;
634
635 /* Wait till PLL is used as system clock source */
636 while (RCM->CFG_B.SCLKSELSTS != 0x02);
637 }
638 }
639
640 #elif defined SYSTEM_CLOCK_72MHz
641 /*!
642 * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers
643 *
644 * @param None
645 *
646 * @retval None
647 *
648 */
SystemClock72M(void)649 static void SystemClock72M(void)
650 {
651 __IO uint32_t i;
652
653 RCM->CTRL_B.HSEEN = BIT_SET;
654
655 for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
656 {
657 if (RCM->CTRL_B.HSERDYFLG)
658 {
659 break;
660 }
661 }
662
663 if (RCM->CTRL_B.HSERDYFLG)
664 {
665 /* Enable Prefetch Buffer */
666 FMC->CTRL1_B.PBEN = BIT_SET;
667 /* Flash 2 wait state */
668 FMC->CTRL1_B.WS = 2;
669
670 /* HCLK = SYSCLK */
671 RCM->CFG_B.AHBPSC = 0X00;
672 /* PCLK2 = HCLK */
673 RCM->CFG_B.APB2PSC = 0;
674 /* PCLK1 = HCLK / 2 */
675 RCM->CFG_B.APB1PSC = 4;
676
677 #ifdef APM32F10X_CL
678 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */
679 /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */
680
681 RCM->CFG2_B.PLLPSC2 = 4;
682 RCM->CFG2_B.PLL2MUL = 0x06;
683
684 RCM->CFG2_B.PLLPSC1SRC = 1;
685 RCM->CFG2_B.PLLPSC1 = 0x4;
686
687 /* Enable PLL2 */
688 RCM->CTRL_B.PLL2EN = 1;
689 /* Wait till PLL2 is ready */
690 while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET);
691
692 RCM->CFG_B.PLL1SRCSEL = 1;
693 RCM->CFG_B.PLL1MULCFG = 7;
694 #else
695 /* PLL: HSE * 9 */
696 RCM->CFG_B.PLL1SRCSEL = 1;
697 RCM->CFG_B.PLL1MULCFG = 7;
698 #endif
699
700 /* Enable PLL */
701 RCM->CTRL_B.PLL1EN = 1;
702
703 /* Wait PLL Ready */
704 while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET);
705
706 /* Select PLL as system clock source */
707 RCM->CFG_B.SCLKSEL = 2;
708
709 /* Wait till PLL is used as system clock source */
710 while (RCM->CFG_B.SCLKSELSTS != 0x02);
711 }
712
713 }
714
715 #elif defined SYSTEM_CLOCK_96MHz
716 /*!
717 * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers
718 *
719 * @param None
720 *
721 * @retval None
722 *
723 */
SystemClock96M(void)724 static void SystemClock96M(void)
725 {
726 __IO uint32_t i;
727
728 RCM->CTRL_B.HSEEN = BIT_SET;
729
730 for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
731 {
732 if (RCM->CTRL_B.HSERDYFLG)
733 {
734 break;
735 }
736 }
737
738 if (RCM->CTRL_B.HSERDYFLG)
739 {
740 /* Enable Prefetch Buffer */
741 FMC->CTRL1_B.PBEN = BIT_SET;
742 /* Flash 3 wait state */
743 FMC->CTRL1_B.WS = 3;
744
745 /* HCLK = SYSCLK */
746 RCM->CFG_B.AHBPSC = 0X00;
747 /* PCLK2 = HCLK */
748 RCM->CFG_B.APB2PSC = 0;
749 /* PCLK1 = HCLK / 2 */
750 RCM->CFG_B.APB1PSC = 4;
751
752 #ifdef APM32F10X_CL
753 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 12 = 60 MHz (HSE is 25MHz for APM32F10X_CL) */
754 /* PLL configuration: PLLCLK = (PLL2 / 5) * 8 = 96 MHz */
755
756 RCM->CFG2_B.PLLPSC2 = 4;
757 RCM->CFG2_B.PLL2MUL = 10;
758
759 RCM->CFG2_B.PLLPSC1SRC = 1;
760 RCM->CFG2_B.PLLPSC1 = 4;
761
762 /* Enable PLL2 */
763 RCM->CTRL_B.PLL2EN = 1;
764 /* Wait till PLL2 is ready */
765 while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET);
766
767 RCM->CFG_B.PLL1SRCSEL = 1;
768 RCM->CFG_B.PLL1MULCFG = 6;
769 #else
770 /* PLL: HSE * 12 */
771 RCM->CFG_B.PLL1SRCSEL = 1;
772 RCM->CFG_B.PLL1MULCFG = 10;
773 #endif
774
775 /* Enable PLL */
776 RCM->CTRL_B.PLL1EN = 1;
777
778 /* Wait PLL Ready */
779 while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET);
780
781 /* Select PLL as system clock source */
782 RCM->CFG_B.SCLKSEL = 2;
783
784 /* Wait till PLL is used as system clock source */
785 while (RCM->CFG_B.SCLKSELSTS != 0x02);
786 }
787 }
788 #endif
789
790 /**@} end of group System_Functions */
791 /**@} end of group APM32F10x_System */
792 /**@} end of group CMSIS */
793