1 /**************************************************************************//**
2 * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f0006.c
3 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
4 * for the Holtek HT32F5xxxx Device Series
5 * @version $Rev:: 6597 $
6 * @date $Date:: 2022-12-27 #$
7 *
8 * @note
9 * Copyright (C) Holtek Semiconductor Inc. All rights reserved.
10 *
11 * @par
12 * ARM Limited (ARM) supplies this software for Cortex-M processor-based
13 * microcontrollers. This file can be freely distributed within development
14 * tools that are supporting such ARM based processors.
15 *
16 * @par
17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22 *
23 ******************************************************************************/
24
25 // Supported Device
26 // ========================================
27 // HT32F0006
28 // HT32F61352
29
30 //#define USE_HT32F0006
31 //#define USE_HT32F61352
32
33 /** @addtogroup CMSIS
34 * @{
35 */
36
37 /** @addtogroup HT32F5xxxx_system HT32F5xxxx System
38 * @{
39 */
40
41
42 #include "ht32f5xxxx_01.h"
43
44 /** @addtogroup HT32F5xxxx_System_Private_Defines
45 * @{
46 */
47 /*
48 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
49 */
50
51 /*--------------------- Clock Configuration ----------------------------------
52 //
53 // <q1> Enable High Speed External Crystal Oscillator (HSE)
54 // <i> Default HSE = DISABLE
55 //
56 // <q3> Enable Low Speed External Crystal Oscillator (LSE)
57 // <i> Default LSE = DISABLE
58 //
59 // <e4> Enable PLL
60 // <i> Default PLL = DISABLE
61 // <o5> PLL Clock Source
62 // <0=> CK_HSE
63 // <1=> CK_HSI
64 // <i> Default PLL clock source = CK_HSI
65 // <i> PLL source clock must be in the range of 4 MHz to 16 MHz
66 // <o6> PLL Feedback Clock Divider (NF2): 1 ~ 16
67 // <1-16:1>
68 // <i> PLL feedback clock = PLL clock source x NF2
69 // <i> PLL feedback clock must be in the range of 24 MHz to 48 MHz
70 // <o7> PLL Output Clock Divider (NO2)
71 // <0=> 1
72 // <1=> 2
73 // <2=> 4
74 // <3=> 8
75 // <i> PLL output clock = PLL feedback clock / NO2
76 // <i> PLL output clock must be in the range of 4 MHz to 48 MHz
77 // </e>
78 //
79 // <h> SystemCoreClock Configuration (CK_AHB)
80 // <o8> SystemCoreClock Source
81 // <1=> CK_PLL
82 // <2=> CK_HSE
83 // <3=> CK_HSI
84 // <6=> CK_LSE
85 // <7=> CK_LSI
86 // <i> Default SystemCoreClock source = CK_HSI
87 // <o9> SystemCoreClock Source Divider
88 // <0=> 1
89 // <1=> 2
90 // <2=> 4
91 // <3=> 8
92 // <4=> 16
93 // <5=> 32
94 // <i> Default SystemCoreClock source divider = 1
95 // </h>
96 //
97 // <h> FLASH Configuration
98 // <o10> Wait state
99 // <0=> 0 WS
100 // <1=> 1 WS
101 // <9=> AUTO
102 // <i> 0 WS: 1 kHz <= CK_AHB <= 24 MHz
103 // <i> 1 WS: 24 MHz < CK_AHB <= 48 MHz
104 // <q11> Pre-fetch Buffer Enable
105 // <i> Default pre-fetch buffer = ENABLE
106 // <q12> Branch cache Enable
107 // <i> Default branch cache = ENABLE
108 // </h>
109 */
110
111 /* !!! NOTICE !!!
112 HSI must keep turn on when doing the Flash operation (Erase/Program).
113 */
114
115 /* !!! NOTICE !!!
116 * How to adjust the value of High Speed External oscillator (HSE)?
117 The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h".
118 If your board uses a different HSE speed, please add a new compiler preprocessor
119 C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE,
120 or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file.
121 Take Keil MDK-ARM for instance, to set HSE as 16 MHz:
122 "Option of Taret -> C/C++ > Preprocessor Symbols"
123 Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000
124 ^^ Add "HSE_VALUE"
125 define as above.
126 */
127 #define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */
128 #define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */
129 #define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */
130 #define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */
131 #define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */
132 #define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */
133 #define PLL_NF2_DIV (4) /*!< 1~16: DIV1~DIV16 */
134 #define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */
135 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */
136 #define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */
137 #define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 9: WS = AUTO */
138 #define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */
139 #define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */
140 #define DEINIT_ENABLE (1) /* Set 0 for reduce code size */
141
142 /*----------------------------------------------------------------------------------------------------------*/
143 /* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */
144 /*----------------------------------------------------------------------------------------------------------*/
145
146
147 /*--------------------- WDT Configuration ----------------------------------
148 //
149 // <e0> Enable WDT Configuration
150 // <o1> WDT Prescaler Selection
151 // <0=> CK_WDT / 1
152 // <1=> CK_WDT / 2
153 // <2=> CK_WDT / 4
154 // <3=> CK_WDT / 8
155 // <4=> CK_WDT / 16
156 // <5=> CK_WDT / 32
157 // <6=> CK_WDT / 64
158 // <7=> CK_WDT / 128
159 // <o2> WDT Reload Value <1-4095:1>
160 // <q3> Enable WDT Reset function
161 // <o4> WDT Sleep Halt mode
162 // <0=> No halt
163 // <1=> Halt in DeepSleep1
164 // <2=> Halt in Sleep & DeepSleep1
165 // </e>
166 */
167 #define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */
168 #define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */
169 #define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */
170 #define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */
171 #define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */
172
173 /**
174 * @brief Check HSI frequency
175 */
176 #if (HSI_VALUE != 8000000UL)
177 #error "CK_HSI clock issue: must be 8 MHz!"
178 #endif
179
180 /**
181 * @brief Check HSE frequency
182 */
183 #if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL))
184 #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!"
185 #endif
186
187 /**
188 * @brief Check LSI frequency
189 */
190 #if (LSI_VALUE != 32000UL)
191 #error "CK_LSI clock issue: must be 32 kHz!"
192 #endif
193
194 /**
195 * @brief Check LSE frequency
196 */
197 #if (LSE_VALUE != 32768UL)
198 #error "CK_LSE clock issue: must be 32.768 kHz!"
199 #endif
200
201 /**
202 * @brief CK_PLL definition
203 */
204 #if (PLL_ENABLE == 1)
205 /* Get CK_VCO frequency */
206 #if (PLL_CLK_SRC == 1)
207 #if (HSI_ENABLE == 0)
208 #error "CK_PLL clock source issue: HSI has not been enabled"
209 #else
210 #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */
211 #endif
212 #else
213 #if (HSE_ENABLE == 0)
214 #error "CK_PLL clock source issue: HSE has not been enabled!"
215 #else
216 #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */
217 #endif
218 #endif
219
220 #define VCO_MIN 24000000UL
221 #define VCO_MAX 48000000UL
222 #define PLL_MIN 4000000UL
223 #define PLL_MAX 48000000UL
224
225 /* Check CK_VCO frequency */
226 #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX))
227 #error "CK_VCO clock issue: must be in the range!"
228 #endif
229
230 #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */
231
232 /* Check CK_PLL frequency */
233 #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX))
234 #error "CK_PLL clock issue: must be in the range!"
235 #endif
236 #endif
237
238 /**
239 * @brief CK_SYS definition
240 */
241 #if (HCLK_SRC == 1)
242 #if (PLL_ENABLE == 1)
243 #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */
244 #else
245 #error "CK_SYS clock source issue: PLL is not enable!"
246 #endif
247 #elif (HCLK_SRC == 2)
248 #if (HSE_ENABLE == 1)
249 #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */
250 #else
251 #error "CK_SYS clock source issue: HSE is not enable!"
252 #endif
253 #elif (HCLK_SRC == 3)
254 #if (HSI_ENABLE == 1)
255 #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */
256 #else
257 #error "CK_SYS clock source issue: HSI is not enable!"
258 #endif
259 #elif (HCLK_SRC == 6)
260 #if (LSE_ENABLE == 1)
261 #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */
262 #else
263 #error "CK_SYS clock source issue: LSE is not enable!"
264 #endif
265 #elif (HCLK_SRC == 7)
266 #if (LSI_ENABLE == 1)
267 #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */
268 #else
269 #error "CK_SYS clock source issue: LSI is not enable!"
270 #endif
271 #else
272 #error "CK_SYS clock source issue: No clock source is selected!"
273 #endif
274
275 /**
276 * @brief CK_AHB definition
277 */
278 #define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */
279
280 #define CKAHB_MIN 1000UL
281 #define CKAHB_MAX 48000000UL
282 #define WS0_CLK 24000000UL
283
284 /* Check CK_AHB frequency */
285 #if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX))
286 #error "CK_AHB clock issue: must be in the range!"
287 #endif
288
289 /* Check FLASH wait-state setting */
290 #if ((__CK_AHB > WS0_CLK) && (WAIT_STATE < 1))
291 #error "FLASH wait state configuration issue!"
292 #endif
293 /**
294 * @}
295 */
296
297 /** @addtogroup HT32F5xxxx_System_Private_Variables
298 * @{
299 */
300 __IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */
301 /**
302 * @}
303 */
304
305 /** @addtogroup HT32F5xxxx_System_Private_Functions
306 * @{
307 */
308
309 /**
310 * @brief Setup the microcontroller system.
311 * Initializes the system clocks and the embedded Flash.
312 * @note This function should be used after reset.
313 * @retval None
314 */
SystemInit(void)315 void SystemInit(void)
316 {
317 #if (WDT_ENABLE == 1)
318 HT_CKCU->APBCCR1 |= (0x1 << 4);
319 HT_WDT->PR = 0x35CA;
320 HT_WDT->MR0 = 0;
321 HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12));
322 HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16);
323 HT_WDT->CR = 0x5FA00001;
324 #else
325 #if (DEINIT_ENABLE == 1)
326 HT_RSTCU->APBPRST1 = (1 << 4);
327 #endif
328 #endif
329
330 HT_CKCU->LPCR = 1; /* configure Backup domain isolation */
331 SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */
332 while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */
333
334 #if (DEINIT_ENABLE == 1)
335 /* De-init the setting */
336 HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */
337 SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */
338 while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */
339 HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */
340 while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */
341 HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */
342 HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */
343 ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */
344 SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */
345 #endif
346
347 /* HSE initiation */
348 #if (HSE_ENABLE == 1)
349 SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */
350 while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */
351 #endif
352
353 /* LSE initiation */
354 #if (LSE_ENABLE == 1)
355 do {
356 SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */
357 } while (!GetBit_BB((u32)(&HT_RTC->CR), 3));
358 while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */
359 #endif
360
361 ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */
362
363 /* LSI initiation */
364 #if (HCLK_SRC == 7)
365 while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */
366 #endif
367
368 /* PLL initiation */
369 #if (PLL_ENABLE == 1)
370 #if (PLL_CLK_SRC == 0)
371 ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */
372 #else
373 SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */
374 #endif
375 HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */
376 SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */
377 while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */
378 #endif
379
380 /* CK_AHB initiation */
381 #if (WAIT_STATE == 9)
382 #if (__CK_AHB > WS0_CLK)
383 HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */
384 #endif
385 #else
386 HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */
387 #endif
388
389 HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */
390 HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */
391 while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */
392
393 /* Pre-fetch buffer configuration */
394 #if (PRE_FETCH_ENABLE == 0)
395 ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */
396 #else
397 SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */
398 #endif
399
400 /* Branch cache configuration */
401 #if (BCACHE_ENABLE == 0)
402 ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */
403 #else
404 SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */
405 #endif
406
407 /* HSE power down */
408 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1)))
409 ResetBit_BB((u32)(&HT_CKCU->GCCR), 10);
410 #endif
411
412 /* HSI power down */
413 #if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0)))
414 ResetBit_BB((u32)(&HT_CKCU->GCCR), 11);
415 #endif
416 }
417
418 /**
419 * @brief Update SystemCoreClock
420 * @retval None
421 */
SystemCoreClockUpdate(void)422 void SystemCoreClockUpdate(void)
423 {
424 u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL;
425 u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23);
426 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL;
427 u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL;
428
429 /* Get system core clock according to global clock control & configuration registers */
430 if (SystemCoreClockSrc == 1)
431 {
432 if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31))
433 {
434 PllFeedbackClockDiv = 1;
435 PllOutputClockDiv = 0;
436 }
437
438 if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8))
439 {
440 SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv;
441 }
442 else
443 {
444 SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv;
445 }
446 }
447 else if (SystemCoreClockSrc == 2)
448 {
449 SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv;
450 }
451 else if (SystemCoreClockSrc == 3)
452 {
453 SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv;
454 }
455 else if (SystemCoreClockSrc == 6)
456 {
457 SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv;
458 }
459 else if (SystemCoreClockSrc == 7)
460 {
461 SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv;
462 }
463 }
464
465 /**
466 * @}
467 */
468
469
470 /**
471 * @}
472 */
473
474 /**
475 * @}
476 */
477
478 /******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */
479