1 /**************************************************************************//**
2 * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_08.c
3 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
4 * for the Holtek HT32F5xxxx Device Series
5 * @version $Rev:: 6877 $
6 * @date $Date:: 2023-05-04 #$
7 *
8 * @note
9 * Copyright (C) Holtek Semiconductor Inc. All rights reserved.
10 *
11 * @par
12 * ARM Limited (ARM) supplies this software for Cortex-M processor-based
13 * microcontrollers. This file can be freely distributed within development
14 * tools that are supporting such ARM based processors.
15 *
16 * @par
17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22 *
23 ******************************************************************************/
24
25 // Supported Device
26 // ========================================
27 // HT32F65230, HT32F65240
28 // HT32F65232
29 // MXTX6306
30 // HT50F3200S
31
32 //#define USE_HT32F65230_40
33 //#define USE_HT32F65232
34 //#define USE_MXTX6306
35 //#define USE_HT50F3200S
36
37 /** @addtogroup CMSIS
38 * @{
39 */
40
41 /** @addtogroup HT32F5xxxx_system HT32F5xxxx System
42 * @{
43 */
44
45
46 #include "ht32f5xxxx_01.h"
47
48 /** @addtogroup HT32F5xxxx_System_Private_Defines
49 * @{
50 */
51 /*
52 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
53 */
54
55 /*--------------------- Clock Configuration ----------------------------------
56 //
57 // <q1> Enable High Speed External Crystal Oscillator (HSE)
58 // <i> Default HSE = DISABLE
59 //
60 // <q3> Enable Low Speed External Crystal Oscillator (LSE)
61 // <i> Default LSE = DISABLE
62 // <i> HT32F65230/65240, MXTX6306, HT50F3200S Only
63 //
64 // <e4> Enable PLL
65 // <i> Default PLL = DISABLE
66 // <i> PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2
67 // <o5> PLL Clock Source
68 // <0=> CK_HSE
69 // <1=> CK_HSI
70 // <i> Default PLL clock source = CK_HSI
71 // <i> PLL source clock must be in the range of 4 MHz to 16 MHz
72 // <o6> PLL Clock Source Divider (SRC_DIV)
73 // <0=> 1
74 // <1=> 2
75 // <i> PLL input clock = PLL Clock Source / (SRC_DIV)
76 // <o7> PLL Feedback Clock Divider (NF2): 1 ~ 16
77 // <1-16:1>
78 // <i> PLL feedback clock = PLL input clock x NF2
79 // <i> PLL feedback clock must be in the range of 24 MHz to 60 MHz
80 // <o8> PLL Output Clock Divider (NO2)
81 // <0=> 1
82 // <1=> 2
83 // <2=> 4
84 // <3=> 8
85 // <i> PLL output clock = PLL feedback clock / NO2
86 // <i> PLL output clock must be in the range of 4 MHz to 60 MHz
87 // </e>
88 //
89 // <h> SystemCoreClock Configuration (CK_AHB)
90 // <o9> SystemCoreClock Source
91 // <1=> CK_PLL
92 // <2=> CK_HSE
93 // <3=> CK_HSI
94 // <6=> CK_LSE (HT32F65230/65240, MXTX6306, HT50F3200S Only)
95 // <7=> CK_LSI
96 // <i> Default SystemCoreClock source = CK_HSI
97 // <o10> SystemCoreClock Source Divider
98 // <0=> 1
99 // <1=> 2
100 // <2=> 4
101 // <3=> 8
102 // <4=> 16
103 // <5=> 32
104 // <i> Default SystemCoreClock source divider = 1
105 // </h>
106 //
107 // <h> FLASH Configuration
108 // <o11> Wait state
109 // <0=> 0 WS
110 // <1=> 1 WS
111 // <2=> 2 WS
112 // <9=> AUTO
113 // <i> 0 WS: 1 kHz <= CK_AHB <= 20 MHz
114 // <i> 1 WS: 20 MHz < CK_AHB <= 40 MHz
115 // <i> 2 WS: 40 MHz < CK_AHB <= 60 MHz
116 // <q12> Pre-fetch Buffer Enable
117 // <i> Default pre-fetch buffer = ENABLE
118 // <q13> Branch cache Enable (HT32F52357/67, HT32F65230/40, MXTX6306, HT50F3200S Only)
119 // <i> Default branch cache = ENABLE
120 // </h>
121 */
122
123 /* !!! NOTICE !!!
124 HSI must keep turn on when doing the Flash operation (Erase/Program).
125 */
126
127 /* !!! NOTICE !!!
128 * How to adjust the value of High Speed External oscillator (HSE)?
129 The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h".
130 If your board uses a different HSE speed, please add a new compiler preprocessor
131 C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE,
132 or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file.
133 Take Keil MDK-ARM for instance, to set HSE as 16 MHz:
134 "Option of Taret -> C/C++ > Preprocessor Symbols"
135 Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000
136 ^^ Add "HSE_VALUE"
137 define as above.
138 */
139 #define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */
140 #define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */
141 #define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */
142 #define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */
143 #define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */
144 #define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */
145 #define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */
146 #define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */
147 #define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */
148 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */
149 #define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */
150 #define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */
151 #define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */
152 #define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */
153 #define DEINIT_ENABLE (1) /* Set 0 for reduce code size */
154
155 /*----------------------------------------------------------------------------------------------------------*/
156 /* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */
157 /*----------------------------------------------------------------------------------------------------------*/
158
159
160 /*--------------------- WDT Configuration ----------------------------------
161 //
162 // <e0> Enable WDT Configuration
163 // <o1> WDT Prescaler Selection
164 // <0=> CK_WDT / 1
165 // <1=> CK_WDT / 2
166 // <2=> CK_WDT / 4
167 // <3=> CK_WDT / 8
168 // <4=> CK_WDT / 16
169 // <5=> CK_WDT / 32
170 // <6=> CK_WDT / 64
171 // <7=> CK_WDT / 128
172 // <o2> WDT Reload Value <1-4095:1>
173 // <q3> Enable WDT Reset function
174 // <o4> WDT Sleep Halt mode
175 // <0=> No halt
176 // <1=> Halt in DeepSleep1
177 // <2=> Halt in Sleep & DeepSleep1
178 // </e>
179 */
180 #define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */
181 #define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */
182 #define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */
183 #define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */
184 #define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */
185
186 /**
187 * @brief Check HSI frequency
188 */
189 #if (HSI_VALUE != 8000000UL)
190 #error "CK_HSI clock issue: must be 8 MHz!"
191 #endif
192
193 /**
194 * @brief Check HSE frequency
195 */
196 #if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL))
197 #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!"
198 #endif
199
200 /**
201 * @brief Check LSI frequency
202 */
203 #if (LSI_VALUE != 32000UL)
204 #error "CK_LSI clock issue: must be 32 kHz!"
205 #endif
206
207 /**
208 * @brief Check LSE frequency
209 */
210 #if defined(USE_HT32F65230_40)
211 #if (LSE_VALUE != 32768UL)
212 #error "CK_LSE clock issue: must be 32.768 kHz!"
213 #endif
214 #endif
215 #if defined(USE_HT32F65232)
216 #if (LSE_ENABLE == 1)
217 #error "Dose not support LSE!"
218 #endif
219 #endif
220
221 /**
222 * @brief CK_PLL definition
223 */
224 #if (PLL_ENABLE == 1)
225 /* Get CK_VCO frequency */
226 #if (PLL_CLK_SRC == 1)
227 #if (HSI_ENABLE == 0)
228 #error "CK_PLL clock source issue: HSI has not been enabled"
229 #else
230 #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */
231 #endif
232 #else
233 #if (HSE_ENABLE == 0)
234 #error "CK_PLL clock source issue: HSE has not been enabled!"
235 #else
236 #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */
237 #endif
238 #endif
239
240 #define VCO_MIN 24000000UL
241 #define VCO_MAX 60000000UL
242 #define PLL_MIN 4000000UL
243 #define PLL_MAX 60000000UL
244
245 /* Check CK_VCO frequency */
246 #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX))
247 #error "CK_VCO clock issue: must be in the range!"
248 #endif
249
250 #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */
251
252 /* Check CK_PLL frequency */
253 #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX))
254 #error "CK_PLL clock issue: must be in the range!"
255 #endif
256 #endif
257
258 /**
259 * @brief CK_SYS definition
260 */
261 #if (HCLK_SRC == 1)
262 #if (PLL_ENABLE == 1)
263 #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */
264 #else
265 #error "CK_SYS clock source issue: PLL is not enable!"
266 #endif
267 #elif (HCLK_SRC == 2)
268 #if (HSE_ENABLE == 1)
269 #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */
270 #else
271 #error "CK_SYS clock source issue: HSE is not enable!"
272 #endif
273 #elif (HCLK_SRC == 3)
274 #if (HSI_ENABLE == 1)
275 #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */
276 #else
277 #error "CK_SYS clock source issue: HSI is not enable!"
278 #endif
279 #elif (HCLK_SRC == 6)
280 #if defined(USE_HT32F65230_40)
281 #if (LSE_ENABLE == 1)
282 #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */
283 #else
284 #error "CK_SYS clock source issue: LSE is not enable!"
285 #endif
286 #if defined(USE_HT32F65232)
287 #error "Dose not support LSE!"
288 #endif
289 #endif
290 #elif (HCLK_SRC == 7)
291 #if (LSI_ENABLE == 1)
292 #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */
293 #else
294 #error "CK_SYS clock source issue: LSI is not enable!"
295 #endif
296 #else
297 #error "CK_SYS clock source issue: No clock source is selected!"
298 #endif
299
300 /**
301 * @brief CK_AHB definition
302 */
303 #define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */
304
305 #define CKAHB_MIN 1000UL
306 #define CKAHB_MAX 60000000UL
307 #define WS0_CLK 20000000UL
308 #define WS1_CLK 40000000UL
309
310 /* Check CK_AHB frequency */
311 #if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX))
312 #error "CK_AHB clock issue: must be in the range!"
313 #endif
314
315 /* Check FLASH wait-state setting */
316 #if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \
317 (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1))
318 #error "FLASH wait state configuration issue!"
319 #endif
320 /**
321 * @}
322 */
323
324 /** @addtogroup HT32F5xxxx_System_Private_Variables
325 * @{
326 */
327 __IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */
328 /**
329 * @}
330 */
331
332 /** @addtogroup HT32F5xxxx_System_Private_Functions
333 * @{
334 */
335
336 /**
337 * @brief Setup the microcontroller system.
338 * Initializes the system clocks and the embedded Flash.
339 * @note This function should be used after reset.
340 * @retval None
341 */
SystemInit(void)342 void SystemInit(void)
343 {
344 #if (WDT_ENABLE == 1)
345 HT_CKCU->APBCCR1 |= (0x1 << 4);
346 HT_WDT->PR = 0x35CA;
347 HT_WDT->MR0 = 0;
348 HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12));
349 HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16);
350 HT_WDT->CR = 0x5FA00001;
351 #else
352 #if (DEINIT_ENABLE == 1)
353 HT_RSTCU->APBPRST1 = (1 << 4);
354 #endif
355 #endif
356
357 SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */
358
359 #if (DEINIT_ENABLE == 1)
360 /* De-init the setting */
361 HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */
362 SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */
363 while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */
364 HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */
365 while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */
366 HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */
367 HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */
368 ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */
369 SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */
370 #endif
371
372 /* HSE initiation */
373 #if (HSE_ENABLE == 1)
374 SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */
375 while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */
376 #endif
377
378 /* LSE initiation */
379 #if defined(USE_HT32F65230_40)
380 #if (LSE_ENABLE == 1)
381 do {
382 SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */
383 } while (!GetBit_BB((u32)(&HT_RTC->CR), 3));
384 while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */
385 #endif
386 #endif
387
388 ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */
389
390 /* LSI initiation */
391 #if (HCLK_SRC == 7)
392 while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */
393 #endif
394
395 /* PLL initiation */
396 #if (PLL_ENABLE == 1)
397 HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */
398
399 #if (PLL_CLK_SRC_DIV == 1)
400 SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */
401 #else
402 ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */
403 #endif
404
405 #if (PLL_CLK_SRC == 0)
406 ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */
407 #else
408 SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */
409 #endif
410
411 SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */
412 while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */
413 #endif
414
415 /* CK_AHB initiation */
416 #if (WAIT_STATE == 9)
417 #if (__CK_AHB > WS1_CLK)
418 HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */
419 #elif (__CK_AHB > WS0_CLK)
420 HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */
421 #endif
422 #else
423 HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */
424 #endif
425
426 HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */
427 HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */
428 while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */
429
430 /* Pre-fetch buffer configuration */
431 #if (PRE_FETCH_ENABLE == 0)
432 ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */
433 #else
434 SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */
435 #endif
436
437 /* Branch cache configuration */
438 #if (BCACHE_ENABLE == 0)
439 ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */
440 #else
441 SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */
442 #endif
443
444 /* HSE power down */
445 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1)))
446 ResetBit_BB((u32)(&HT_CKCU->GCCR), 10);
447 #endif
448
449 /* HSI power down */
450 #if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0)))
451 ResetBit_BB((u32)(&HT_CKCU->GCCR), 11);
452 #endif
453 }
454
455 /**
456 * @brief Update SystemCoreClock
457 * @retval None
458 */
SystemCoreClockUpdate(void)459 void SystemCoreClockUpdate(void)
460 {
461 u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL;
462 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL;
463 u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL);
464 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL;
465 u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL;
466
467 /* Get system core clock according to global clock control & configuration registers */
468 if (SystemCoreClockSrc == 1)
469 {
470 if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31))
471 {
472 PllFeedbackClockDiv = 1;
473 PllOutputClockDiv = 0;
474 }
475
476 if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8))
477 {
478 SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv;
479 }
480 else
481 {
482 SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv;
483 }
484 }
485 else if (SystemCoreClockSrc == 2)
486 {
487 SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv;
488 }
489 else if (SystemCoreClockSrc == 3)
490 {
491 SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv;
492 }
493 #if defined(USE_HT32F65230_40)
494 else if (SystemCoreClockSrc == 6)
495 {
496 SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv;
497 }
498 #endif
499 else if (SystemCoreClockSrc == 7)
500 {
501 SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv;
502 }
503 }
504
505 /**
506 * @}
507 */
508
509
510 /**
511 * @}
512 */
513
514 /**
515 * @}
516 */
517
518 /******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */
519