1 /** 2 ****************************************************************************** 3 * @file tae32f53xx_ll_tmr.h 4 * @author MCD Application Team 5 * @brief Header for TMR LL module driver 6 * 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2020 Tai-Action. 11 * All rights reserved.</center></h2> 12 * 13 * This software is licensed by Tai-Action under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef _TAE32F53XX_LL_TMR_H_ 23 #define _TAE32F53XX_LL_TMR_H_ 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif /* __cplusplus */ 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "tae32f53xx_ll_def.h" 31 32 33 /** @addtogroup TAE32F53xx_LL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup TMR_LL 38 * @{ 39 */ 40 41 42 /* Exported types ------------------------------------------------------------*/ 43 /** @defgroup TMR_LL_Exported_Types TMR LL Exported Types 44 * @brief TMR LL Exported Types 45 * @{ 46 */ 47 48 /** 49 * @brief TMR Continuous Mode 50 */ 51 typedef enum { 52 TMR_CONTINUOUS_MODE_ENABLE = 0x00000000U, /*!< TMR performed in Continuous counting mode */ 53 TMR_CONTINUOUS_MODE_DISABLE = TMR_CR_MS, /*!< TMR performed in Single counting mode */ 54 } TMR_ContinuousETypeDef; 55 56 /** 57 * @brief TMR Update Event Enable 58 */ 59 typedef enum { 60 TMR_UPDATE_ENABLE = 0x00000000U, /*!< Update event generation enabled */ 61 TMR_UPDATE_DISABLE = TMR_CR_UDIS, /*!< Update event generation disabled */ 62 } TMR_UpdateETypeDef; 63 64 /** 65 * @brief TMR_Update_Request_Source TMR Update Request Source 66 */ 67 typedef enum { 68 TMR_UPDATE_SOURCE_REGULAR = 0x00000000U, /*!< Counter overflow or Setting the UG bit generates an update request */ 69 TMR_UPDATE_SOURCE_COUNTER = TMR_CR_URS, /*!< Only counter overflow generates an update request */ 70 } TMR_UpdateSrcETypeDef; 71 72 /** 73 * @brief TMR Auto-Reload Preload 74 */ 75 typedef enum { 76 TMR_AUTORELOAD_PRELOAD_DISABLE = 0x00000000U, /*!< Disable auto-reload preload feature */ 77 TMR_AUTORELOAD_PRELOAD_ENABLE = TMR_CR_ARPE, /*!< Enable auto-reload preload feature */ 78 } TMR_AutoReloadETypeDef; 79 80 /** 81 * @brief TMR Clock Souce 82 */ 83 typedef enum { 84 TMR_CLKSOURCE_INTERNAL = TMR_CR_CKSRC_0, /*!< Internal clock source */ 85 TMR_CLKSOURCE_ETR_RISING = TMR_CR_CKSRC_1, /*!< External clock source rising edge */ 86 TMR_CLKSOURCE_ETR_FALLING = TMR_CR_CKSRC_2, /*!< External clock source falling edge */ 87 TMR_CLKSOURCE_ETR_BOTHEDGE = TMR_CR_CKSRC_3, /*!< External clock source both rising and falling edge */ 88 } TMR_ClkSrcETypeDef; 89 90 /** 91 * @brief TMR PWM Wave Export 92 */ 93 typedef enum { 94 TMR_EXT_PWM_WAVE_DISABLE = 0x00000000U, /*!< Disable the export of the PWM Wave */ 95 TMR_EXT_PWM_WAVE_ENABLE = TMR_ETER_PWMOE, /*!< Enable the export of the PWM Wave */ 96 } TMR_Ext_PWMETypeDef; 97 98 /** 99 * @brief TMR Capture Compare Event Trigger Export 100 */ 101 typedef enum { 102 TMR_EXT_CC_TRIGGER_DISABLE = 0x00000000U, /*!< Disable the export of the Capture Compare Trigger */ 103 TMR_EXT_CC_TRIGGER_ENABLE = TMR_ETER_CCTE, /*!< Enable the export of the Capture Compare Trigger */ 104 } TMR_Ext_CCETypeDef; 105 106 /** 107 * @brief TMR TRGO Trigger Export 108 */ 109 typedef enum { 110 TMR_EXT_TRGO_TRIGGER_DISABLE = 0x00000000U, /*!< Disable the export of the TRGO signal (source from Update Event) Trigger */ 111 TMR_EXT_TRGO_TRIGGER_ENABLE = TMR_ETER_UTE, /*!< Enable the export of the TRGO signal (source from Update Event) Trigger */ 112 } TMR_Ext_TRGOETypeDef; 113 114 /** 115 * @brief TMR Event Source 116 */ 117 typedef enum { 118 TMR_EVENTSOURCE_UG = TMR_EGR_UG, /*!< Reinitialize the counter and generates an update of the registers */ 119 TMR_EVENTSOURCE_CCG = TMR_EGR_CCG, /*!< A capture/compare event is generated */ 120 } TMR_EventSRCETypeDef; 121 122 /** @brief TMR Input Capture Selection 123 */ 124 typedef enum { 125 TMR_ICSELECTION_TMR0 = TMR_CCCR_ICSRS_0, /*!< TMR input capture source TMR0 io (specific to (LS)TMR0/1/2/3). */ 126 TMR_ICSELECTION_TMR4 = TMR_CCCR_ICSRS_0, /*!< TMR input capture source TMR4 io (specific to (HS)TMR4/5/6/7). */ 127 128 TMR_ICSELECTION_TMR1 = TMR_CCCR_ICSRS_1, /*!< TMR input capture source TMR1 io (specific to (LS)TMR0/1/2/3). */ 129 TMR_ICSELECTION_TMR5 = TMR_CCCR_ICSRS_1, /*!< TMR input capture source TMR5 io (specific to (HS)TMR4/5/6/7). */ 130 131 TMR_ICSELECTION_TMR2 = TMR_CCCR_ICSRS_2, /*!< TMR input capture source TMR2 io (specific to (LS)TMR0/1/2/3). */ 132 TMR_ICSELECTION_TMR6 = TMR_CCCR_ICSRS_2, /*!< TMR input capture source TMR6 io (specific to (HS)TMR4/5/6/7). */ 133 134 TMR_ICSELECTION_TMR3 = TMR_CCCR_ICSRS_3, /*!< TMR input capture source TMR3 io (specific to (LS)TMR0/1/2/3). */ 135 TMR_ICSELECTION_TMR7 = TMR_CCCR_ICSRS_3, /*!< TMR input capture source TMR7 io (specific to (HS)TMR4/5/6/7). */ 136 137 TMR_ICSELECTION_CMP0 = TMR_CCCR_ICSRS_4, /*!< The internal CMP0 output single 138 will be selected as the input source of LSTMR or HSTMR */ 139 140 TMR_ICSELECTION_CMP1 = TMR_CCCR_ICSRS_5, /*!< The internal CMP1 output single 141 will be selected as the input source of LSTMR or HSTMR */ 142 143 TMR_ICSELECTION_CMP2 = TMR_CCCR_ICSRS_6, /*!< The internal CMP2 output single 144 will be selected as the input source of LSTMR or HSTMR */ 145 146 TMR_ICSELECTION_CMP3 = TMR_CCCR_ICSRS_7, /*!< The internal CMP3 output single 147 will be selected as the input source of LSTMR or HSTMR */ 148 } TMR_ICSelETypeDef; 149 150 /** 151 * @brief TMR Input Capture Polarity 152 */ 153 typedef enum { 154 TMR_ICPOLARITY_RISING = 0x00000000U, /*!< Capture triggered by rising edge on timer input */ 155 TMR_ICPOLARITY_FALLING = TMR_CCCR_CCP_0, /*!< Capture triggered by falling edge on timer input */ 156 TMR_ICPOLARITY_BOTHEDGE = TMR_CCCR_CCP_1, /*!< Capture triggered by both rising and falling edges on timer input */ 157 } TMR_ICPolarityETypeDef; 158 159 /** 160 * @brief TMR Output Compare and PWM Modes 161 */ 162 typedef enum { 163 TMR_OCMODE_FROZEN = TMR_CCCR_OCM_0, /*!< Frozen */ 164 TMR_OCMODE_ACTIVE = TMR_CCCR_OCM_1, /*!< active on match */ 165 TMR_OCMODE_INACTIVE = TMR_CCCR_OCM_2, /*!< inactive on match */ 166 TMR_OCMODE_TOGGLE = TMR_CCCR_OCM_3, /*!< Toggle */ 167 TMR_OCMODE_FORCED_INACTIVE = TMR_CCCR_OCM_4, /*!< Force inactive */ 168 TMR_OCMODE_FORCED_ACTIVE = TMR_CCCR_OCM_5, /*!< Force active */ 169 TMR_OCMODE_PWM1 = TMR_CCCR_OCM_6, /*!< PWM mode 1 */ 170 TMR_OCMODE_PWM2 = TMR_CCCR_OCM_7, /*!< PWM mode 2 */ 171 } TMR_OCModeETypeDef; 172 173 /** 174 * @brief TMR_OCPreload_Enable TMR OCPreload Enable 175 */ 176 typedef enum { 177 TMR_OCPRELOAD_DISABLE = 0x00000000U, /*!< TMR OCPreload Disable */ 178 TMR_OCPRELOAD_ENABLE = TMR_CCCR_OCPE, /*!< TMR OCPreload Enable */ 179 } TMR_OCPreloadETypeDef; 180 181 /** 182 * @brief TMR Complementary Output Compare Polarity 183 */ 184 typedef enum { 185 TMR_OCPOLARITY_HIGH = 0x00000000U, /*!< Output Compare polarity active high */ 186 TMR_OCPOLARITY_LOW = TMR_CCCR_CCP_0, /*!< Output Compare polarity active low */ 187 } TMR_OCPolarityETypeDef; 188 189 /** 190 * @brief Timer Base Unit Initialization Structure definition 191 * @note Please notice that TMR can enable either Input Capture mode or Output Compare mode. 192 */ 193 typedef struct __TMR_TB_InitTypeDef { 194 TMR_ClkSrcETypeDef ClockSource; /*!< Specifies the Clock Source. */ 195 196 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TMR clock. 197 This parameter can be a number in range of: 198 For low-speed timer(TMR0/1/2/3): from Min 0x0 to Max 0x0000FFFF 199 For high-speed timer(TMR4/5/6/7): from Min 0x0 to Max 0xFFFFFFFF */ 200 201 uint32_t StartValue; /*!< Specifies the timer counter start value. 202 This parameter can be a number in range of: 203 For low-speed timer(TMR0/1/2/3): from Min 0x0 to Max 0x0000FFFF 204 For high-speed timer(TMR4/5/6/7): from Min 0x0 to Max 0xFFFFFFFF */ 205 206 uint32_t EndValue; /*!< Specifies the timer counter end value. 207 This parameter can be a number in range of: 208 For low-speed timer(TMR0/1/2/3): from Min 0x0 to Max 0x0000FFFF 209 For high-speed timer(TMR4/5/6/7): from Min 0x0 to Max 0xFFFFFFFF */ 210 211 TMR_ContinuousETypeDef ContinuousMode; /*!< Specifies the timer continuous mode enable or disable. */ 212 213 TMR_AutoReloadETypeDef AutoReloadPreload; /*!< Specifies the auto-reload preload. */ 214 215 TMR_UpdateETypeDef UpdateEnable; /*!< Specifies the Update event enable or not. */ 216 217 TMR_UpdateSrcETypeDef UpdateSource; /*!< Specifies the Update request Source */ 218 } TMR_TB_InitTypeDef; 219 220 /** 221 * @brief Timer Input Capture Initialization Structure definition 222 * @note Please notice that TMR can enable either Input Capture mode or Output Compare mode. 223 */ 224 typedef struct __TMR_IC_InitTypeDef { 225 LL_FuncStatusETypeDef ICEnable; /*!< Specifies enable the Input Capture feature or not. 226 This parameter can be ENABLE or DISABLE */ 227 228 TMR_ICPolarityETypeDef ICPolarity; /*!< Specifies the active edge of the input signal. */ 229 230 TMR_ICSelETypeDef ICSelection; /*!< Specifies the input source to be used. */ 231 232 uint32_t ICFilter; /*!< Specifies the input capture filter. 233 This parameter can be a number between 0x0 and 0xFF */ 234 } TMR_IC_InitTypeDef; 235 236 /** 237 * @brief Timer Output Compare Initialization Structure definition 238 * @note Please notice that TMR can enable either Input Capture mode or Output Compare mode. 239 */ 240 typedef struct __TMR_OC_InitTypeDef { 241 LL_FuncStatusETypeDef OCEnable; /*!< Specifies enable the Output Compare feature or not. 242 This parameter can be ENABLE or DISABLE */ 243 244 TMR_OCPolarityETypeDef OCPolarity; /*!< Specifies the output polarity. */ 245 246 TMR_OCPreloadETypeDef OCPreload; /*!< Timer Output Compare Preload Enable */ 247 248 TMR_OCModeETypeDef OCMode; /*!< Specifies the TMR mode. */ 249 250 uint32_t OCValue; /*!< Specifies the compare value which loaded into Capture Compare Register. 251 This parameter can be a number in range of: 252 For low-speed timer(TMR0/1/2/3): from Min 0x0 to Max 0x0000FFFF 253 For high-speed timer(TMR4/5/6/7): from Min 0x0 to Max 0xFFFFFFFF */ 254 } TMR_OC_InitTypeDef; 255 256 /** 257 * @brief Timer Export Trigger Initialization Structure definition 258 */ 259 typedef struct __TMR_EXT_InitTypeDef { 260 LL_FuncStatusETypeDef ExtEnable; /*!< Specifies enable the Export Event Trigger feature or not. 261 This parameter can be ENABLE or DISABLE */ 262 263 TMR_Ext_PWMETypeDef ExtPWMWave; /*!< Specifies PWM Wave (output compare) export to internal signal or not. */ 264 265 TMR_Ext_CCETypeDef ExtCCTrigger; /*!< Specifies Capture Compare Trigger Event export to internal signal or not. */ 266 267 TMR_Ext_TRGOETypeDef ExtTRGOTrigger;/*!< Specifies TMR TRGO signal (source from Update Event) export to internal signal or not. */ 268 } TMR_EXT_InitTypeDef; 269 270 /** 271 * @brief Timer Initialization Structure definition 272 * @note Please notice that TMR can be configured to either Input Capture mode or Output Compare mode. 273 * Witch means that either ICEnable or OCEnable in the Initialization Structure can be enable the feature. 274 */ 275 typedef struct __TMR_InitTypeDef { 276 TMR_TB_InitTypeDef TBInit; /*!< Timer Base Unit Initialization Structure definition */ 277 278 TMR_IC_InitTypeDef ICInit; /*!< Timer Input Capture Initialization Structure definition */ 279 280 TMR_OC_InitTypeDef OCInit; /*!< Timer Output Compare Initialization Structure */ 281 282 TMR_EXT_InitTypeDef ExtInit; /*!< Timer Export Event Trigger feature Initialization Structure */ 283 } TMR_InitTypeDef; 284 285 /** 286 * @} 287 */ 288 289 290 /* Exported constants --------------------------------------------------------*/ 291 /** @defgroup TMR_LL_Exported_Constants TMR LL Exported Constants 292 * @brief TMR LL Exported Constants 293 * @{ 294 */ 295 296 /** @defgroup TMR_Interrupt_definition TMR Interrupt Definition 297 * @{ 298 */ 299 #define TMR_IT_UIE TMR_CR_UIE /*!< Update interrupt */ 300 #define TMR_IT_OVIE TMR_CR_OVIE /*!< Counter Overflow interrupt */ 301 /** 302 * @} 303 */ 304 305 /** @defgroup TMR_CC_Interrupt_definition TMR Capture/Compare Interrupt Definition 306 * @{ 307 */ 308 #define TMR_IT_ICIE TMR_CCCR_ICIE /*!< Input Capture interrupt */ 309 #define TMR_IT_ICOIE TMR_CCCR_ICOIE /*!< Input Capture OverCapture interrupt */ 310 #define TMR_IT_OCIE TMR_CCCR_OCIE /*!< Output Compare Match interrupt */ 311 /** 312 * @} 313 */ 314 315 /** @defgroup TMR_Flag_definition TMR Flag Definition 316 * @{ 317 */ 318 #define TMR_FLAG_OVIF TMR_ISR_OVIF /*!< Timer Counter Overflow Interrupt Flag */ 319 #define TMR_FLAG_ICOIF TMR_ISR_ICOIF /*!< Timer Input Capture OverCapture Interrupt Flag */ 320 #define TMR_FLAG_ICIF TMR_ISR_ICIF /*!< Timer Input Capture Interrupt Flag */ 321 #define TMR_FLAG_OCIF TMR_ISR_OCIF /*!< Timer Output Compare Interrupt Flag */ 322 #define TMR_FLAG_UIF TMR_ISR_UIF /*!< Timer Counter Update Interrupt Flag */ 323 /** 324 * @} 325 */ 326 327 /** @defgroup TMR_Sync_definition Timer Group synchronization Definition 328 * @{ 329 */ 330 #define TMRGRP_SYNC_TMR0 TMRGRP_SYNC0EN /*!< Select TMR0(specific to TMRGRP0) */ 331 #define TMRGRP_SYNC_TMR4 TMRGRP_SYNC0EN /*!< Select TMR4(specific to TMRGRP1) */ 332 333 #define TMRGRP_SYNC_TMR1 TMRGRP_SYNC1EN /*!< Select TMR1(specific to TMRGRP0) */ 334 #define TMRGRP_SYNC_TMR5 TMRGRP_SYNC1EN /*!< Select TMR5(specific to TMRGRP1) */ 335 336 #define TMRGRP_SYNC_TMR2 TMRGRP_SYNC2EN /*!< Select TMR2(specific to TMRGRP0) */ 337 #define TMRGRP_SYNC_TMR6 TMRGRP_SYNC2EN /*!< Select TMR6(specific to TMRGRP1) */ 338 339 #define TMRGRP_SYNC_TMR3 TMRGRP_SYNC3EN /*!< Select TMR2(specific to TMRGRP0) */ 340 #define TMRGRP_SYNC_TMR7 TMRGRP_SYNC3EN /*!< Select TMR6(specific to TMRGRP1) */ 341 342 #define TMRGRP_SYNC_ALL TMRGRP_SYNCALLEN /*!< Select all TMRs in TMRGRPx(x = 0 or 1) */ 343 /** 344 * @} 345 */ 346 347 /** 348 * @} 349 */ 350 351 352 /* Exported macro ------------------------------------------------------------*/ 353 /** @defgroup TMR_LL_Exported_Macros TMR LL Exported Macros 354 * @brief TMR LL Exported Macros 355 * @{ 356 */ 357 358 /** 359 * @brief Enable TMR Base Unit on runtime 360 * @param __INSTANCE__ TMR peripheral 361 * @return None 362 */ 363 #define __LL_TMR_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CR, TMR_CR_CEN) 364 365 /** 366 * @brief Disable TMR Base Unit on runtime 367 * @param __INSTANCE__ TMR peripheral 368 * @return None 369 */ 370 #define __LL_TMR_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CR, TMR_CR_CEN) 371 372 /** 373 * @brief Enable TMR Capture/Compare feature on runtime 374 * @param __INSTANCE__ TMR peripheral 375 * @return None 376 */ 377 #define __LL_TMR_CC_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CCCR, TMR_CCCR_CCE) 378 379 /** 380 * @brief Disable TMR Capture/Compare feature on runtime 381 * @param __INSTANCE__ TMR peripheral 382 * @return None 383 */ 384 #define __LL_TMR_CC_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CCCR, TMR_CCCR_CCE) 385 386 387 /** 388 * @brief Enable the specified TMR Basic Unit Interrupt 389 * @param __INSTANCE__ TMR peripheral 390 * @param __INTERRUPT__ specifies the TMR base unit interrupt source to enable. 391 * This parameter can be any combination of @ref TMR_Interrupt_definition: 392 * @arg TMR_IT_UIE: Update interrupt 393 * @arg TMR_IT_OVIE: Counter Overflow interrupt 394 * @return None 395 */ 396 #define __LL_TMR_IT_ENABLE(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->CR, (__INTERRUPT__)) 397 398 /** 399 * @brief Disable the specified TMR Basic Unit Interrupt 400 * @param __INSTANCE__ TMR peripheral 401 * @param __INTERRUPT__ specifies the TMR base unit interrupt source to disable. 402 * This parameter can be any combination of @ref TMR_Interrupt_definition: 403 * @arg TMR_IT_UIE: Update interrupt 404 * @arg TMR_IT_OVIE: Counter Overflow interrupt 405 * @return None 406 */ 407 #define __LL_TMR_IT_DISABLE(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->CR, (__INTERRUPT__)) 408 409 /** 410 * @brief Check whether the specified TMR Basic Unit interrupt source is set or not. 411 * @param __INSTANCE__ TMR peripheral 412 * @param __INTERRUPT__ specifies the TMR interrupt source to check. 413 * This parameter can be any combination of @ref TMR_Interrupt_definition: 414 * @arg TMR_IT_UIE: Update interrupt 415 * @arg TMR_IT_OVIE: Counter Overflow interrupt 416 * @return The state of __INTERRUPT__ (SET or RESET). 417 */ 418 #define __LL_TMR_IT_CHECK_SOURCE(__INSTANCE__, __INTERRUPT__) ((READ_BIT((__INSTANCE__)->CR, (__INTERRUPT__)) \ 419 == (__INTERRUPT__)) ? SET : RESET) 420 421 /** 422 * @brief Enable the specified Capture/Compare Interrupt 423 * @param __INSTANCE__ TMR peripheral 424 * @param __INTERRUPT__ specifies the TMR Capture/Compare interrupt source to enable. 425 * This parameter can be any combination of @ref TMR_CC_Interrupt_definition: 426 * @arg TMR_IT_ICIE: Input Capture interrupt 427 * @arg TMR_IT_ICOIE: Input Capture OverCapture interrupt 428 * @arg TMR_IT_OCIE: Output Compare Match interrupt 429 * @return None 430 */ 431 #define __LL_TMR_CC_IT_ENABLE(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->CCCR, (__INTERRUPT__)) 432 433 /** 434 * @brief Disable Input Capture Interrupt 435 * @param __INSTANCE__ TMR peripheral 436 * @param __INTERRUPT__ specifies the TMR Capture/Compare interrupt source to disable. 437 * This parameter can be any combination of @ref TMR_CC_Interrupt_definition: 438 * @arg TMR_IT_ICIE: Input Capture interrupt 439 * @arg TMR_IT_ICOIE: Input Capture OverCapture interrupt 440 * @arg TMR_IT_OCIE: Output Compare Matched interrupt 441 * @return None 442 */ 443 #define __LL_TMR_CC_IT_DISABLE(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->CCCR, (__INTERRUPT__)) 444 445 446 /** 447 * @brief Check whether the specified TMR Capture/Compare interrupt source is set or not. 448 * @param __INSTANCE__ TMR peripheral 449 * @param __INTERRUPT__ specifies the TMR Capture/Compare interrupt source to check. 450 * This parameter can be any combination of @ref TMR_CC_Interrupt_definition: 451 * @arg TMR_IT_ICIE: Input Capture interrupt 452 * @arg TMR_IT_ICOIE: Input Capture OverCapture interrupt 453 * @arg TMR_IT_OCIE: Output Compare Matched interrupt 454 * @return he state of __INTERRUPT__ (SET or RESET). 455 */ 456 #define __LL_TMR_CC_IT_CHECK_SOURCE(__INSTANCE__, __INTERRUPT__) \ 457 ((READ_BIT((__INSTANCE__)->CCCR, (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 458 459 /** 460 * @brief Check whether the specified TMR interrupt flag is set or not. 461 * @param __INSTANCE__ TMR peripheral. 462 * @param __FLAG__ specifies the TMR flags to check. 463 * This parameter can be any combination of @ref TMR_Flag_definition: 464 * @arg TMR_FLAG_OVIF: Counter Overflow Interrupt Flag 465 * @arg TMR_FLAG_ICOIF: Input Capture OverCapture Interrupt Flag 466 * @arg TMR_FLAG_ICIF: Input Capture Interrupt Flag 467 * @arg TMR_FLAG_OCIF: Output Compare Interrupt Flag 468 * @arg TMR_FLAG_UIF: Counter Update Interrupt Flag 469 * @return The state of __FLAG__ (SET or RESET). 470 */ 471 #define __LL_TMR_GET_FLAG(__INSTANCE__, __FLAG__) \ 472 ((READ_BIT((__INSTANCE__)->ISR, (__FLAG__)) == (__FLAG__)) ? SET : RESET) 473 474 /** 475 * @brief Clear the specified TMR interrupt flags 476 * @param __INSTANCE__ TMR peripheral 477 * @param __FLAG__ specifies the TMR flags to clear. 478 * This parameter can be any combination of @ref TMR_Flag_definition: 479 * @arg TMR_FLAG_OVIF: Counter Overflow Interrupt Flag 480 * @arg TMR_FLAG_ICOIF: Input Capture OverCapture Interrupt Flag 481 * @arg TMR_FLAG_ICIF: Input Capture Interrupt Flag 482 * @arg TMR_FLAG_OCIF: Output Compare Interrupt Flag 483 * @arg TMR_FLAG_UIF: Counter Update Interrupt Flag 484 * @return None 485 */ 486 #define __LL_TMR_CLEAR_FLAG(__INSTANCE__, __FLAG__) WRITE_REG((__INSTANCE__)->ISR, (__FLAG__)) 487 488 /** 489 * @brief Enable TMR Auto-Reload feature 490 * @param __INSTANCE__ TMR peripheral 491 * @return None 492 */ 493 #define __LL_TMR_AUTORELOAD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CR, TMR_CR_ARPE) 494 495 /** 496 * @brief Disable TMR Auto-Reload feature 497 * @param __INSTANCE__ TMR peripheral 498 * @return None 499 */ 500 #define __LL_TMR_AUTORELOAD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CR, TMR_CR_ARPE) 501 502 /** 503 * @brief Enable TMR Output Compare Preload feature 504 * @param __INSTANCE__ TMR peripheral 505 * @return None 506 */ 507 #define __LL_TMR_OC_PRELOAD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CCCR, TMR_CCCR_OCPE) 508 509 /** 510 * @brief Disable TMR Output Compare Preload feature 511 * @param __INSTANCE__ TMR peripheral 512 * @return None 513 */ 514 #define __LL_TMR_OC_PRELOAD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CCCR, TMR_CCCR_OCPE) 515 516 /** 517 * @brief Enable TMR Update event (UDIS) 518 * @param __INSTANCE__ TMR peripheral 519 * @return None 520 */ 521 #define __LL_TMR_UPDATE_ENABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CR, TMR_CR_UDIS) 522 523 /** 524 * @brief Disable TMR Update event (UDIS) 525 * @param __INSTANCE__ TMR peripheral 526 * @return None 527 */ 528 #define __LL_TMR_UPDATE_DISABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CR, TMR_CR_UDIS) 529 530 /** 531 * @brief Selection of the Update Request Source (URS) bit of the TMRx_CR register. 532 * @param __INSTANCE__ TMR peripheral 533 * @param __SOURCE__ specifies the Update Request Source 534 * This parameter can be one of the following values in @ref TMR_Update_Request_Source: 535 * @arg TMR_UPDATE_SOURCE_REGULAR: Counter overflow or Setting the UG bit generates an update request 536 * @arg TMR_UPDATE_SOURCE_COUNTER: Only counter overflow generates an update request 537 * @note To generate the update request, Update event should be enabled(reset UDIS bit in TMRx_CR register). 538 * @return None 539 */ 540 #define __LL_TMR_UPDATE_SOURCE(__INSTANCE__, __SOURCE__) MODIFY_REG((__INSTANCE__)->CR, TMR_CR_URS_Msk, (__SOURCE__)) 541 542 /** 543 * @brief Set the TMR Prescaler on runtime. 544 * @param __INSTANCE__ TMR peripheral 545 * @param __PRESC__ specifies the Prescaler new value. 546 * @retval None 547 */ 548 #define __LL_TMR_SET_PRESCALER(__INSTANCE__, __PRESC__) WRITE_REG((__INSTANCE__)->PSCR, (__PRESC__)) 549 550 /** 551 * @brief Get the TMR Prescaler on runtime. 552 * @param __INSTANCE__ TMR peripheral 553 * @retval 16-bit or 32-bit value of the timer prescaler register (TMRx_PSCR) 554 */ 555 #define __LL_TMR_GET_PRESCALER(__INSTANCE__) READ_REG((__INSTANCE__)->PSCR) 556 557 /** 558 * @brief Set the TMR Start value on runtime. 559 * @param __INSTANCE__ TMR peripheral 560 * @param __START__ specifies the new starting value. 561 * @retval None 562 */ 563 #define __LL_TMR_SET_START_VAL(__INSTANCE__, __START__) WRITE_REG((__INSTANCE__)->CSVR, (__START__)) 564 565 /** 566 * @brief Get the TMR Start value on runtime. 567 * @param __INSTANCE__ TMR peripheral 568 * @retval 16-bit or 32-bit value of the timer start value register (TMRx_CSVR) 569 */ 570 #define __LL_TMR_GET_START_VAL(__INSTANCE__) READ_REG((__INSTANCE__)->CSVR) 571 572 /** 573 * @brief Set the TMR End value on runtime. 574 * @param __INSTANCE__ TMR peripheral 575 * @param __END__ specifies the new ending value. 576 * @retval None 577 */ 578 #define __LL_TMR_SET_END_VAL(__INSTANCE__, __END__) WRITE_REG((__INSTANCE__)->CEVR, (__END__)) 579 580 /** 581 * @brief Get the TMR End value on runtime. 582 * @param __INSTANCE__ TMR peripheral 583 * @retval 16-bit or 32-bit value of the timer end value register (TMRx_CEVR) 584 */ 585 #define __LL_TMR_GET_END_VAL(__INSTANCE__) READ_REG((__INSTANCE__)->CEVR) 586 587 /** 588 * @brief Set the TMR Counter Register value on runtime. 589 * @param __INSTANCE__ TMR peripheral 590 * @param __COUNTER__ specifies the Counter register new value. 591 * @return None 592 */ 593 #define __LL_TMR_SET_COUNTER(__INSTANCE__, __COUNTER__) WRITE_REG((__INSTANCE__)->CNTR, (__COUNTER__)) 594 595 /** 596 * @brief Get the TMR Counter Register value on runtime. 597 * @param __INSTANCE__ TMR peripheral 598 * @return 16-bit or 32-bit value of the timer counter register (TMRx_CNTR) 599 */ 600 #define __LL_TMR_GET_COUNTER(__INSTANCE__) READ_REG((__INSTANCE__)->CNTR) 601 602 /** 603 * @brief Set the TMR Capture Compare Register(TMRx_CCR) value on runtime. 604 * @note This macro normally used when the TMR is configured in Output Compare mode. 605 * User can use the macro to change the compare value on runtime without calling 606 * another time Config function. 607 * @note The new value will take effect immediately when Output Compare Preload (OCPE) 608 * is disabled. Otherwise it will take effect by following condition: 609 * - Update event generated by counter overflow only (if Update event enabled) 610 * - Compare Matching event with the older value. 611 * - Software generate by setting the CCG bit in TMRx_EGR register 612 * @param __INSTANCE__ TMR peripheral 613 * @param __COMPARE__ specifies the Counter register new value. 614 * @return None 615 */ 616 #define __LL_TMR_SET_COMPARE(__INSTANCE__, __COMPARE__) WRITE_REG((__INSTANCE__)->CCR, (__COMPARE__)) 617 618 /** 619 * @brief Get the TMR Capture Compare Register(TMRx_CCR) value on runtime. 620 * @note This macro normally used when the TMR is configured in Input Capture mode. 621 * User can use the macro to get the new capture value on runtime when a Capture event 622 * is generated by fllowing condition: 623 * - Input source trigger an edge matches the Input Capture Polarity edge configuration (CCP) 624 * - Software generate by setting the CCG bit in TMRx_EGR register 625 * @param __INSTANCE__ TMR peripheral 626 * @return 16-bit or 32-bit value of the timer capture compare register (TMRx_CCR) 627 */ 628 #define __LL_TMR_GET_CAPTURE(__INSTANCE__) READ_REG((__INSTANCE__)->CCR) 629 630 /** 631 * @brief Set the input channel polarity. 632 * @param __INSTANCE__ Timer peripheral 633 * @param __POLARITY__ This parameter can be one of the following values in @ref TMR_Input_Capture_Polarity: 634 * @arg @ref TMR_ICPOLARITY_RISING :Capture triggered by rising edge on timer input 635 * @arg @ref TMR_ICPOLARITY_FALLING :Capture triggered by falling edge on timer input 636 * @arg @ref TMR_ICPOLARITY_BOTHEDGE :Capture triggered by both rising and falling edges on timer input 637 * @retval None 638 */ 639 #define __LL_TMR_POLARITY_SET(__INSTANCE__, __POLARITY__) MODIFY_REG((__INSTANCE__)->CCCR, TMR_CCCR_CCP_Msk, (__POLARITY__)) 640 641 /** 642 * @brief Set the TMR Ouput Compare Mode on runtime. 643 * @param __INSTANCE__ TMR peripheral 644 * @param __OCMODE__ TMR Output Compare and PWM Modes 645 * This parameter can be one of @ref TMR_Output_Compare_and_PWM_modes 646 * @return None 647 */ 648 #define __LL_TMR_SET_OCMODE(__INSTANCE__, __OCMODE__) MODIFY_REG((__INSTANCE__)->CCCR, TMR_CCCR_OCM_Msk, (__OCMODE__)) 649 650 /** 651 * @} 652 */ 653 654 655 /* Exported functions --------------------------------------------------------*/ 656 /** @addtogroup TMR_LL_Exported_Functions 657 * @{ 658 */ 659 660 /** @addtogroup TMR_LL_Exported_Functions_Group1 661 * @{ 662 */ 663 LL_StatusETypeDef LL_TMR_Init(TMR_TypeDef *Instance, TMR_InitTypeDef *Init); 664 LL_StatusETypeDef LL_TMR_DeInit(TMR_TypeDef *Instance); 665 void LL_TMR_MspInit(TMR_TypeDef *Instance); 666 void LL_TMR_MspDeInit(TMR_TypeDef *Instance); 667 /** 668 * @} 669 */ 670 671 672 /** @addtogroup TMR_LL_Exported_Functions_Group2 673 * @{ 674 */ 675 LL_StatusETypeDef LL_TMR_TB_Config(TMR_TypeDef *Instance, TMR_TB_InitTypeDef *sConfig); 676 LL_StatusETypeDef LL_TMR_IC_Config(TMR_TypeDef *Instance, TMR_IC_InitTypeDef *sConfig); 677 LL_StatusETypeDef LL_TMR_OC_Config(TMR_TypeDef *Instance, TMR_OC_InitTypeDef *sConfig); 678 LL_StatusETypeDef LL_TMR_EXT_Config(TMR_TypeDef *Instance, TMR_EXT_InitTypeDef *sConfig); 679 /** 680 * @} 681 */ 682 683 684 /** @addtogroup TMR_LL_Exported_Functions_Group3 685 * @{ 686 */ 687 LL_StatusETypeDef LL_TMR_Start(TMR_TypeDef *Instance); 688 LL_StatusETypeDef LL_TMR_Stop(TMR_TypeDef *Instance); 689 LL_StatusETypeDef LL_TMR_Start_IT(TMR_TypeDef *Instance); 690 LL_StatusETypeDef LL_TMR_Stop_IT(TMR_TypeDef *Instance); 691 LL_StatusETypeDef LL_TMR_Start_Synchro(TMRGRP_TypeDef *TMRGRPx, uint32_t SynchroMask); 692 LL_StatusETypeDef LL_TMR_Stop_Synchro(TMRGRP_TypeDef *TMRGRPx, uint32_t SynchroMask); 693 LL_StatusETypeDef LL_TMR_EventGenerate(TMR_TypeDef *Instance, TMR_EventSRCETypeDef EventSource); 694 /** 695 * @} 696 */ 697 698 699 /** @addtogroup TMR_LL_Exported_Functions_Interrupt 700 * @{ 701 */ 702 void LL_TMR_IRQHandler(TMR_TypeDef *Instance); 703 void LL_TMR_TB_UpdateCallback(TMR_TypeDef *Instance); 704 void LL_TMR_TB_OverflowCallback(TMR_TypeDef *Instance); 705 void LL_TMR_IC_CaptureCallback(TMR_TypeDef *Instance); 706 void LL_TMR_IC_OverCaptureCallback(TMR_TypeDef *Instance); 707 void LL_TMR_OC_CompareMatchedCallback(TMR_TypeDef *Instance); 708 /** 709 * @} 710 */ 711 712 /** 713 * @} 714 */ 715 716 717 /* Private types -------------------------------------------------------------*/ 718 /* Private variables ---------------------------------------------------------*/ 719 /* Private constants ---------------------------------------------------------*/ 720 /* Private macros ------------------------------------------------------------*/ 721 /** @defgroup TMR_LL_Private_Macros TMR LL Private Macros 722 * @brief TMR LL Private Macros 723 * @{ 724 */ 725 726 /** 727 * @brief Judge is LSTMR instance or not 728 * @param __INSTANCE__ instance to judge 729 * @retval 0 isn't LSTMR instance 730 * @retval 1 is LSTMR instance 731 */ 732 #define IS_TMR_LSTMR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TMR0) || \ 733 ((__INSTANCE__) == TMR1) || \ 734 ((__INSTANCE__) == TMR2) || \ 735 ((__INSTANCE__) == TMR3)) 736 737 /** 738 * @brief Judge is HSTMR instance or not 739 * @param __INSTANCE__ instance to judge 740 * @retval 0 isn't HSTMR instance 741 * @retval 1 is HSTMR instance 742 */ 743 #define IS_TMR_HSTMR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TMR4) || \ 744 ((__INSTANCE__) == TMR5) || \ 745 ((__INSTANCE__) == TMR6) || \ 746 ((__INSTANCE__) == TMR7)) 747 748 /** 749 * @brief Judge is LSTMR prescaler or not 750 * @param __PRESCALER__ prescaler to judge 751 * @retval 0 isn't LSTMR prescaler 752 * @retval 1 is LSTMR prescaler 753 */ 754 #define IS_TMR_LSTMR_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFU ) 755 756 /** 757 * @brief Judge is HSTMR prescaler or not 758 * @param __PRESCALER__ prescaler to judge 759 * @retval 0 isn't HSTMR prescaler 760 * @retval 1 is HSTMR prescaler 761 */ 762 #define IS_TMR_HSTMR_PRSCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFFFFFU ) 763 764 /** 765 * @brief Judge is LSTMR start value or not 766 * @param __VAL__ value to judge 767 * @retval 0 is LSTMR start value 768 * @retval 1 is LSTMR start value 769 */ 770 #define IS_TMR_LSTMR_START_VAL(__VAL__) ((__VAL__) <= 0xFFFFUL) 771 772 /** 773 * @brief Judge is HSTMR start value or not 774 * @param __VAL__ value to judge 775 * @retval 0 is HSTMR start value 776 * @retval 1 is HSTMR start value 777 */ 778 #define IS_TMR_HSTMR_START_VAL(__VAL__) ((__VAL__) <= 0xFFFFFFFFUL) 779 780 /** 781 * @brief Judge is LSTMR end value or not 782 * @param __VAL__ value to judge 783 * @retval 0 is LSTMR end value 784 * @retval 1 is LSTMR end value 785 */ 786 #define IS_TMR_LSTMR_END_VAL(__VAL__) ((__VAL__) <= 0xFFFFUL) 787 788 /** 789 * @brief Judge is HSTMR end value or not 790 * @param __VAL__ value to judge 791 * @retval 0 is HSTMR end value 792 * @retval 1 is HSTMR end value 793 */ 794 #define IS_TMR_HSTMR_END_VAL(__VAL__) ((__VAL__) <= 0xFFFFFFFFUL) 795 796 /** 797 * @brief Judge is LSTMR compare value or not 798 * @param __VAL__ value to judge 799 * @retval 0 isn't LSTMR compare value 800 * @retval 1 is LSTMR compare value 801 */ 802 #define IS_TMR_LSTMR_COMPARE_VAL(__VAL__) ((__VAL__) <= 0xFFFFUL) 803 804 /** 805 * @brief Judge is HSTMR compare value or not 806 * @param __VAL__ value to judge 807 * @retval 0 isn't HSTMR compare value 808 * @retval 1 is HSTMR compare value 809 */ 810 #define IS_TMR_HSTMR_COMPARE_VAL(__VAL__) ((__VAL__) <= 0xFFFFFFFFUL) 811 812 813 /** 814 * @brief Judge is TMR input capture filter or not 815 * @param __FILTER__ filter to judge 816 * @retval 0 isn't TMR input capture filter 817 * @retval 1 is TMR input capture filter 818 */ 819 #define IS_TMR_ICFILTER(__FILTER__) ((__FILTER__) <= 0xFFUL) 820 821 /** 822 * @} 823 */ 824 825 826 /* Private functions ---------------------------------------------------------*/ 827 828 829 /** 830 * @} 831 */ 832 833 /** 834 * @} 835 */ 836 837 838 #ifdef __cplusplus 839 } 840 #endif /* __cplusplus */ 841 842 843 #endif /* _TAE32F53XX_LL_TMR_H_ */ 844 845 846 /************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/ 847 848