1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the People's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef __COMMON_TWI_I_H__ 34 #define __COMMON_TWI_I_H__ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* TWI Register Offset */ 41 #define TWI_ADDR_REG (0x00) /* 31:8bit reserved,7-1bit for slave addr,0 bit for GCE */ 42 #define TWI_XADDR_REG (0x04) /* 31:8bit reserved,7-0bit for second addr in 10bit addr */ 43 #define TWI_DATA_REG (0x08) /* 31:8bit reserved, 7-0bit send or receive data byte */ 44 #define TWI_CTL_REG (0x0C) /* INT_EN,BUS_EN,M_STA,INT_FLAG,A_ACK */ 45 #define TWI_STAT_REG (0x10) /* 28 interrupt types + 0xF8 normal type = 29 */ 46 #define TWI_CLK_REG (0x14) /* 31:7bit reserved,6-3bit,CLK_M,2-0bit CLK_N */ 47 #define TWI_SRST_REG (0x18) /* 31:1bit reserved;0bit,write 1 to clear 0. */ 48 #define TWI_EFR_REG (0x1C) /* 31:2bit reserved,1:0 bit data byte follow read command */ 49 #define TWI_LCR_REG (0x20) /* 31:6bits reserved 5:0bit for sda&scl control*/ 50 #define TWI_DVFS_REG (0x24) /* 31:3bits reserved 2:0bit for dvfs control. only A10 support. */ 51 #define TWI_DRIVER_CTRL (0x200) 52 #define TWI_DRIVER_CFG (0x204) 53 #define TWI_DRIVER_SLV (0x208) 54 #define TWI_DRIVER_FMT (0x20C) 55 #define TWI_DRIVER_BUSC (0x210) 56 #define TWI_DRIVER_INTC (0x214) 57 #define TWI_DRIVER_DMAC (0x218) 58 #define TWI_DRIVER_FIFOC (0x21C) 59 #define TWI_DRIVER_SENDF (0x300) 60 #define TWI_DRIVER_RECVF (0x304) 61 62 /* TWI address register */ 63 /* general call address enable for slave mode */ 64 #define TWI_GCE_EN (0x1<<0) 65 #define TWI_ADDR_MASK (0x7f<<1) /* 7:1bits */ 66 /* 31:8bits reserved */ 67 68 69 /* TWI extend address register */ 70 /* 7:0bits for extend slave address */ 71 #define TWI_XADDR_MASK (0xff) 72 /* 31:8bits reserved */ 73 74 75 /* TWI Data register default is 0x0000_0000 */ 76 /* 7:0bits for send or received */ 77 #define TWI_DATA_MASK (0xff) 78 79 /* TWI Control Register Bit Fields & Masks, default value: 0x0000_0000*/ 80 /* 1:0 bits reserved */ 81 /* set 1 to send A_ACK,then low level on SDA */ 82 #define TWI_CTL_ACK (0x1<<2) 83 /* INT_FLAG,interrupt status flag: set '1' when interrupt coming */ 84 #define TWI_CTL_INTFLG (0x1<<3) 85 #define TWI_CTL_STP (0x1<<4) /* M_STP,Automatic clear 0 */ 86 #define TWI_CTL_STA (0x1<<5) /* M_STA,atutomatic clear 0 */ 87 /* BUS_EN, master mode should be set 1.*/ 88 #define TWI_CTL_BUSEN (0x1<<6) 89 #define TWI_CTL_INTEN (0x1<<7) /* INT_EN */ 90 /* 31:8 bit reserved */ 91 92 /* TWI Clock Register Bit Fields & Masks,default value:0x0000_0000 */ 93 /* 94 * Fin is APB CLOCK INPUT; 95 * Fsample = F0 = Fin/2^CLK_N; 96 * F1 = F0/(CLK_M+1); 97 * 98 * Foscl = F1/10 = Fin/(2^CLK_N * (CLK_M+1)*10); 99 * Foscl is clock SCL;standard mode:100KHz or fast mode:400KHz 100 */ 101 #define TWI_CLK_DUTY (0x1<<7) /* 7bit */ 102 #define TWI_CLK_DIV_M (0xf<<3) /* 6:3bit */ 103 #define TWI_CLK_DIV_N (0x7<<0) /* 2:0bit */ 104 105 /* TWI Soft Reset Register Bit Fields & Masks */ 106 /* write 1 to clear 0, when complete soft reset clear 0 */ 107 #define TWI_SRST_SRST (0x1<<0) 108 109 /* TWI Enhance Feature Register Bit Fields & Masks */ 110 /* default -- 0x0 */ 111 /* 00:no,01: 1byte, 10:2 bytes, 11: 3bytes */ 112 #define TWI_EFR_MASK (0x3<<0) 113 #define TWI_EFR_WARC_0 (0x0<<0) 114 #define TWI_EFR_WARC_1 (0x1<<0) 115 #define TWI_EFR_WARC_2 (0x2<<0) 116 #define TWI_EFR_WARC_3 (0x3<<0) 117 118 /* twi line control register -default value: 0x0000_003a */ 119 /* SDA line state control enable ,1:enable;0:disable */ 120 #define TWI_LCR_SDA_EN (0x01<<0) 121 /* SDA line state control bit, 1:high level;0:low level */ 122 #define TWI_LCR_SDA_CTL (0x01<<1) 123 /* SCL line state control enable ,1:enable;0:disable */ 124 #define TWI_LCR_SCL_EN (0x01<<2) 125 /* SCL line state control bit, 1:high level;0:low level */ 126 #define TWI_LCR_SCL_CTL (0x01<<3) 127 /* current state of SDA,readonly bit */ 128 #define TWI_LCR_SDA_STATE_MASK (0x01<<4) 129 /* current state of SCL,readonly bit */ 130 #define TWI_LCR_SCL_STATE_MASK (0x01<<5) 131 /* 31:6bits reserved */ 132 #define TWI_LCR_IDLE_STATUS (0x3a) 133 #define TWI_LCR_NORM_STATUS (0x30) /* normal status */ 134 135 /* TWI Status Register Bit Fields & Masks */ 136 #define TWI_STAT_MASK (0xff) 137 /* 7:0 bits use only,default is 0xF8 */ 138 #define TWI_STAT_BUS_ERR (0x00) /* BUS ERROR */ 139 /* Master mode use only */ 140 #define TWI_STAT_TX_STA (0x08) /* START condition transmitted */ 141 /* Repeated START condition transmitted */ 142 #define TWI_STAT_TX_RESTA (0x10) 143 /* Address+Write bit transmitted, ACK received */ 144 #define TWI_STAT_TX_AW_ACK (0x18) 145 /* Address+Write bit transmitted, ACK not received */ 146 #define TWI_STAT_TX_AW_NAK (0x20) 147 /* data byte transmitted in master mode,ack received */ 148 #define TWI_STAT_TXD_ACK (0x28) 149 /* data byte transmitted in master mode ,ack not received */ 150 #define TWI_STAT_TXD_NAK (0x30) 151 /* arbitration lost in address or data byte */ 152 #define TWI_STAT_ARBLOST (0x38) 153 /* Address+Read bit transmitted, ACK received */ 154 #define TWI_STAT_TX_AR_ACK (0x40) 155 /* Address+Read bit transmitted, ACK not received */ 156 #define TWI_STAT_TX_AR_NAK (0x48) 157 /* data byte received in master mode ,ack transmitted */ 158 #define TWI_STAT_RXD_ACK (0x50) 159 /* date byte received in master mode,not ack transmitted */ 160 #define TWI_STAT_RXD_NAK (0x58) 161 /* Slave mode use only */ 162 /* Slave address+Write bit received, ACK transmitted */ 163 #define TWI_STAT_RXWS_ACK (0x60) 164 #define TWI_STAT_ARBLOST_RXWS_ACK (0x68) 165 /* General Call address received, ACK transmitted */ 166 #define TWI_STAT_RXGCAS_ACK (0x70) 167 #define TWI_STAT_ARBLOST_RXGCAS_ACK (0x78) 168 #define TWI_STAT_RXDS_ACK (0x80) 169 #define TWI_STAT_RXDS_NAK (0x88) 170 #define TWI_STAT_RXDGCAS_ACK (0x90) 171 #define TWI_STAT_RXDGCAS_NAK (0x98) 172 #define TWI_STAT_RXSTPS_RXRESTAS (0xA0) 173 #define TWI_STAT_RXRS_ACK (0xA8) 174 #define TWI_STAT_ARBLOST_SLAR_ACK (0xB0) 175 /* 10bit Address, second part of address */ 176 /* Second Address byte+Write bit transmitted,ACK received */ 177 #define TWI_STAT_TX_SAW_ACK (0xD0) 178 /* Second Address byte+Write bit transmitted,ACK not received */ 179 #define TWI_STAT_TX_SAW_NAK (0xD8) 180 /* No relevant status information,INT_FLAG = 0 */ 181 #define TWI_STAT_IDLE (0xF8) 182 183 /* Offset:0x0200. Twi driver control register(Default Value:0x00F8_0000) */ 184 #define TWI_DRV_EN (0x01<<0) 185 #define TWI_DRV_RST (0x01<<1) 186 #define TWI_DRV_STA (0xff<<16) 187 #define TRAN_RESULT (0x0f<<24) 188 #define READ_TRAN (0x01<<28) 189 #define START_TRAN (0x01<<31) 190 #define TRAN_OK 0x00 191 #define TRAN_FAIL 0x01 192 193 /* 194 * Offset:0x0204. 195 * Twi driver transmission configuration register(Default Value:0x1000_0001) 196 */ 197 #define PACKET_MASK (0xffff<<0) 198 #define INTERVAL_MASK (0xff<<16) 199 200 /* Offset:0x0208. Twi driver slave id register(Default Value:0x0000_0000) */ 201 #define SLV_ID_X (0xff<<0) 202 #define SLV_RD_CMD (0x01<<8) 203 #define SLV_ID (0x7f<<9) 204 205 /* 206 * Offset:0x020C. 207 * Twi driver packet format register(Default Value:0x0001_0001) 208 */ 209 #define DATA_BYTE 0xffff 210 #define ADDR_BYTE (0xff<<16) 211 212 /* Offset:0x0210. Twi driver bus control register(Default Value:0x0000_00C0) */ 213 #define TWI_DRV_CLK_DUTY (0x01<<16) 214 #define TWI_DRV_CLK_M (0x0f<<8) 215 #define TWI_DRV_CLK_N (0x07<<12) 216 217 /* 218 * Offset:0x0214. 219 * Twi driver interrupt control register(Default Value:0x0000_0000) 220 */ 221 #define TRAN_COM_PD (0x1<<0) 222 #define TRAN_ERR_PD (0x1<<1) 223 #define TX_REQ_PD (0x1<<2) 224 #define RX_REQ_PD (0x1<<3) 225 #define TRAN_COM_INT (0x1<<16) 226 #define TRAN_ERR_INT (0x1<<17) 227 #define TX_REQ_INT (0x1<<18) 228 #define RX_REQ_INT (0x1<<19) 229 #define TWI_DRV_INT_MASK (0x0f<<16) 230 #define TWI_DRV_STAT_MASK (0x0f<<0) 231 232 /* 233 * Offset:0x0218. 234 * Twi driver DMA configure register(Default Value:0x0010_0010) 235 */ 236 #define TRIG_DEFAULT 0x10 237 #define TRIG_MASK 0x3f 238 #define DMA_TX (0x01<<8) 239 #define DMA_RX (0x01<<24) 240 #define TWI_DRQEN_MASK (DMA_TX | DMA_RX) 241 242 /* Offset:0x021C. Twi driver FIFO content register(Default Value:0x0000_0000) */ 243 #define SEND_FIFO_CONT (0x3f<<0) 244 #define SEND_FIFO_CLEAR (0x01<<6) 245 #define RECV_FIFO_CONT (0x3f<<16) 246 #define RECV_FIFO_CLEAR (0x01<<22) 247 248 /* 249 * Offset:0x0300. 250 * Twi driver send data FIFO access register(Default Value:0x0000_0000) 251 */ 252 #define SEND_DATA_FIFO (0xff<<0) 253 254 255 /* 256 * Offset:0x0304. 257 * Twi driver receive data FIFO access register(Default Value:0x0000_0000) 258 */ 259 #define RECV_DATA_FIFO (0xff<<0) 260 261 /* TWI driver result */ 262 #define RESULT_COMPLETE 1 263 #define RESULT_ERR 2 264 265 /* TWI mode select */ 266 #define TWI_MASTER_MODE (1) 267 #define TWI_SLAVE_MODE (0) /* seldom use */ 268 269 #define TWI_SEM_MAX_COUNT 0xFFFFFFFFUL 270 271 #define SUNXI_TWI_OK 0 272 #define SUNXI_TWI_FAIL -1 273 #define SUNXI_TWI_RETRY -2 274 #define SUNXI_TWI_SFAIL -3 /* start fail */ 275 #define SUNXI_TWI_TFAIL -4 /* stop fail */ 276 277 #define DMA_THRESHOLD 32 278 #define MAX_FIFO 32 279 #define DMA_TIMEOUT 1000 280 281 #define TWI_PIN_NUM 2 /*pin num of twi*/ 282 283 #ifdef __cplusplus 284 } 285 #endif 286 #endif /* __COMMON_TWI_I_H__ */ 287