1 /**************************************************************************** 2 * include/nuttx/usb/ehci.h 3 * 4 * Licensed to the Apache Software Foundation (ASF) under one or more 5 * contributor license agreements. See the NOTICE file distributed with 6 * this work for additional information regarding copyright ownership. The 7 * ASF licenses this file to you under the Apache License, Version 2.0 (the 8 * "License"); you may not use this file except in compliance with the 9 * License. You may obtain a copy of the License at 10 * 11 * http://www.apache.org/licenses/LICENSE-2.0 12 * 13 * Unless required by applicable law or agreed to in writing, software 14 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 15 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 16 * License for the specific language governing permissions and limitations 17 * under the License. 18 * 19 ****************************************************************************/ 20 /* 21 * Copyright 2022 sakumisu 22 * 23 * SPDX-License-Identifier: Apache-2.0 24 */ 25 #ifndef __INCLUDE_NUTTX_USB_EHCI_H 26 #define __INCLUDE_NUTTX_USB_EHCI_H 27 28 #define EHCI_FULL_SPEED (0) /* Full-Speed (12Mbs) */ 29 #define EHCI_LOW_SPEED (1) /* Low-Speed (1.5Mbs) */ 30 #define EHCI_HIGH_SPEED (2) /* High-Speed (480 Mb/s) */ 31 32 /* Host Controller Capability Register Bit Definitions **********************/ 33 34 /* Structural Parameters. Paragraph 2.2.3 */ 35 36 #define EHCI_HCSPARAMS_NPORTS_SHIFT (0) /* Bit 0-3: Number of physical downstream ports */ 37 #define EHCI_HCSPARAMS_NPORTS_MASK (15 << EHCI_HCSPARAMS_NPORTS_SHIFT) 38 #define EHCI_HCSPARAMS_PPC (1 << 4) /* Bit 4: Port Power Control */ 39 #define EHCI_HCSPARAMS_PRR (1 << 7) /* Bit 7: Port Routing Rules */ 40 #define EHCI_HCSPARAMS_NPCC_SHIFT (8) /* Bit 8-11: Number of Ports per Companion Controller */ 41 #define EHCI_HCSPARAMS_NPCC_MASK (15 << EHCI_HCSPARAMS_NPCC_SHIFT) 42 #define EHCI_HCSPARAMS_NCC_SHIFT (12) /* Bit 12-15: Number of Companion Controllers */ 43 #define EHCI_HCSPARAMS_NCC_MASK (15 << EHCI_HCSPARAMS_NCC_SHIFT) 44 #define EHCI_HCSPARAMS_PIND (1 << 16) /* Bit 16: Port Indicators */ 45 #define EHCI_HCSPARAMS_DBGPORT_SHIFT (20) /* Bit 20-23: Debug Port Number */ 46 #define EHCI_HCSPARAMS_DBGPORT_MASK (15 << EHCI_HCSPARAMS_DBGPORT_SHIFT) 47 48 /* Capability Parameters. Paragraph 2.2.4 */ 49 50 #define EHCI_HCCPARAMS_64BIT (1 << 0) /* Bit 0: 64-bit Addressing Capability */ 51 #define EHCI_HCCPARAMS_PFLF (1 << 1) /* Bit 1: Programmable Frame List Flag */ 52 #define EHCI_HCCPARAMS_ASPC (1 << 2) /* Bit 2: Asynchronous Schedule Park Capability */ 53 #define EHCI_HCCPARAMS_IST_SHIFT (4) /* Bits 4-7: Isochronous Scheduling Threshold */ 54 #define EHCI_HCCPARAMS_IST_MASK (15 << EHCI_HCCPARAMS_IST_SHIFT) 55 #define EHCI_HCCPARAMS_EECP_SHIFT (8) /* Bits 8-15: EHCI Extended Capabilities Pointer */ 56 #define EHCI_HCCPARAMS_EECP_MASK (0xff << EHCI_HCCPARAMS_EECP_SHIFT) 57 58 /* Host Controller Operational Register Bit Definitions *********************/ 59 60 /* USB Command. Paragraph 2.3.1 */ 61 62 #define EHCI_USBCMD_RUN (1 << 0) /* Bit 0: Run/Stop */ 63 #define EHCI_USBCMD_HCRESET (1 << 1) /* Bit 1: Host Controller Reset */ 64 #define EHCI_USBCMD_FLSIZE_SHIFT (2) /* Bits 2-3: Frame List Size */ 65 #define EHCI_USBCMD_FLSIZE_MASK (3 << EHCI_USBCMD_FLSIZE_SHIFT) 66 #define EHCI_USBCMD_FLSIZE_1024 (0 << EHCI_USBCMD_FLSIZE_SHIFT) /* 1024 elements (4096 bytes) */ 67 #define EHCI_USBCMD_FLSIZE_512 (1 << EHCI_USBCMD_FLSIZE_SHIFT) /* 512 elements (2048 bytes) */ 68 #define EHCI_USBCMD_FLSIZE_256 (2 << EHCI_USBCMD_FLSIZE_SHIFT) /* 256 elements (1024 bytes) */ 69 #define EHCI_USBCMD_PSEN (1 << 4) /* Bit 4: Periodic Schedule Enable */ 70 #define EHCI_USBCMD_ASEN (1 << 5) /* Bit 5: Asynchronous Schedule Enable */ 71 #define EHCI_USBCMD_IAAD (1 << 6) /* Bit 6: Interrupt on Async Advance Doorbell */ 72 #define EHCI_USBCMD_LRESET (1 << 7) /* Bit 7: Light Host Controller Reset */ 73 #define EHCI_USBCMD_ASYNC_PARKCNT_SHIFT (8) /* Bits 8-9: Asynchronous Schedule Park Mode Count */ 74 #define EHCI_USBCMD_ASYNC_PARKCNT_MASK (3 << EHCI_USBCMD_ASYNC_PARKCNT_SHIFT) 75 #define EHCI_USBCMD_ASYNC_PARK (1 << 11) /* Bit 11: Asynchronous Schedule Park Mode Enable */ 76 #define EHCI_USBCMD_ITHRE_SHIFT (16) /* Bits 16-23: Interrupt Threshold Control */ 77 #define EHCI_USBCMD_ITHRE_MASK (0xff << EHCI_USBCMD_ITHRE_SHIFT) 78 #define EHCI_USBCMD_ITHRE_1MF (0x01 << EHCI_USBCMD_ITHRE_SHIFT) /* 1 micro-frame */ 79 #define EHCI_USBCMD_ITHRE_2MF (0x02 << EHCI_USBCMD_ITHRE_SHIFT) /* 2 micro-frames */ 80 #define EHCI_USBCMD_ITHRE_4MF (0x04 << EHCI_USBCMD_ITHRE_SHIFT) /* 4 micro-frames */ 81 #define EHCI_USBCMD_ITHRE_8MF (0x08 << EHCI_USBCMD_ITHRE_SHIFT) /* 8 micro-frames (default, 1 ms) */ 82 #define EHCI_USBCMD_ITHRE_16MF (0x10 << EHCI_USBCMD_ITHRE_SHIFT) /* 16 micro-frames (2 ms) */ 83 #define EHCI_USBCMD_ITHRE_32MF (0x20 << EHCI_USBCMD_ITHRE_SHIFT) /* 32 micro-frames (4 ms) */ 84 #define EHCI_USBCMD_ITHRE_64MF (0x40 << EHCI_USBCMD_ITHRE_SHIFT) /* 64 micro-frames (8 ms) */ 85 86 /* USB Status. Paragraph 2.3.2 */ 87 88 #define EHCI_USBSTS_INT (1 << 0) /* Bit 0: USB Interrupt */ 89 #define EHCI_USBSTS_ERR (1 << 1) /* Bit 1: USB Error Interrupt */ 90 #define EHCI_USBSTS_PCD (1 << 2) /* Bit 2: Port Change Detect */ 91 #define EHCI_USBSTS_FLR (1 << 3) /* Bit 3: Frame List Rollover */ 92 #define EHCI_USBSTS_FATAL (1 << 4) /* Bit 4: Host System Error */ 93 #define EHCI_USBSTS_IAA (1 << 5) /* Bit 5: Interrupt on Async Advance */ 94 #define EHCI_USBSTS_HALTED (1 << 12) /* Bit 12: HC Halted */ 95 #define EHCI_USBSTS_RECLAM (1 << 13) /* Bit 13: Reclamation */ 96 #define EHCI_USBSTS_PSS (1 << 14) /* Bit 14: Periodic Schedule Status */ 97 #define EHCI_USBSTS_ASS (1 << 15) /* Bit 15: Asynchronous Schedule Status */ 98 /* Bits 16-31: Reserved */ 99 100 /* USB Interrupt Enable. Paragraph 2.3.3 */ 101 102 #define EHCI_USBIE_INT (1 << 0) /* Bit 0: USB Interrupt */ 103 #define EHCI_USBIE_ERR (1 << 1) /* Bit 1: USB Error Interrupt */ 104 #define EHCI_USBIE_PCD (1 << 2) /* Bit 2: Port Change Detect */ 105 #define EHCI_USBIE_FLROLL (1 << 3) /* Bit 3: Frame List Rollover */ 106 #define EHCI_USBIE_FATAL (1 << 4) /* Bit 4: Host System Error */ 107 #define EHCI_USBIE_IAA (1 << 5) /* Bit 5: Interrupt on Async Advance */ 108 #define EHCI_USBIE_ALLINTS (0x3f) /* Bits 0-5: All interrupts */ 109 110 /* USB Frame Index. Paragraph 2.3.4 */ 111 112 #define EHCI_FRINDEX_MASK (0x3fff) /* Bits 0-13: Frame index */ 113 114 /* 4G Segment Selector. 115 * Paragraph 2.3.5, Bits[64:32] of data structure addresses 116 */ 117 118 /* Frame List Base Address. Paragraph 2.3.6 */ 119 #define EHCI_PERIODICLISTBASE_MASK (0xfffff000) /* Bits 12-31: Base Address (Low) */ 120 121 /* Next Asynchronous List Address. Paragraph 2.3.7 */ 122 123 #define EHCI_ASYNCLISTADDR_MASK (0xffffffe0) /* Bits 5-31: Link Pointer Low (LPL) */ 124 125 /* Configured Flag Register. Paragraph 2.3.8 */ 126 127 #define EHCI_CONFIGFLAG (1 << 0) /* Bit 0: Configure Flag */ 128 129 /* Port Status/Control, Port 1-n. Paragraph 2.3.9 */ 130 131 #define EHCI_PORTSC_CCS (1 << 0) /* Bit 0: Current Connect Status */ 132 #define EHCI_PORTSC_CSC (1 << 1) /* Bit 1: Connect Status Change */ 133 #define EHCI_PORTSC_PE (1 << 2) /* Bit 2: Port Enable */ 134 #define EHCI_PORTSC_PEC (1 << 3) /* Bit 3: Port Enable/Disable Change */ 135 #define EHCI_PORTSC_OCA (1 << 4) /* Bit 4: Over-current Active */ 136 #define EHCI_PORTSC_OCC (1 << 5) /* Bit 5: Over-current Change */ 137 #define EHCI_PORTSC_RESUME (1 << 6) /* Bit 6: Force Port Resume */ 138 #define EHCI_PORTSC_SUSPEND (1 << 7) /* Bit 7: Suspend */ 139 #define EHCI_PORTSC_RESET (1 << 8) /* Bit 8: Port Reset */ 140 #define EHCI_PORTSC_LSTATUS_SHIFT (10) /* Bits 10-11: Line Status */ 141 #define EHCI_PORTSC_LSTATUS_MASK (3 << EHCI_PORTSC_LSTATUS_SHIFT) 142 #define EHCI_PORTSC_LSTATUS_SE0 (0 << EHCI_PORTSC_LSTATUS_SHIFT) /* SE0 Not Low-speed device, perform EHCI reset */ 143 #define EHCI_PORTSC_LSTATUS_KSTATE (1 << EHCI_PORTSC_LSTATUS_SHIFT) /* K-state Low-speed device, release ownership of port */ 144 #define EHCI_PORTSC_LSTATUS_JSTATE (2 << EHCI_PORTSC_LSTATUS_SHIFT) /* J-state Not Low-speed device, perform EHCI reset */ 145 #define EHCI_PORTSC_PP (1 << 12) /* Bit 12: Port Power */ 146 #define EHCI_PORTSC_OWNER (1 << 13) /* Bit 13: Port Owner */ 147 #define EHCI_PORTSC_PIC_SHIFT (14) /* Bits 14-15: Port Indicator Control */ 148 #define EHCI_PORTSC_PIC_MASK (3 << EHCI_PORTSC_PIC_SHIFT) 149 #define EHCI_PORTSC_PIC_OFF (0 << EHCI_PORTSC_PIC_SHIFT) /* Port indicators are off */ 150 #define EHCI_PORTSC_PIC_AMBER (1 << EHCI_PORTSC_PIC_SHIFT) /* Amber */ 151 #define EHCI_PORTSC_PIC_GREEN (2 << EHCI_PORTSC_PIC_SHIFT) /* Green */ 152 #define EHCI_PORTSC_PTC_SHIFT (16) /* Bits 16-19: Port Test Control */ 153 #define EHCI_PORTSC_PTC_MASK (15 << EHCI_PORTSC_PTC_SHIFT) 154 #define EHCI_PORTSC_PTC_DISABLED (0 << EHCI_PORTSC_PTC_SHIFT) /* Test mode not enabled */ 155 #define EHCI_PORTSC_PTC_JSTATE (1 << EHCI_PORTSC_PTC_SHIFT) /* Test J_STATE */ 156 #define EHCI_PORTSC_PTC_KSTATE (2 << EHCI_PORTSC_PTC_SHIFT) /* Test K_STATE */ 157 #define EHCI_PORTSC_PTC_SE0NAK (3 << EHCI_PORTSC_PTC_SHIFT) /* Test SE0_NAK */ 158 #define EHCI_PORTSC_PTC_PACKET (4 << EHCI_PORTSC_PTC_SHIFT) /* Test Packet */ 159 #define EHCI_PORTSC_PTC_ENABLE (5 << EHCI_PORTSC_PTC_SHIFT) /* Test FORCE_ENABLE */ 160 #define EHCI_PORTSC_WKCCNTE (1 << 20) /* Bit 20: Wake on Connect Enable */ 161 #define EHCI_PORTSC_WKDSCNNTE (1 << 21) /* Bit 21: Wake on Disconnect Enable */ 162 #define EHCI_PORTSC_WKOCE (1 << 22) /* Bit 22: Wake on Over-current Enable */ 163 /* Bits 23-31: Reserved */ 164 165 #define EHCI_PORTSC_ALLINTS (EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | \ 166 EHCI_PORTSC_OCC | EHCI_PORTSC_RESUME) 167 168 /* Queue Head. Paragraph 3.6 */ 169 170 /* Queue Head Horizontal Link Pointer: Queue Head DWord 0. Table 3-19 */ 171 172 #define QH_HLP_END 0x1 173 174 #define QH_HLP_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0) /* Isochronous Transfer Descriptor */ 175 #define QH_HLP_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2) /* Queue Head */ 176 #define QH_HLP_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4) /* Split Transaction Isochronous Transfer Descriptor */ 177 #define QH_HLP_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6) /* Frame Span Traversal Node */ 178 179 /* Endpoint Characteristics: Queue Head DWord 1. Table 3-19 */ 180 181 #define QH_EPCHAR_DEVADDR_SHIFT (0) /* Bitx 0-6: Device Address */ 182 #define QH_EPCHAR_DEVADDR_MASK (0x7f << QH_EPCHAR_DEVADDR_SHIFT) 183 #define QH_EPCHAR_I (1 << 7) /* Bit 7: Inactivate on Next Transaction */ 184 #define QH_EPCHAR_ENDPT_SHIFT (8) /* Bitx 8-11: Endpoint Number */ 185 #define QH_EPCHAR_ENDPT_MASK (15 << QH_EPCHAR_ENDPT_SHIFT) 186 #define QH_EPCHAR_EPS_SHIFT (12) /* Bitx 12-13: Endpoint Speed */ 187 #define QH_EPCHAR_EPS_MASK (3 << QH_EPCHAR_EPS_SHIFT) 188 #define QH_EPCHAR_EPS_FULL (0 << QH_EPCHAR_EPS_SHIFT) /* Full-Speed (12Mbs) */ 189 #define QH_EPCHAR_EPS_LOW (1 << QH_EPCHAR_EPS_SHIFT) /* Low-Speed (1.5Mbs) */ 190 #define QH_EPCHAR_EPS_HIGH (2 << QH_EPCHAR_EPS_SHIFT) /* High-Speed (480 Mb/s) */ 191 #define QH_EPCHAR_DTC (1 << 14) /* Bit 14: Data Toggle Control */ 192 #define QH_EPCHAR_H (1 << 15) /* Bit 15: Head of Reclamation List Flag */ 193 #define QH_EPCHAR_MAXPKT_SHIFT (16) /* Bitx 16-26: Maximum Packet Length */ 194 #define QH_EPCHAR_MAXPKT_MASK (0x7ff << QH_EPCHAR_MAXPKT_SHIFT) 195 #define QH_EPCHAR_C (1 << 27) /* Bit 27: Control Endpoint Flag */ 196 #define QH_EPCHAR_RL_SHIFT (28) /* Bitx 28-31: Nak Count Reload */ 197 #define QH_EPCHAR_RL_MASK (15 << QH_EPCHAR_RL_SHIFT) 198 199 /* Endpoint Capabilities: Queue Head DWord 2. Table 3-20 */ 200 201 #define QH_EPCAPS_SSMASK_SHIFT (0) /* Bitx 0-7: Interrupt Schedule Mask (Frame S-mask) */ 202 #define QH_EPCAPS_SSMASK_MASK (0xff << QH_EPCAPS_SSMASK_SHIFT) 203 #define QH_EPCAPS_SSMASK(n) ((n) << QH_EPCAPS_SSMASK_SHIFT) 204 #define QH_EPCAPS_SCMASK_SHIFT (8) /* Bitx 8-15: Split Completion Mask (Frame C-Mask) */ 205 #define QH_EPCAPS_SCMASK_MASK (0xff << QH_EPCAPS_SCMASK_SHIFT) 206 #define QH_EPCAPS_SCMASK(n) ((n) << QH_EPCAPS_SCMASK_SHIFT) 207 #define QH_EPCAPS_HUBADDR_SHIFT (16) /* Bitx 16-22: Hub Address */ 208 #define QH_EPCAPS_HUBADDR_MASK (0x7f << QH_EPCAPS_HUBADDR_SHIFT) 209 #define QH_EPCAPS_HUBADDR(n) ((n) << QH_EPCAPS_HUBADDR_SHIFT) 210 #define QH_EPCAPS_PORT_SHIFT (23) /* Bit 23-29: Port Number */ 211 #define QH_EPCAPS_PORT_MASK (0x7f << QH_EPCAPS_PORT_SHIFT) 212 #define QH_EPCAPS_PORT(n) ((n) << QH_EPCAPS_PORT_SHIFT) 213 #define QH_EPCAPS_MULT_SHIFT (30) /* Bit 30-31: High-Bandwidth Pipe Multiplier */ 214 #define QH_EPCAPS_MULT_MASK (3 << QH_EPCAPS_MULT_SHIFT) 215 #define QH_EPCAPS_MULT(n) ((n) << QH_EPCAPS_MULT_SHIFT) 216 217 /* qTD Token. Paragraph 3.5.3 */ 218 219 #define QTD_LIST_END 1 220 221 #define QTD_TOKEN_STATUS_SHIFT (0) /* Bits 0-7: Status */ 222 #define QTD_TOKEN_STATUS_MASK (0xff << QTD_TOKEN_STATUS_SHIFT) 223 #define QTD_TOKEN_STATUS_PINGSTATE (1 << 0) /* Bit 0 Ping State */ 224 #define QTD_TOKEN_STATUS_ERR (1 << 0) /* Bit 0 Error */ 225 #define QTD_TOKEN_STATUS_SPLITXSTATE (1 << 1) /* Bit 1 Split Transaction State */ 226 #define QTD_TOKEN_STATUS_MMF (1 << 2) /* Bit 2 Missed Micro-Frame */ 227 #define QTD_TOKEN_STATUS_XACTERR (1 << 3) /* Bit 3 Transaction Error */ 228 #define QTD_TOKEN_STATUS_BABBLE (1 << 4) /* Bit 4 Babble Detected */ 229 #define QTD_TOKEN_STATUS_DBERR (1 << 5) /* Bit 5 Data Buffer Error */ 230 #define QTD_TOKEN_STATUS_HALTED (1 << 6) /* Bit 6 Halted */ 231 #define QTD_TOKEN_STATUS_ACTIVE (1 << 7) /* Bit 7 Active */ 232 #define QTD_TOKEN_STATUS_ERRORS (0x78 << QTD_TOKEN_STATUS_SHIFT) 233 #define QTD_TOKEN_PID_SHIFT (8) /* Bits 8-9: PID Code */ 234 #define QTD_TOKEN_PID_MASK (3 << QTD_TOKEN_PID_SHIFT) 235 #define QTD_TOKEN_PID_OUT (0 << QTD_TOKEN_PID_SHIFT) /* OUT Token generates token (E1H) */ 236 #define QTD_TOKEN_PID_IN (1 << QTD_TOKEN_PID_SHIFT) /* IN Token generates token (69H) */ 237 #define QTD_TOKEN_PID_SETUP (2 << QTD_TOKEN_PID_SHIFT) /* SETUP Token generates token (2DH) */ 238 #define QTD_TOKEN_CERR_SHIFT (10) /* Bits 10-11: Error Counter */ 239 #define QTD_TOKEN_CERR_MASK (3 << QTD_TOKEN_CERR_SHIFT) 240 #define QTD_TOKEN_CPAGE_SHIFT (12) /* Bits 12-14: Current Page */ 241 #define QTD_TOKEN_CPAGE_MASK (7 << QTD_TOKEN_CPAGE_SHIFT) 242 #define QTD_TOKEN_IOC (1 << 15) /* Bit 15: Interrupt On Complete */ 243 #define QTD_TOKEN_NBYTES_SHIFT (16) /* Bits 16-30: Total Bytes to Transfer */ 244 #define QTD_TOKEN_NBYTES_MASK (0x7fff << QTD_TOKEN_NBYTES_SHIFT) 245 #define QTD_TOKEN_TOGGLE (1 << 31) /* Bit 31: Data Toggle */ 246 247 /* Isochronous (High-Speed) Transfer Descriptor (iTD). Paragraph 3.3 */ 248 249 /* iTD Next Link Pointer. Paragraph 3.3.1 */ 250 251 #define ITD_NLP_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0) 252 #define ITD_NLP_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2) 253 #define ITD_NLP_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4) 254 #define ITD_NLP_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6) 255 256 /* iTD Transaction Status and Control List. Paragraph 3.3.2 */ 257 #define ITD_TSCL_XOFFS_SHIFT (0) /* Bits 0-11: Transaction X offset */ 258 #define ITD_TSCL_XOFFS_MASK (0xfff << ITD_TSCL_XOFFS_SHIFT) 259 #define ITD_TSCL_PG_SHIFT (12) /* Bits 12-14: Page select */ 260 #define ITD_TSCL_PG_MASK (7 << ITD_TSCL_PG_SHIFT) 261 #define ITD_TSCL_IOC (1 << 15) /* Bit 15: Interrupt On Comp */ 262 #define ITD_TSCL_LENGTH_SHIFT (16) /* Bits 16-27: Transaction length */ 263 #define ITD_TSCL_LENGTH_MASK (0xfff << ITD_TSCL_LENGTH_SHIFT) 264 #define ITD_TSCL_STATUS_SHIFT (28) /* Bits 28-31: Transaction status */ 265 #define ITD_TSCL_STATUS_MASK (15 << ITD_TSCL_STATUS_SHIFT) 266 #define ITD_TSCL_STATUS_XACTERR (1 << 28) /* Bit 28: Transaction error */ 267 #define ITD_TSCL_STATUS_BABBLE (1 << 29) /* Bit 29: Babble Detected */ 268 #define ITD_TSCL_STATUS_DBERROR (1 << 30) /* Bit 30: Data Buffer Error */ 269 #define ITD_TSCL_STATUS_ACTIVE (1 << 31) /* Bit 31: Active error */ 270 271 /* iTD Buffer Page Pointer List. Paragraph 3.3.4 */ 272 273 /* iTD Buffer Pointer Page 0. Table 3-4 */ 274 275 #define ITD_BUFPTR0_DEVADDR_SHIFT (0) /* Bits 0-6: Device Address */ 276 #define ITD_BUFPTR0_DEVADDR_MASK (0x7f << ITD_BUFPTR0_DEVADDR_SHIFT) 277 #define ITD_BUFPTR0_ENDPT_SHIFT (8) /* Bits 8-11: Endpoint Number */ 278 #define ITD_BUFPTR0_ENDPT_MASK (15 << ITD_BUFPTR0_ENDPT_SHIFT) 279 280 /* iTD Buffer Pointer Page 1. Table 3-5 */ 281 282 #define ITD_BUFPTR1_MAXPKT_SHIFT (0) /* Bits 0-10: Maximum Packet Size */ 283 #define ITD_BUFPTR1_MAXPKT_MASK (0x7ff << ITD_BUFPTR1_MAXPKT_SHIFT) 284 #define ITD_BUFPTR1_DIRIN (1 << 11) /* Bit 11: Direction 1=IN */ 285 #define ITD_BUFPTR1_DIROUT (0) /* Bit 11: Direction 0=OUT */ 286 287 /* iTD Buffer Pointer Page 2. Table 3-6 */ 288 289 #define ITD_BUFPTR2_MULTI_SHIFT (0) /* Bits 0-1: Multi */ 290 #define ITD_BUFPTR2_MULTI_MASK (3 << ITD_BUFPTR2_MULTI_SHIFT) 291 #define ITD_BUFPTR2_MULTI_1 (1 << ITD_BUFPTR2_MULTI_SHIFT) /* One transaction per micro-frame */ 292 #define ITD_BUFPTR2_MULTI_2 (2 << ITD_BUFPTR2_MULTI_SHIFT) /* Two transactions per micro-frame */ 293 #define ITD_BUFPTR2_MULTI_3 (3 << ITD_BUFPTR2_MULTI_SHIFT) /* Three transactions per micro-frame */ 294 295 /* Registers ****************************************************************/ 296 297 /* Host Controller Capability Registers. 298 * This register block must be positioned at a well known address. 299 */ 300 301 struct ehci_hccr { 302 volatile uint8_t caplength; /* 0x00: Capability Register Length */ 303 volatile uint8_t reserved; /* 0x01: reserved */ 304 volatile uint16_t hciversion; /* 0x02: Interface Version Number */ 305 volatile uint32_t hcsparams; /* 0x04: Structural Parameters */ 306 volatile uint32_t hccparams; /* 0x08: Capability Parameters */ 307 volatile uint8_t hcspportroute[8]; /* 0x0c: Companion Port Route Description */ 308 }; 309 310 /* Host Controller Operational Registers. 311 * This register block is positioned at an offset of 'caplength' from the 312 * beginning of the Host Controller Capability Registers. 313 */ 314 315 struct ehci_hcor { 316 volatile uint32_t usbcmd; /* 0x00: USB Command */ 317 volatile uint32_t usbsts; /* 0x04: USB Status */ 318 volatile uint32_t usbintr; /* 0x08: USB Interrupt Enable */ 319 volatile uint32_t frindex; /* 0x0c: USB Frame Index */ 320 volatile uint32_t ctrldssegment; /* 0x10: 4G Segment Selector */ 321 volatile uint32_t periodiclistbase; /* 0x14: Frame List Base Address */ 322 volatile uint32_t asynclistaddr; /* 0x18: Next Asynchronous List Address */ 323 #ifndef CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE 324 uint32_t reserved[9]; 325 #endif 326 volatile uint32_t configflag; /* 0x40: Configured Flag Register */ 327 volatile uint32_t portsc[15]; /* 0x44: Port Status/Control */ 328 }; 329 330 /* USB2 Debug Port Register Interface. 331 * This register block is normally found via the PCI capabalities. 332 * In non-PCI implementions, you need apriori information about the 333 * location of these registers. 334 */ 335 336 struct ehci_debug { 337 uint32_t psc; /* 0x00: Debug Port Control/Status Register */ 338 uint32_t pids; /* 0x04: Debug USB PIDs Register */ 339 uint32_t data[2]; /* 0x08: Debug Data buffer Registers */ 340 uint32_t addr; /* 0x10: Device Address Register */ 341 }; 342 343 /* Data Structures **********************************************************/ 344 345 /* Queue Element Transfer Descriptor (qTD). Paragraph 3.5 */ 346 347 struct ehci_qtd { 348 uint32_t next_qtd; /* 0x00-0x03: Next qTD Pointer */ 349 uint32_t alt_next_qtd; /* 0x04-0x07: Alternate Next qTD Pointer */ 350 uint32_t token; /* 0x08-0x0b: qTD Token */ 351 uint32_t bpl[5]; /* 0x0c-0x1c: Buffer Page Pointer List */ 352 }; 353 354 #define SIZEOF_EHCI_QTD (32) /* 8*sizeof(uint32_t) */ 355 356 /* Queue Head. Paragraph 3.6 */ 357 358 struct ehci_qh { 359 uint32_t hlp; /* 0x00-0x03: Queue Head Horizontal Link Pointer */ 360 uint32_t epchar; /* 0x04-0x07: Endpoint Characteristics */ 361 uint32_t epcap; /* 0x08-0x0b: Endpoint Capabilities */ 362 uint32_t curr_qtd; /* 0x0c-0x0f: Current qTD Pointer */ 363 struct ehci_qtd overlay; /* 0x10-0x2c: Transfer overlay */ 364 }; 365 366 #define SIZEOF_EHCI_QH (48) /* 4*sizeof(uint32_t) + 32 */ 367 368 /* Isochronous (High-Speed) Transfer Descriptor (iTD). 369 * Paragraph 3.3. Must be aligned to 32-byte boundaries. 370 */ 371 372 struct ehci_itd { 373 uint32_t nlp; /* 0x00-0x03: Next link pointer */ 374 uint32_t tscl[8]; /* 0x04-0x23: Transaction Status and Control List */ 375 uint32_t bpl[7]; /* 0x24-0x3c: Buffer Page Pointer List */ 376 }; 377 378 #define SIZEOF_EHCI_ITD (64) /* 16*sizeof(uint32_t) */ 379 380 /* Split Transaction Isochronous Transfer Descriptor (siTD). Paragraph 3.4 */ 381 382 struct ehci_sitd { 383 uint32_t nlp; /* 0x00-0x03: Next link pointer */ 384 uint32_t epchar; /* 0x04-0x07: Endpoint and Transaction Translator Characteristics */ 385 uint32_t mfsc; /* 0x08-0x0b: Micro-frame Schedule Control */ 386 uint32_t tsc; /* 0x0c-0x0f: Transfer Status and Control */ 387 uint32_t bpl[2]; /* 0x10-0x17: Buffer Pointer List */ 388 uint32_t blp; /* 0x18-0x1b: Back link pointer */ 389 }; 390 391 #define SIZEOF_EHCI_SITD (28) /* 7*sizeof(uint32_t) */ 392 393 #endif /* __INCLUDE_NUTTX_USB_EHCI_H */ 394