1 /* 2 * Copyright (c) 2024, sakumisu 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef USBH_ASIX_H 7 #define USBH_ASIX_H 8 9 /* ASIX AX8817X based USB 2.0 Ethernet Devices */ 10 11 #define AX_CMD_SET_SW_MII 0x06 12 #define AX_CMD_READ_MII_REG 0x07 13 #define AX_CMD_WRITE_MII_REG 0x08 14 #define AX_CMD_STATMNGSTS_REG 0x09 15 #define AX_CMD_SET_HW_MII 0x0a 16 #define AX_CMD_READ_EEPROM 0x0b 17 #define AX_CMD_WRITE_EEPROM 0x0c 18 #define AX_CMD_WRITE_ENABLE 0x0d 19 #define AX_CMD_WRITE_DISABLE 0x0e 20 #define AX_CMD_READ_RX_CTL 0x0f 21 #define AX_CMD_WRITE_RX_CTL 0x10 22 #define AX_CMD_READ_IPG012 0x11 23 #define AX_CMD_WRITE_IPG0 0x12 24 #define AX_CMD_WRITE_IPG1 0x13 25 #define AX_CMD_READ_NODE_ID 0x13 26 #define AX_CMD_WRITE_NODE_ID 0x14 27 #define AX_CMD_WRITE_IPG2 0x14 28 #define AX_CMD_WRITE_MULTI_FILTER 0x16 29 #define AX88172_CMD_READ_NODE_ID 0x17 30 #define AX_CMD_READ_PHY_ID 0x19 31 #define AX_CMD_READ_MEDIUM_STATUS 0x1a 32 #define AX_CMD_WRITE_MEDIUM_MODE 0x1b 33 #define AX_CMD_READ_MONITOR_MODE 0x1c 34 #define AX_CMD_WRITE_MONITOR_MODE 0x1d 35 #define AX_CMD_READ_GPIOS 0x1e 36 #define AX_CMD_WRITE_GPIOS 0x1f 37 #define AX_CMD_SW_RESET 0x20 38 #define AX_CMD_SW_PHY_STATUS 0x21 39 #define AX_CMD_SW_PHY_SELECT 0x22 40 #define AX_QCTCTRL 0x2A 41 42 #define AX_CHIPCODE_MASK 0x70 43 #define AX_AX88772_CHIPCODE 0x00 44 #define AX_AX88772A_CHIPCODE 0x10 45 #define AX_AX88772B_CHIPCODE 0x20 46 #define AX_HOST_EN 0x01 47 48 #define AX_PHYSEL_PSEL 0x01 49 #define AX_PHYSEL_SSMII 0 50 #define AX_PHYSEL_SSEN 0x10 51 52 #define AX_PHY_SELECT_MASK (BIT(3) | BIT(2)) 53 #define AX_PHY_SELECT_INTERNAL 0 54 #define AX_PHY_SELECT_EXTERNAL BIT(2) 55 56 #define AX_MONITOR_MODE 0x01 57 #define AX_MONITOR_LINK 0x02 58 #define AX_MONITOR_MAGIC 0x04 59 #define AX_MONITOR_HSFS 0x10 60 61 /* AX88172 Medium Status Register values */ 62 #define AX88172_MEDIUM_FD 0x02 63 #define AX88172_MEDIUM_TX 0x04 64 #define AX88172_MEDIUM_FC 0x10 65 #define AX88172_MEDIUM_DEFAULT \ 66 (AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC) 67 68 #define AX_MCAST_FILTER_SIZE 8 69 #define AX_MAX_MCAST 64 70 71 #define AX_SWRESET_CLEAR 0x00 72 #define AX_SWRESET_RR 0x01 73 #define AX_SWRESET_RT 0x02 74 #define AX_SWRESET_PRTE 0x04 75 #define AX_SWRESET_PRL 0x08 76 #define AX_SWRESET_BZ 0x10 77 #define AX_SWRESET_IPRL 0x20 78 #define AX_SWRESET_IPPD 0x40 79 80 #define AX88772_IPG0_DEFAULT 0x15 81 #define AX88772_IPG1_DEFAULT 0x0c 82 #define AX88772_IPG2_DEFAULT 0x12 83 84 /* AX88772 & AX88178 Medium Mode Register */ 85 #define AX_MEDIUM_PF 0x0080 86 #define AX_MEDIUM_JFE 0x0040 87 #define AX_MEDIUM_TFC 0x0020 88 #define AX_MEDIUM_RFC 0x0010 89 #define AX_MEDIUM_ENCK 0x0008 90 #define AX_MEDIUM_AC 0x0004 91 #define AX_MEDIUM_FD 0x0002 92 #define AX_MEDIUM_GM 0x0001 93 #define AX_MEDIUM_SM 0x1000 94 #define AX_MEDIUM_SBP 0x0800 95 #define AX_MEDIUM_PS 0x0200 96 #define AX_MEDIUM_RE 0x0100 97 98 #define AX88178_MEDIUM_DEFAULT \ 99 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ 100 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ 101 AX_MEDIUM_RE) 102 103 #define AX88772_MEDIUM_DEFAULT \ 104 (AX_MEDIUM_FD | AX_MEDIUM_PS | \ 105 AX_MEDIUM_AC | AX_MEDIUM_RE) 106 107 /* AX88772 & AX88178 RX_CTL values */ 108 #define AX_RX_CTL_SO 0x0080 109 #define AX_RX_CTL_AP 0x0020 110 #define AX_RX_CTL_AM 0x0010 111 #define AX_RX_CTL_AB 0x0008 112 #define AX_RX_CTL_SEP 0x0004 113 #define AX_RX_CTL_AMALL 0x0002 114 #define AX_RX_CTL_PRO 0x0001 115 #define AX_RX_CTL_MFB_2048 0x0000 116 #define AX_RX_CTL_MFB_4096 0x0100 117 #define AX_RX_CTL_MFB_8192 0x0200 118 #define AX_RX_CTL_MFB_16384 0x0300 119 120 #define AX_DEFAULT_RX_CTL (AX_RX_CTL_SO | AX_RX_CTL_AB) 121 122 /* GPIO 0 .. 2 toggles */ 123 #define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */ 124 #define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */ 125 #define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */ 126 #define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */ 127 #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ 128 #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ 129 #define AX_GPIO_RESERVED 0x40 /* Reserved */ 130 #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ 131 132 #define AX_EEPROM_MAGIC 0xdeadbeef 133 #define AX_EEPROM_LEN 0x200 134 135 #define AX_EMBD_PHY_ADDR 0x10 136 137 struct usbh_asix { 138 struct usbh_hubport *hport; 139 struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ 140 struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ 141 struct usb_endpoint_descriptor *intin; /* INTR IN endpoint */ 142 struct usbh_urb bulkout_urb; 143 struct usbh_urb bulkin_urb; 144 struct usbh_urb intin_urb; 145 146 uint8_t intf; 147 char *name; 148 uint8_t phy_addr; 149 uint8_t embd_phy; 150 uint8_t chipcode; 151 uint16_t mac_capabilities; 152 153 bool connect_status; 154 uint8_t mac[6]; 155 156 void *user_data; 157 }; 158 159 #ifdef __cplusplus 160 extern "C" { 161 #endif 162 163 int usbh_asix_get_connect_status(struct usbh_asix *asix_class); 164 165 void usbh_asix_run(struct usbh_asix *asix_class); 166 void usbh_asix_stop(struct usbh_asix *asix_class); 167 168 uint8_t *usbh_asix_get_eth_txbuf(void); 169 int usbh_asix_eth_output(uint32_t buflen); 170 void usbh_asix_eth_input(uint8_t *buf, uint32_t buflen); 171 void usbh_asix_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV); 172 173 #ifdef __cplusplus 174 } 175 #endif 176 177 #endif /* USBH_ASIX_H */