1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: usdhc1_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for usdhc1 module.
usdhc1_iomux_config(void)34 void usdhc1_iomux_config(void)
35 {
36 // Config usdhc1.SD1_CD_B to pad GPIO01(T4)
37 // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_WR(0x00000006);
38 // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR(0x0001B0B0);
39 // Mux Register:
40 // IOMUXC_SW_MUX_CTL_PAD_GPIO01(0x020E0210)
41 // SION [4] - Software Input On Field Reset: DISABLED
42 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
43 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
44 // ENABLED (1) - Force input path of pad.
45 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
46 // Select iomux modes to be used for pad.
47 // ALT0 (0) - Select instance: esai signal: ESAI_RX_CLK
48 // ALT1 (1) - Select instance: wdog2 signal: WDOG2_B
49 // ALT2 (2) - Select instance: kpp signal: KEY_ROW5
50 // ALT3 (3) - Select instance: usb signal: USB_OTG_ID
51 // ALT4 (4) - Select instance: pwm2 signal: PWM2_OUT
52 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO01
53 // ALT6 (6) - Select instance: usdhc1 signal: SD1_CD_B
54 HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_WR(
55 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION_V(DISABLED) |
56 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE_V(ALT6));
57 // Pad Control Register:
58 // IOMUXC_SW_PAD_CTL_PAD_GPIO01(0x020E05E0)
59 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
60 // DISABLED (0) - CMOS input
61 // ENABLED (1) - Schmitt trigger input
62 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
63 // 100K_OHM_PD (0) - 100K Ohm Pull Down
64 // 47K_OHM_PU (1) - 47K Ohm Pull Up
65 // 100K_OHM_PU (2) - 100K Ohm Pull Up
66 // 22K_OHM_PU (3) - 22K Ohm Pull Up
67 // PUE [13] - Pull / Keep Select Field Reset: PULL
68 // KEEP (0) - Keeper Enabled
69 // PULL (1) - Pull Enabled
70 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
71 // DISABLED (0) - Pull/Keeper Disabled
72 // ENABLED (1) - Pull/Keeper Enabled
73 // ODE [11] - Open Drain Enable Field Reset: DISABLED
74 // Enables open drain of the pin.
75 // DISABLED (0) - Output is CMOS.
76 // ENABLED (1) - Output is Open Drain.
77 // SPEED [7:6] - Speed Field Reset: 100MHZ
78 // RESERVED0 (0) - Reserved
79 // 50MHZ (1) - Low (50 MHz)
80 // 100MHZ (2) - Medium (100 MHz)
81 // 200MHZ (3) - Maximum (200 MHz)
82 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
83 // HIZ (0) - HI-Z
84 // 240_OHM (1) - 240 Ohm
85 // 120_OHM (2) - 120 Ohm
86 // 80_OHM (3) - 80 Ohm
87 // 60_OHM (4) - 60 Ohm
88 // 48_OHM (5) - 48 Ohm
89 // 40_OHM (6) - 40 Ohm
90 // 34_OHM (7) - 34 Ohm
91 // SRE [0] - Slew Rate Field Reset: SLOW
92 // Slew rate control.
93 // SLOW (0) - Slow Slew Rate
94 // FAST (1) - Fast Slew Rate
95 HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR(
96 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS_V(ENABLED) |
97 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS_V(100K_OHM_PU) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE_V(PULL) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE_V(ENABLED) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE_V(DISABLED) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED_V(100MHZ) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE_V(40_OHM) |
103 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE_V(SLOW));
104
105 // Config usdhc1.SD1_CLK to pad SD1_CLK(D20)
106 // HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_WR(0x00000000);
107 // HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR(0x0001B0B0);
108 // HW_IOMUXC_USDHC1_CARD_CLK_IN_SELECT_INPUT_WR(0x00000001);
109 // Mux Register:
110 // IOMUXC_SW_MUX_CTL_PAD_SD1_CLK(0x020E02DC)
111 // SION [4] - Software Input On Field Reset: DISABLED
112 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
113 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
114 // ENABLED (1) - Force input path of pad.
115 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
116 // Select iomux modes to be used for pad.
117 // ALT0 (0) - Select instance: usdhc1 signal: SD1_CLK
118 // ALT3 (3) - Select instance: gpt signal: GPT_CLKIN
119 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO20
120 HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_WR(
121 BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION_V(DISABLED) |
122 BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_V(ALT0));
123 // Pad Control Register:
124 // IOMUXC_SW_PAD_CTL_PAD_SD1_CLK(0x020E06C4)
125 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
126 // DISABLED (0) - CMOS input
127 // ENABLED (1) - Schmitt trigger input
128 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
129 // 100K_OHM_PD (0) - 100K Ohm Pull Down
130 // 47K_OHM_PU (1) - 47K Ohm Pull Up
131 // 100K_OHM_PU (2) - 100K Ohm Pull Up
132 // 22K_OHM_PU (3) - 22K Ohm Pull Up
133 // PUE [13] - Pull / Keep Select Field Reset: PULL
134 // KEEP (0) - Keeper Enabled
135 // PULL (1) - Pull Enabled
136 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
137 // DISABLED (0) - Pull/Keeper Disabled
138 // ENABLED (1) - Pull/Keeper Enabled
139 // ODE [11] - Open Drain Enable Field Reset: DISABLED
140 // Enables open drain of the pin.
141 // DISABLED (0) - Output is CMOS.
142 // ENABLED (1) - Output is Open Drain.
143 // SPEED [7:6] - Speed Field Reset: 100MHZ
144 // RESERVED0 (0) - Reserved
145 // 50MHZ (1) - Low (50 MHz)
146 // 100MHZ (2) - Medium (100 MHz)
147 // 200MHZ (3) - Maximum (200 MHz)
148 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
149 // HIZ (0) - HI-Z
150 // 240_OHM (1) - 240 Ohm
151 // 120_OHM (2) - 120 Ohm
152 // 80_OHM (3) - 80 Ohm
153 // 60_OHM (4) - 60 Ohm
154 // 48_OHM (5) - 48 Ohm
155 // 40_OHM (6) - 40 Ohm
156 // 34_OHM (7) - 34 Ohm
157 // SRE [0] - Slew Rate Field Reset: SLOW
158 // Slew rate control.
159 // SLOW (0) - Slow Slew Rate
160 // FAST (1) - Fast Slew Rate
161 HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR(
162 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS_V(ENABLED) |
163 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS_V(100K_OHM_PU) |
164 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE_V(PULL) |
165 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE_V(ENABLED) |
166 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE_V(DISABLED) |
167 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED_V(100MHZ) |
168 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_V(40_OHM) |
169 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE_V(SLOW));
170 // Pad SD1_CLK is involved in Daisy Chain.
171 // Input Select Register:
172 // IOMUXC_USDHC1_CARD_CLK_IN_SELECT_INPUT(0x020E0928)
173 // DAISY [0] - MUX Mode Select Field Reset: RESERVED0
174 // Selecting Pads Involved in Daisy Chain.
175 // RESERVED0 (0) - This field value is reserved.
176 // SD1_CLK_ALT0 (1) - Select signal usdhc1 SD1_CLK as input from pad SD1_CLK(ALT0).
177 HW_IOMUXC_USDHC1_CARD_CLK_IN_SELECT_INPUT_WR(
178 BF_IOMUXC_USDHC1_CARD_CLK_IN_SELECT_INPUT_DAISY_V(SD1_CLK_ALT0));
179
180 // Config usdhc1.SD1_CMD to pad SD1_CMD(B21)
181 // HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_WR(0x00000000);
182 // HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR(0x0001B0B0);
183 // Mux Register:
184 // IOMUXC_SW_MUX_CTL_PAD_SD1_CMD(0x020E02E0)
185 // SION [4] - Software Input On Field Reset: DISABLED
186 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
187 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
188 // ENABLED (1) - Force input path of pad.
189 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
190 // Select iomux modes to be used for pad.
191 // ALT0 (0) - Select instance: usdhc1 signal: SD1_CMD
192 // ALT2 (2) - Select instance: pwm4 signal: PWM4_OUT
193 // ALT3 (3) - Select instance: gpt signal: GPT_COMPARE1
194 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO18
195 HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_WR(
196 BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION_V(DISABLED) |
197 BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_V(ALT0));
198 // Pad Control Register:
199 // IOMUXC_SW_PAD_CTL_PAD_SD1_CMD(0x020E06C8)
200 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
201 // DISABLED (0) - CMOS input
202 // ENABLED (1) - Schmitt trigger input
203 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
204 // 100K_OHM_PD (0) - 100K Ohm Pull Down
205 // 47K_OHM_PU (1) - 47K Ohm Pull Up
206 // 100K_OHM_PU (2) - 100K Ohm Pull Up
207 // 22K_OHM_PU (3) - 22K Ohm Pull Up
208 // PUE [13] - Pull / Keep Select Field Reset: PULL
209 // KEEP (0) - Keeper Enabled
210 // PULL (1) - Pull Enabled
211 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
212 // DISABLED (0) - Pull/Keeper Disabled
213 // ENABLED (1) - Pull/Keeper Enabled
214 // ODE [11] - Open Drain Enable Field Reset: DISABLED
215 // Enables open drain of the pin.
216 // DISABLED (0) - Output is CMOS.
217 // ENABLED (1) - Output is Open Drain.
218 // SPEED [7:6] - Speed Field Reset: 100MHZ
219 // RESERVED0 (0) - Reserved
220 // 50MHZ (1) - Low (50 MHz)
221 // 100MHZ (2) - Medium (100 MHz)
222 // 200MHZ (3) - Maximum (200 MHz)
223 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
224 // HIZ (0) - HI-Z
225 // 240_OHM (1) - 240 Ohm
226 // 120_OHM (2) - 120 Ohm
227 // 80_OHM (3) - 80 Ohm
228 // 60_OHM (4) - 60 Ohm
229 // 48_OHM (5) - 48 Ohm
230 // 40_OHM (6) - 40 Ohm
231 // 34_OHM (7) - 34 Ohm
232 // SRE [0] - Slew Rate Field Reset: SLOW
233 // Slew rate control.
234 // SLOW (0) - Slow Slew Rate
235 // FAST (1) - Fast Slew Rate
236 HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR(
237 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS_V(ENABLED) |
238 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS_V(100K_OHM_PU) |
239 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE_V(PULL) |
240 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE_V(ENABLED) |
241 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE_V(DISABLED) |
242 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED_V(100MHZ) |
243 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_V(40_OHM) |
244 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE_V(SLOW));
245
246 // Config usdhc1.SD1_DATA0 to pad SD1_DATA0(A21)
247 // HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_WR(0x00000000);
248 // HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR(0x0001B0B0);
249 // Mux Register:
250 // IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0(0x020E02E4)
251 // SION [4] - Software Input On Field Reset: DISABLED
252 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
253 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
254 // ENABLED (1) - Force input path of pad.
255 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
256 // Select iomux modes to be used for pad.
257 // ALT0 (0) - Select instance: usdhc1 signal: SD1_DATA0
258 // ALT3 (3) - Select instance: gpt signal: GPT_CAPTURE1
259 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO16
260 HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_WR(
261 BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_V(DISABLED) |
262 BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_V(ALT0));
263 // Pad Control Register:
264 // IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0(0x020E06CC)
265 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
266 // DISABLED (0) - CMOS input
267 // ENABLED (1) - Schmitt trigger input
268 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
269 // 100K_OHM_PD (0) - 100K Ohm Pull Down
270 // 47K_OHM_PU (1) - 47K Ohm Pull Up
271 // 100K_OHM_PU (2) - 100K Ohm Pull Up
272 // 22K_OHM_PU (3) - 22K Ohm Pull Up
273 // PUE [13] - Pull / Keep Select Field Reset: PULL
274 // KEEP (0) - Keeper Enabled
275 // PULL (1) - Pull Enabled
276 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
277 // DISABLED (0) - Pull/Keeper Disabled
278 // ENABLED (1) - Pull/Keeper Enabled
279 // ODE [11] - Open Drain Enable Field Reset: DISABLED
280 // Enables open drain of the pin.
281 // DISABLED (0) - Output is CMOS.
282 // ENABLED (1) - Output is Open Drain.
283 // SPEED [7:6] - Speed Field Reset: 100MHZ
284 // RESERVED0 (0) - Reserved
285 // 50MHZ (1) - Low (50 MHz)
286 // 100MHZ (2) - Medium (100 MHz)
287 // 200MHZ (3) - Maximum (200 MHz)
288 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
289 // HIZ (0) - HI-Z
290 // 240_OHM (1) - 240 Ohm
291 // 120_OHM (2) - 120 Ohm
292 // 80_OHM (3) - 80 Ohm
293 // 60_OHM (4) - 60 Ohm
294 // 48_OHM (5) - 48 Ohm
295 // 40_OHM (6) - 40 Ohm
296 // 34_OHM (7) - 34 Ohm
297 // SRE [0] - Slew Rate Field Reset: SLOW
298 // Slew rate control.
299 // SLOW (0) - Slow Slew Rate
300 // FAST (1) - Fast Slew Rate
301 HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR(
302 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_V(ENABLED) |
303 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_V(100K_OHM_PU) |
304 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE_V(PULL) |
305 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE_V(ENABLED) |
306 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE_V(DISABLED) |
307 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_V(100MHZ) |
308 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_V(40_OHM) |
309 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_V(SLOW));
310
311 // Config usdhc1.SD1_DATA1 to pad SD1_DATA1(C20)
312 // HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_WR(0x00000000);
313 // HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR(0x0001B0B0);
314 // Mux Register:
315 // IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1(0x020E02E8)
316 // SION [4] - Software Input On Field Reset: DISABLED
317 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
318 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
319 // ENABLED (1) - Force input path of pad.
320 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
321 // Select iomux modes to be used for pad.
322 // ALT0 (0) - Select instance: usdhc1 signal: SD1_DATA1
323 // ALT2 (2) - Select instance: pwm3 signal: PWM3_OUT
324 // ALT3 (3) - Select instance: gpt signal: GPT_CAPTURE2
325 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO17
326 HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_WR(
327 BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_V(DISABLED) |
328 BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_V(ALT0));
329 // Pad Control Register:
330 // IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1(0x020E06D0)
331 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
332 // DISABLED (0) - CMOS input
333 // ENABLED (1) - Schmitt trigger input
334 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
335 // 100K_OHM_PD (0) - 100K Ohm Pull Down
336 // 47K_OHM_PU (1) - 47K Ohm Pull Up
337 // 100K_OHM_PU (2) - 100K Ohm Pull Up
338 // 22K_OHM_PU (3) - 22K Ohm Pull Up
339 // PUE [13] - Pull / Keep Select Field Reset: PULL
340 // KEEP (0) - Keeper Enabled
341 // PULL (1) - Pull Enabled
342 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
343 // DISABLED (0) - Pull/Keeper Disabled
344 // ENABLED (1) - Pull/Keeper Enabled
345 // ODE [11] - Open Drain Enable Field Reset: DISABLED
346 // Enables open drain of the pin.
347 // DISABLED (0) - Output is CMOS.
348 // ENABLED (1) - Output is Open Drain.
349 // SPEED [7:6] - Speed Field Reset: 100MHZ
350 // RESERVED0 (0) - Reserved
351 // 50MHZ (1) - Low (50 MHz)
352 // 100MHZ (2) - Medium (100 MHz)
353 // 200MHZ (3) - Maximum (200 MHz)
354 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
355 // HIZ (0) - HI-Z
356 // 240_OHM (1) - 240 Ohm
357 // 120_OHM (2) - 120 Ohm
358 // 80_OHM (3) - 80 Ohm
359 // 60_OHM (4) - 60 Ohm
360 // 48_OHM (5) - 48 Ohm
361 // 40_OHM (6) - 40 Ohm
362 // 34_OHM (7) - 34 Ohm
363 // SRE [0] - Slew Rate Field Reset: SLOW
364 // Slew rate control.
365 // SLOW (0) - Slow Slew Rate
366 // FAST (1) - Fast Slew Rate
367 HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR(
368 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_V(ENABLED) |
369 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_V(100K_OHM_PU) |
370 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE_V(PULL) |
371 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE_V(ENABLED) |
372 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE_V(DISABLED) |
373 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_V(100MHZ) |
374 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_V(40_OHM) |
375 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_V(SLOW));
376
377 // Config usdhc1.SD1_DATA2 to pad SD1_DATA2(E19)
378 // HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_WR(0x00000000);
379 // HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR(0x0001B0B0);
380 // Mux Register:
381 // IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2(0x020E02EC)
382 // SION [4] - Software Input On Field Reset: DISABLED
383 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
384 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
385 // ENABLED (1) - Force input path of pad.
386 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
387 // Select iomux modes to be used for pad.
388 // ALT0 (0) - Select instance: usdhc1 signal: SD1_DATA2
389 // ALT2 (2) - Select instance: gpt signal: GPT_COMPARE2
390 // ALT3 (3) - Select instance: pwm2 signal: PWM2_OUT
391 // ALT4 (4) - Select instance: wdog1 signal: WDOG1_B
392 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO19
393 // ALT6 (6) - Select instance: wdog1 signal: WDOG1_RESET_B_DEB
394 HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_WR(
395 BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION_V(DISABLED) |
396 BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_V(ALT0));
397 // Pad Control Register:
398 // IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2(0x020E06D4)
399 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
400 // DISABLED (0) - CMOS input
401 // ENABLED (1) - Schmitt trigger input
402 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
403 // 100K_OHM_PD (0) - 100K Ohm Pull Down
404 // 47K_OHM_PU (1) - 47K Ohm Pull Up
405 // 100K_OHM_PU (2) - 100K Ohm Pull Up
406 // 22K_OHM_PU (3) - 22K Ohm Pull Up
407 // PUE [13] - Pull / Keep Select Field Reset: PULL
408 // KEEP (0) - Keeper Enabled
409 // PULL (1) - Pull Enabled
410 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
411 // DISABLED (0) - Pull/Keeper Disabled
412 // ENABLED (1) - Pull/Keeper Enabled
413 // ODE [11] - Open Drain Enable Field Reset: DISABLED
414 // Enables open drain of the pin.
415 // DISABLED (0) - Output is CMOS.
416 // ENABLED (1) - Output is Open Drain.
417 // SPEED [7:6] - Speed Field Reset: 100MHZ
418 // RESERVED0 (0) - Reserved
419 // 50MHZ (1) - Low (50 MHz)
420 // 100MHZ (2) - Medium (100 MHz)
421 // 200MHZ (3) - Maximum (200 MHz)
422 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
423 // HIZ (0) - HI-Z
424 // 240_OHM (1) - 240 Ohm
425 // 120_OHM (2) - 120 Ohm
426 // 80_OHM (3) - 80 Ohm
427 // 60_OHM (4) - 60 Ohm
428 // 48_OHM (5) - 48 Ohm
429 // 40_OHM (6) - 40 Ohm
430 // 34_OHM (7) - 34 Ohm
431 // SRE [0] - Slew Rate Field Reset: SLOW
432 // Slew rate control.
433 // SLOW (0) - Slow Slew Rate
434 // FAST (1) - Fast Slew Rate
435 HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR(
436 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS_V(ENABLED) |
437 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS_V(100K_OHM_PU) |
438 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE_V(PULL) |
439 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE_V(ENABLED) |
440 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE_V(DISABLED) |
441 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED_V(100MHZ) |
442 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_V(40_OHM) |
443 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE_V(SLOW));
444
445 // Config usdhc1.SD1_DATA3 to pad SD1_DATA3(F18)
446 // HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_WR(0x00000000);
447 // HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR(0x0001B0B0);
448 // Mux Register:
449 // IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3(0x020E02F0)
450 // SION [4] - Software Input On Field Reset: DISABLED
451 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
452 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
453 // ENABLED (1) - Force input path of pad.
454 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
455 // Select iomux modes to be used for pad.
456 // ALT0 (0) - Select instance: usdhc1 signal: SD1_DATA3
457 // ALT2 (2) - Select instance: gpt signal: GPT_COMPARE3
458 // ALT3 (3) - Select instance: pwm1 signal: PWM1_OUT
459 // ALT4 (4) - Select instance: wdog2 signal: WDOG2_B
460 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO21
461 // ALT6 (6) - Select instance: wdog2 signal: WDOG2_RESET_B_DEB
462 HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_WR(
463 BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION_V(DISABLED) |
464 BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_V(ALT0));
465 // Pad Control Register:
466 // IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3(0x020E06D8)
467 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
468 // DISABLED (0) - CMOS input
469 // ENABLED (1) - Schmitt trigger input
470 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
471 // 100K_OHM_PD (0) - 100K Ohm Pull Down
472 // 47K_OHM_PU (1) - 47K Ohm Pull Up
473 // 100K_OHM_PU (2) - 100K Ohm Pull Up
474 // 22K_OHM_PU (3) - 22K Ohm Pull Up
475 // PUE [13] - Pull / Keep Select Field Reset: PULL
476 // KEEP (0) - Keeper Enabled
477 // PULL (1) - Pull Enabled
478 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
479 // DISABLED (0) - Pull/Keeper Disabled
480 // ENABLED (1) - Pull/Keeper Enabled
481 // ODE [11] - Open Drain Enable Field Reset: DISABLED
482 // Enables open drain of the pin.
483 // DISABLED (0) - Output is CMOS.
484 // ENABLED (1) - Output is Open Drain.
485 // SPEED [7:6] - Speed Field Reset: 100MHZ
486 // RESERVED0 (0) - Reserved
487 // 50MHZ (1) - Low (50 MHz)
488 // 100MHZ (2) - Medium (100 MHz)
489 // 200MHZ (3) - Maximum (200 MHz)
490 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
491 // HIZ (0) - HI-Z
492 // 240_OHM (1) - 240 Ohm
493 // 120_OHM (2) - 120 Ohm
494 // 80_OHM (3) - 80 Ohm
495 // 60_OHM (4) - 60 Ohm
496 // 48_OHM (5) - 48 Ohm
497 // 40_OHM (6) - 40 Ohm
498 // 34_OHM (7) - 34 Ohm
499 // SRE [0] - Slew Rate Field Reset: SLOW
500 // Slew rate control.
501 // SLOW (0) - Slow Slew Rate
502 // FAST (1) - Fast Slew Rate
503 HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR(
504 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS_V(ENABLED) |
505 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS_V(100K_OHM_PU) |
506 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE_V(PULL) |
507 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE_V(ENABLED) |
508 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE_V(DISABLED) |
509 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED_V(100MHZ) |
510 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_V(40_OHM) |
511 BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE_V(SLOW));
512
513 // Config usdhc1.SD1_DATA4 to pad NAND_DATA00(A18)
514 // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR(0x00000001);
515 // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(0x0001B0B0);
516 // Mux Register:
517 // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00(0x020E0284)
518 // SION [4] - Software Input On Field Reset: DISABLED
519 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
520 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
521 // ENABLED (1) - Force input path of pad.
522 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
523 // Select iomux modes to be used for pad.
524 // ALT0 (0) - Select instance: gpmi signal: NAND_DATA00
525 // ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA4
526 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO00
527 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR(
528 BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION_V(DISABLED) |
529 BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_V(ALT1));
530 // Pad Control Register:
531 // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00(0x020E066C)
532 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
533 // DISABLED (0) - CMOS input
534 // ENABLED (1) - Schmitt trigger input
535 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
536 // 100K_OHM_PD (0) - 100K Ohm Pull Down
537 // 47K_OHM_PU (1) - 47K Ohm Pull Up
538 // 100K_OHM_PU (2) - 100K Ohm Pull Up
539 // 22K_OHM_PU (3) - 22K Ohm Pull Up
540 // PUE [13] - Pull / Keep Select Field Reset: PULL
541 // KEEP (0) - Keeper Enabled
542 // PULL (1) - Pull Enabled
543 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
544 // DISABLED (0) - Pull/Keeper Disabled
545 // ENABLED (1) - Pull/Keeper Enabled
546 // ODE [11] - Open Drain Enable Field Reset: DISABLED
547 // Enables open drain of the pin.
548 // DISABLED (0) - Output is CMOS.
549 // ENABLED (1) - Output is Open Drain.
550 // SPEED [7:6] - Speed Field Reset: 100MHZ
551 // RESERVED0 (0) - Reserved
552 // 50MHZ (1) - Low (50 MHz)
553 // 100MHZ (2) - Medium (100 MHz)
554 // 200MHZ (3) - Maximum (200 MHz)
555 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
556 // HIZ (0) - HI-Z
557 // 240_OHM (1) - 240 Ohm
558 // 120_OHM (2) - 120 Ohm
559 // 80_OHM (3) - 80 Ohm
560 // 60_OHM (4) - 60 Ohm
561 // 48_OHM (5) - 48 Ohm
562 // 40_OHM (6) - 40 Ohm
563 // 34_OHM (7) - 34 Ohm
564 // SRE [0] - Slew Rate Field Reset: SLOW
565 // Slew rate control.
566 // SLOW (0) - Slow Slew Rate
567 // FAST (1) - Fast Slew Rate
568 HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(
569 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS_V(ENABLED) |
570 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_V(100K_OHM_PU) |
571 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE_V(PULL) |
572 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE_V(ENABLED) |
573 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE_V(DISABLED) |
574 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_V(100MHZ) |
575 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_V(40_OHM) |
576 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE_V(SLOW));
577
578 // Config usdhc1.SD1_DATA5 to pad NAND_DATA01(C17)
579 // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR(0x00000001);
580 // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR(0x0001B0B0);
581 // Mux Register:
582 // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01(0x020E0288)
583 // SION [4] - Software Input On Field Reset: DISABLED
584 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
585 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
586 // ENABLED (1) - Force input path of pad.
587 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
588 // Select iomux modes to be used for pad.
589 // ALT0 (0) - Select instance: gpmi signal: NAND_DATA01
590 // ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA5
591 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO01
592 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR(
593 BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION_V(DISABLED) |
594 BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_V(ALT1));
595 // Pad Control Register:
596 // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01(0x020E0670)
597 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
598 // DISABLED (0) - CMOS input
599 // ENABLED (1) - Schmitt trigger input
600 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
601 // 100K_OHM_PD (0) - 100K Ohm Pull Down
602 // 47K_OHM_PU (1) - 47K Ohm Pull Up
603 // 100K_OHM_PU (2) - 100K Ohm Pull Up
604 // 22K_OHM_PU (3) - 22K Ohm Pull Up
605 // PUE [13] - Pull / Keep Select Field Reset: PULL
606 // KEEP (0) - Keeper Enabled
607 // PULL (1) - Pull Enabled
608 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
609 // DISABLED (0) - Pull/Keeper Disabled
610 // ENABLED (1) - Pull/Keeper Enabled
611 // ODE [11] - Open Drain Enable Field Reset: DISABLED
612 // Enables open drain of the pin.
613 // DISABLED (0) - Output is CMOS.
614 // ENABLED (1) - Output is Open Drain.
615 // SPEED [7:6] - Speed Field Reset: 100MHZ
616 // RESERVED0 (0) - Reserved
617 // 50MHZ (1) - Low (50 MHz)
618 // 100MHZ (2) - Medium (100 MHz)
619 // 200MHZ (3) - Maximum (200 MHz)
620 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
621 // HIZ (0) - HI-Z
622 // 240_OHM (1) - 240 Ohm
623 // 120_OHM (2) - 120 Ohm
624 // 80_OHM (3) - 80 Ohm
625 // 60_OHM (4) - 60 Ohm
626 // 48_OHM (5) - 48 Ohm
627 // 40_OHM (6) - 40 Ohm
628 // 34_OHM (7) - 34 Ohm
629 // SRE [0] - Slew Rate Field Reset: SLOW
630 // Slew rate control.
631 // SLOW (0) - Slow Slew Rate
632 // FAST (1) - Fast Slew Rate
633 HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR(
634 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS_V(ENABLED) |
635 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_V(100K_OHM_PU) |
636 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE_V(PULL) |
637 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE_V(ENABLED) |
638 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE_V(DISABLED) |
639 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_V(100MHZ) |
640 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_V(40_OHM) |
641 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE_V(SLOW));
642
643 // Config usdhc1.SD1_DATA6 to pad NAND_DATA02(F16)
644 // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR(0x00000001);
645 // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR(0x0001B0B0);
646 // Mux Register:
647 // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02(0x020E028C)
648 // SION [4] - Software Input On Field Reset: DISABLED
649 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
650 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
651 // ENABLED (1) - Force input path of pad.
652 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
653 // Select iomux modes to be used for pad.
654 // ALT0 (0) - Select instance: gpmi signal: NAND_DATA02
655 // ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA6
656 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO02
657 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR(
658 BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION_V(DISABLED) |
659 BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_V(ALT1));
660 // Pad Control Register:
661 // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02(0x020E0674)
662 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
663 // DISABLED (0) - CMOS input
664 // ENABLED (1) - Schmitt trigger input
665 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
666 // 100K_OHM_PD (0) - 100K Ohm Pull Down
667 // 47K_OHM_PU (1) - 47K Ohm Pull Up
668 // 100K_OHM_PU (2) - 100K Ohm Pull Up
669 // 22K_OHM_PU (3) - 22K Ohm Pull Up
670 // PUE [13] - Pull / Keep Select Field Reset: PULL
671 // KEEP (0) - Keeper Enabled
672 // PULL (1) - Pull Enabled
673 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
674 // DISABLED (0) - Pull/Keeper Disabled
675 // ENABLED (1) - Pull/Keeper Enabled
676 // ODE [11] - Open Drain Enable Field Reset: DISABLED
677 // Enables open drain of the pin.
678 // DISABLED (0) - Output is CMOS.
679 // ENABLED (1) - Output is Open Drain.
680 // SPEED [7:6] - Speed Field Reset: 100MHZ
681 // RESERVED0 (0) - Reserved
682 // 50MHZ (1) - Low (50 MHz)
683 // 100MHZ (2) - Medium (100 MHz)
684 // 200MHZ (3) - Maximum (200 MHz)
685 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
686 // HIZ (0) - HI-Z
687 // 240_OHM (1) - 240 Ohm
688 // 120_OHM (2) - 120 Ohm
689 // 80_OHM (3) - 80 Ohm
690 // 60_OHM (4) - 60 Ohm
691 // 48_OHM (5) - 48 Ohm
692 // 40_OHM (6) - 40 Ohm
693 // 34_OHM (7) - 34 Ohm
694 // SRE [0] - Slew Rate Field Reset: SLOW
695 // Slew rate control.
696 // SLOW (0) - Slow Slew Rate
697 // FAST (1) - Fast Slew Rate
698 HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR(
699 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS_V(ENABLED) |
700 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_V(100K_OHM_PU) |
701 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE_V(PULL) |
702 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE_V(ENABLED) |
703 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE_V(DISABLED) |
704 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_V(100MHZ) |
705 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_V(40_OHM) |
706 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE_V(SLOW));
707
708 // Config usdhc1.SD1_DATA7 to pad NAND_DATA03(D17)
709 // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR(0x00000001);
710 // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR(0x0001B0B0);
711 // Mux Register:
712 // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03(0x020E0290)
713 // SION [4] - Software Input On Field Reset: DISABLED
714 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
715 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
716 // ENABLED (1) - Force input path of pad.
717 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
718 // Select iomux modes to be used for pad.
719 // ALT0 (0) - Select instance: gpmi signal: NAND_DATA03
720 // ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA7
721 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO03
722 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR(
723 BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION_V(DISABLED) |
724 BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_V(ALT1));
725 // Pad Control Register:
726 // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03(0x020E0678)
727 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
728 // DISABLED (0) - CMOS input
729 // ENABLED (1) - Schmitt trigger input
730 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
731 // 100K_OHM_PD (0) - 100K Ohm Pull Down
732 // 47K_OHM_PU (1) - 47K Ohm Pull Up
733 // 100K_OHM_PU (2) - 100K Ohm Pull Up
734 // 22K_OHM_PU (3) - 22K Ohm Pull Up
735 // PUE [13] - Pull / Keep Select Field Reset: PULL
736 // KEEP (0) - Keeper Enabled
737 // PULL (1) - Pull Enabled
738 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
739 // DISABLED (0) - Pull/Keeper Disabled
740 // ENABLED (1) - Pull/Keeper Enabled
741 // ODE [11] - Open Drain Enable Field Reset: DISABLED
742 // Enables open drain of the pin.
743 // DISABLED (0) - Output is CMOS.
744 // ENABLED (1) - Output is Open Drain.
745 // SPEED [7:6] - Speed Field Reset: 100MHZ
746 // RESERVED0 (0) - Reserved
747 // 50MHZ (1) - Low (50 MHz)
748 // 100MHZ (2) - Medium (100 MHz)
749 // 200MHZ (3) - Maximum (200 MHz)
750 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
751 // HIZ (0) - HI-Z
752 // 240_OHM (1) - 240 Ohm
753 // 120_OHM (2) - 120 Ohm
754 // 80_OHM (3) - 80 Ohm
755 // 60_OHM (4) - 60 Ohm
756 // 48_OHM (5) - 48 Ohm
757 // 40_OHM (6) - 40 Ohm
758 // 34_OHM (7) - 34 Ohm
759 // SRE [0] - Slew Rate Field Reset: SLOW
760 // Slew rate control.
761 // SLOW (0) - Slow Slew Rate
762 // FAST (1) - Fast Slew Rate
763 HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR(
764 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS_V(ENABLED) |
765 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_V(100K_OHM_PU) |
766 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE_V(PULL) |
767 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE_V(ENABLED) |
768 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE_V(DISABLED) |
769 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_V(100MHZ) |
770 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_V(40_OHM) |
771 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE_V(SLOW));
772 }
773