1 /*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "vglite_support.h"
9 #include "fsl_clock.h"
10 #include "vg_lite.h"
11 #include "vg_lite_platform.h"
12 #include "display_support.h"
13 /*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16 #define MAX_CONTIGUOUS_SIZE 0x200000
17 /*******************************************************************************
18 * Prototypes
19 ******************************************************************************/
20
21 /*******************************************************************************
22 * Variables
23 ******************************************************************************/
24
25 static uint32_t registerMemBase = 0x41800000;
26 static uint32_t gpu_mem_base = 0x0;
27
28 /*
29 * In case custom VGLite memory parameters are used, the application needs to
30 * allocate and publish the VGLite heap base, its size and the size of the
31 * command buffer(s) using the following global variables:
32 */
33 extern void *vglite_heap_base;
34 extern uint32_t vglite_heap_size;
35
36 #if (CUSTOM_VGLITE_MEMORY_CONFIG == 0)
37 /* VGLite driver heap */
38 AT_NONCACHEABLE_SECTION_ALIGN(static uint8_t contiguous_mem[MAX_CONTIGUOUS_SIZE], FRAME_BUFFER_ALIGN);
39
40 void *vglite_heap_base = &contiguous_mem;
41 uint32_t vglite_heap_size = MAX_CONTIGUOUS_SIZE;
42 #endif /* CUSTOM_VGLITE_MEMORY_CONFIG */
43
44 /*******************************************************************************
45 * Code
46 ******************************************************************************/
GPU2D_IRQHandler(void)47 void GPU2D_IRQHandler(void)
48 {
49 vg_lite_IRQHandler();
50 }
51
BOARD_InitVGliteClock(void)52 static status_t BOARD_InitVGliteClock(void)
53 {
54 const clock_root_config_t gc355ClockConfig = {
55 .clockOff = false,
56 .mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut, /*!< 984MHz */
57 .div = 2,
58 };
59
60 CLOCK_SetRootClock(kCLOCK_Root_Gc355, &gc355ClockConfig);
61
62 CLOCK_GetRootClockFreq(kCLOCK_Root_Gc355);
63
64 CLOCK_EnableClock(kCLOCK_Gpu2d);
65
66 NVIC_SetPriority(GPU2D_IRQn, 3);
67
68 EnableIRQ(GPU2D_IRQn);
69
70 return kStatus_Success;
71 }
72
BOARD_PrepareVGLiteController(void)73 status_t BOARD_PrepareVGLiteController(void)
74 {
75 status_t status;
76
77 status = BOARD_InitVGliteClock();
78
79 if (kStatus_Success != status)
80 {
81 return status;
82 }
83
84 vg_lite_init_mem(registerMemBase, gpu_mem_base, vglite_heap_base, vglite_heap_size);
85
86 return kStatus_Success;
87 }
88