1 /* 2 * Allwinner SoCs display driver. 3 * 4 * Copyright (C) 2016 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef __SUNXI_DISPLAY2_H__ 12 #define __SUNXI_DISPLAY2_H__ 13 #include <typedef.h> 14 #include <stdbool.h> 15 16 struct disp_manager; 17 struct disp_device; 18 struct disp_smbl; 19 struct disp_enhance; 20 struct disp_capture; 21 22 struct disp_color { 23 unsigned char alpha; 24 unsigned char red; 25 unsigned char green; 26 unsigned char blue; 27 }; 28 29 struct disp_rect { 30 int x; 31 int y; 32 unsigned int width; 33 unsigned int height; 34 }; 35 36 struct disp_rectsz { 37 unsigned int width; 38 unsigned int height; 39 }; 40 41 struct disp_position { 42 int x; 43 int y; 44 }; 45 46 typedef enum disp_pixel_format { 47 DISP_FORMAT_ARGB_8888 = 0x00, /* MSB A-R-G-B LSB */ 48 DISP_FORMAT_ABGR_8888 = 0x01, 49 DISP_FORMAT_RGBA_8888 = 0x02, 50 DISP_FORMAT_BGRA_8888 = 0x03, 51 DISP_FORMAT_XRGB_8888 = 0x04, 52 DISP_FORMAT_XBGR_8888 = 0x05, 53 DISP_FORMAT_RGBX_8888 = 0x06, 54 DISP_FORMAT_BGRX_8888 = 0x07, 55 DISP_FORMAT_RGB_888 = 0x08, 56 DISP_FORMAT_BGR_888 = 0x09, 57 DISP_FORMAT_RGB_565 = 0x0a, 58 DISP_FORMAT_BGR_565 = 0x0b, 59 DISP_FORMAT_ARGB_4444 = 0x0c, 60 DISP_FORMAT_ABGR_4444 = 0x0d, 61 DISP_FORMAT_RGBA_4444 = 0x0e, 62 DISP_FORMAT_BGRA_4444 = 0x0f, 63 DISP_FORMAT_ARGB_1555 = 0x10, 64 DISP_FORMAT_ABGR_1555 = 0x11, 65 DISP_FORMAT_RGBA_5551 = 0x12, 66 DISP_FORMAT_BGRA_5551 = 0x13, 67 DISP_FORMAT_A2R10G10B10 = 0x14, 68 DISP_FORMAT_A2B10G10R10 = 0x15, 69 DISP_FORMAT_R10G10B10A2 = 0x16, 70 DISP_FORMAT_B10G10R10A2 = 0x17, 71 DISP_FORMAT_1bpp_palette_LE = 0x18, 72 DISP_FORMAT_2bpp_palette_LE = 0x19, 73 DISP_FORMAT_4bpp_palette_LE = 0x1a, 74 DISP_FORMAT_8bpp_palette_LE = 0x1b, 75 /* 76 * SP: semi-planar 77 * P:planar 78 * I:interleaved 79 * UVUV: U in the LSBs; 80 * VUVU: V in the LSBs 81 */ 82 DISP_FORMAT_YUV444_I_AYUV = 0x40, /* MSB A-Y-U-V LSB */ 83 DISP_FORMAT_YUV444_I_VUYA = 0x41, /* MSB V-U-Y-A LSB */ 84 DISP_FORMAT_YUV422_I_YVYU = 0x42, /* MSB Y-V-Y-U LSB */ 85 DISP_FORMAT_YUV422_I_YUYV = 0x43, /* MSB Y-U-Y-V LSB */ 86 DISP_FORMAT_YUV422_I_UYVY = 0x44, /* MSB U-Y-V-Y LSB */ 87 DISP_FORMAT_YUV422_I_VYUY = 0x45, /* MSB V-Y-U-Y LSB */ 88 DISP_FORMAT_YUV444_P = 0x46, /* MSB P3-2-1-0 LSB, YYYY UUUU VVVV */ 89 DISP_FORMAT_YUV422_P = 0x47, /* MSB P3-2-1-0 LSB YYYY UU VV */ 90 DISP_FORMAT_YUV420_P = 0x48, /* MSB P3-2-1-0 LSB YYYY U V (yu12)*/ 91 DISP_FORMAT_YUV411_P = 0x49, /* MSB P3-2-1-0 LSB YYYY U V */ 92 DISP_FORMAT_YUV422_SP_UVUV = 0x4a, /* MSB V-U-V-U LSB */ 93 DISP_FORMAT_YUV422_SP_VUVU = 0x4b, /* MSB U-V-U-V LSB */ 94 DISP_FORMAT_YUV420_SP_UVUV = 0x4c, 95 DISP_FORMAT_YUV420_SP_VUVU = 0x4d, 96 DISP_FORMAT_YUV411_SP_UVUV = 0x4e, 97 DISP_FORMAT_YUV411_SP_VUVU = 0x4f, 98 DISP_FORMAT_8BIT_GRAY = 0x50, 99 DISP_FORMAT_YUV444_I_AYUV_10BIT = 0x51, 100 DISP_FORMAT_YUV444_I_VUYA_10BIT = 0x52, 101 DISP_FORMAT_YUV422_I_YVYU_10BIT = 0x53, 102 DISP_FORMAT_YUV422_I_YUYV_10BIT = 0x54, 103 DISP_FORMAT_YUV422_I_UYVY_10BIT = 0x55, 104 DISP_FORMAT_YUV422_I_VYUY_10BIT = 0x56, 105 DISP_FORMAT_YUV444_P_10BIT = 0x57, 106 DISP_FORMAT_YUV422_P_10BIT = 0x58, 107 DISP_FORMAT_YUV420_P_10BIT = 0x59, 108 DISP_FORMAT_YUV411_P_10BIT = 0x5a, 109 DISP_FORMAT_YUV422_SP_UVUV_10BIT = 0x5b, 110 DISP_FORMAT_YUV422_SP_VUVU_10BIT = 0x5c, 111 DISP_FORMAT_YUV420_SP_UVUV_10BIT = 0x5d, 112 DISP_FORMAT_YUV420_SP_VUVU_10BIT = 0x5e, 113 DISP_FORMAT_YUV411_SP_UVUV_10BIT = 0x5f, 114 DISP_FORMAT_YUV411_SP_VUVU_10BIT = 0x60, 115 DISP_FORMAT_YUV420_P_YV12 = 0x61, /* MSB P3-2-1-0 LSB YYYY V U DISP_FORMAT_YUV420_P */ 116 DISP_FORMAT_YUV420_P_YU12 = 0x62, /* MSB P3-2-1-0 LSB YYYY U V DISP_FORMAT_YUV420_P*/ 117 118 DISP_FORMAT_CSIRGB, 119 DISP_UNKNOWN_VALUE, 120 DISP_FORMAT_MAX, 121 }__disp_pixel_fmt_t; 122 123 enum disp_3d_out_mode { 124 DISP_3D_OUT_MODE_CI_1 = 0x5, /* column interlaved 1 */ 125 DISP_3D_OUT_MODE_CI_2 = 0x6, /* column interlaved 2 */ 126 DISP_3D_OUT_MODE_CI_3 = 0x7, /* column interlaved 3 */ 127 DISP_3D_OUT_MODE_CI_4 = 0x8, /* column interlaved 4 */ 128 DISP_3D_OUT_MODE_LIRGB = 0x9, /* line interleaved rgb */ 129 130 DISP_3D_OUT_MODE_TB = 0x0, /* top bottom */ 131 DISP_3D_OUT_MODE_FP = 0x1, /* frame packing */ 132 DISP_3D_OUT_MODE_SSF = 0x2, /* side by side full */ 133 DISP_3D_OUT_MODE_SSH = 0x3, /* side by side half */ 134 DISP_3D_OUT_MODE_LI = 0x4, /* line interleaved */ 135 DISP_3D_OUT_MODE_FA = 0xa, /* field alternative */ 136 }; 137 138 enum disp_color_space { 139 DISP_UNDEF = 0x00, 140 DISP_UNDEF_F = 0x01, 141 DISP_GBR = 0x100, 142 DISP_BT709 = 0x101, 143 DISP_FCC = 0x102, 144 DISP_BT470BG = 0x103, 145 DISP_BT601 = 0x104, 146 DISP_SMPTE240M = 0x105, 147 DISP_YCGCO = 0x106, 148 DISP_BT2020NC = 0x107, 149 DISP_BT2020C = 0x108, 150 DISP_GBR_F = 0x200, 151 DISP_BT709_F = 0x201, 152 DISP_FCC_F = 0x202, 153 DISP_BT470BG_F = 0x203, 154 DISP_BT601_F = 0x204, 155 DISP_SMPTE240M_F = 0x205, 156 DISP_YCGCO_F = 0x206, 157 DISP_BT2020NC_F = 0x207, 158 DISP_BT2020C_F = 0x208, 159 DISP_RESERVED = 0x300, 160 DISP_RESERVED_F = 0x301, 161 }; 162 163 typedef enum disp_color_space __disp_cs_mode_t; 164 165 enum disp_csc_type { 166 DISP_CSC_TYPE_RGB = 0, 167 DISP_CSC_TYPE_YUV444 = 1, 168 DISP_CSC_TYPE_YUV422 = 2, 169 DISP_CSC_TYPE_YUV420 = 3, 170 }; 171 172 enum disp_data_bits { 173 DISP_DATA_8BITS = 0, 174 DISP_DATA_10BITS = 1, 175 DISP_DATA_12BITS = 2, 176 DISP_DATA_16BITS = 3, 177 }; 178 enum disp_dvi_hdmi { 179 DISP_DVI_HDMI_UNDEFINED = 0, 180 DISP_DVI = 1, 181 DISP_HDMI = 2, 182 }; 183 enum disp_scan_info { 184 DISP_SCANINFO_NO_DATA = 0, 185 OVERSCAN = 1, 186 UNDERSCAN = 2, 187 }; 188 enum disp_color_range { 189 DISP_COLOR_RANGE_DEFAULT = 0, /*default*/ 190 DISP_COLOR_RANGE_0_255 = 1, 191 DISP_COLOR_RANGE_16_235 = 2, 192 }; 193 194 enum disp_output_type { 195 DISP_OUTPUT_TYPE_NONE = 0, 196 DISP_OUTPUT_TYPE_LCD = 1, 197 DISP_OUTPUT_TYPE_TV = 2, 198 DISP_OUTPUT_TYPE_HDMI = 4, 199 DISP_OUTPUT_TYPE_VGA = 8, 200 DISP_OUTPUT_TYPE_VDPO = 16, 201 DISP_OUTPUT_TYPE_EDP = 32, /*16 for vdpo*/ 202 }; 203 204 enum disp_tv_mode { 205 DISP_TV_MOD_480I = 0, 206 DISP_TV_MOD_576I = 1, 207 DISP_TV_MOD_480P = 2, 208 DISP_TV_MOD_576P = 3, 209 DISP_TV_MOD_720P_50HZ = 4, 210 DISP_TV_MOD_720P_60HZ = 5, 211 DISP_TV_MOD_1080I_50HZ = 6, 212 DISP_TV_MOD_1080I_60HZ = 7, 213 DISP_TV_MOD_1080P_24HZ = 8, 214 DISP_TV_MOD_1080P_50HZ = 9, 215 DISP_TV_MOD_1080P_60HZ = 0xa, 216 DISP_TV_MOD_1080P_24HZ_3D_FP = 0x17, 217 DISP_TV_MOD_720P_50HZ_3D_FP = 0x18, 218 DISP_TV_MOD_720P_60HZ_3D_FP = 0x19, 219 DISP_TV_MOD_1080P_25HZ = 0x1a, 220 DISP_TV_MOD_1080P_30HZ = 0x1b, 221 DISP_TV_MOD_PAL = 0xb, 222 DISP_TV_MOD_PAL_SVIDEO = 0xc, 223 DISP_TV_MOD_NTSC = 0xe, 224 DISP_TV_MOD_NTSC_SVIDEO = 0xf, 225 DISP_TV_MOD_PAL_M = 0x11, 226 DISP_TV_MOD_PAL_M_SVIDEO = 0x12, 227 DISP_TV_MOD_PAL_NC = 0x14, 228 DISP_TV_MOD_PAL_NC_SVIDEO = 0x15, 229 DISP_TV_MOD_3840_2160P_30HZ = 0x1c, 230 DISP_TV_MOD_3840_2160P_25HZ = 0x1d, 231 DISP_TV_MOD_3840_2160P_24HZ = 0x1e, 232 DISP_TV_MOD_4096_2160P_24HZ = 0x1f, 233 DISP_TV_MOD_4096_2160P_25HZ = 0x20, 234 DISP_TV_MOD_4096_2160P_30HZ = 0x21, 235 DISP_TV_MOD_3840_2160P_60HZ = 0x22, 236 DISP_TV_MOD_4096_2160P_60HZ = 0x23, 237 DISP_TV_MOD_3840_2160P_50HZ = 0x24, 238 DISP_TV_MOD_4096_2160P_50HZ = 0x25, 239 DISP_TV_MOD_2560_1440P_60HZ = 0x26, 240 DISP_TV_MOD_1440_2560P_70HZ = 0x27, 241 DISP_TV_MOD_1080_1920P_60HZ = 0x28, 242 DISP_TV_MOD_1280_1024P_60HZ = 0x41, 243 DISP_TV_MOD_1024_768P_60HZ = 0x42, 244 DISP_TV_MOD_900_540P_60HZ = 0x43, 245 DISP_TV_MOD_1920_720P_60HZ = 0x44, 246 /* vga */ 247 DISP_VGA_MOD_640_480P_60 = 0x50, 248 DISP_VGA_MOD_800_600P_60 = 0x51, 249 DISP_VGA_MOD_1024_768P_60 = 0x52, 250 DISP_VGA_MOD_1280_768P_60 = 0x53, 251 DISP_VGA_MOD_1280_800P_60 = 0x54, 252 DISP_VGA_MOD_1366_768P_60 = 0x55, 253 DISP_VGA_MOD_1440_900P_60 = 0x56, 254 DISP_VGA_MOD_1920_1080P_60 = 0x57, 255 DISP_VGA_MOD_1920_1200P_60 = 0x58, 256 DISP_TV_MOD_3840_1080P_30 = 0x59, 257 DISP_VGA_MOD_1280_720P_60 = 0x5a, 258 DISP_VGA_MOD_1600_900P_60 = 0x5b, 259 DISP_VGA_MOD_MAX_NUM = 0x5c, 260 DISP_TV_MODE_NUM, 261 }; 262 263 enum disp_exit_mode { 264 DISP_EXIT_MODE_CLEAN_ALL = 0, 265 DISP_EXIT_MODE_CLEAN_PARTLY = 1, /* only clean interrupt temply */ 266 }; 267 268 enum disp_buffer_flags { 269 DISP_BF_NORMAL = 0, /* non-stereo */ 270 DISP_BF_STEREO_TB = 1 << 0, /* stereo top-bottom */ 271 DISP_BF_STEREO_FP = 1 << 1, /* stereo frame packing */ 272 DISP_BF_STEREO_SSH = 1 << 2, /* stereo side by side half */ 273 DISP_BF_STEREO_SSF = 1 << 3, /* stereo side by side full */ 274 DISP_BF_STEREO_LI = 1 << 4, /* stereo line interlace */ 275 /* 276 * 2d plus depth to convert into 3d, 277 * left and right image using the same frame buffer 278 */ 279 DISP_BF_STEREO_2D_DEPTH = 1 << 5, 280 }; 281 282 enum disp_layer_mode { 283 LAYER_MODE_BUFFER = 0, 284 LAYER_MODE_COLOR = 1, 285 }; 286 287 enum disp_scan_flags { 288 DISP_SCAN_PROGRESSIVE = 0, 289 DISP_SCAN_INTERLACED_ODD_FLD_FIRST = 1 << 0, 290 DISP_SCAN_INTERLACED_EVEN_FLD_FIRST = 1 << 1, 291 }; 292 293 enum disp_eotf { 294 DISP_EOTF_RESERVED = 0x000, 295 DISP_EOTF_BT709 = 0x001, 296 DISP_EOTF_UNDEF = 0x002, 297 DISP_EOTF_GAMMA22 = 0x004, /* SDR */ 298 DISP_EOTF_GAMMA28 = 0x005, 299 DISP_EOTF_BT601 = 0x006, 300 DISP_EOTF_SMPTE240M = 0x007, 301 DISP_EOTF_LINEAR = 0x008, 302 DISP_EOTF_LOG100 = 0x009, 303 DISP_EOTF_LOG100S10 = 0x00a, 304 DISP_EOTF_IEC61966_2_4 = 0x00b, 305 DISP_EOTF_BT1361 = 0x00c, 306 DISP_EOTF_IEC61966_2_1 = 0X00d, 307 DISP_EOTF_BT2020_0 = 0x00e, 308 DISP_EOTF_BT2020_1 = 0x00f, 309 DISP_EOTF_SMPTE2084 = 0x010, /* HDR10 */ 310 DISP_EOTF_SMPTE428_1 = 0x011, 311 DISP_EOTF_ARIB_STD_B67 = 0x012, /* HLG */ 312 }; 313 /* disp_atw_mode - mode for asynchronous time warp 314 * 315 * @NORMAL_MODE: dual buffer, left eye and right eye buffer is individual 316 * @LEFT_RIGHT_MODE: single buffer, the left half of each line buffer 317 * is for left eye, the right half is for the right eye 318 * @UP_DOWN_MODE: single buffer, the first half of the total buffer 319 * is for the left eye, the second half is for the right eye 320 */ 321 enum disp_atw_mode { 322 NORMAL_MODE, 323 LEFT_RIGHT_MODE, 324 UP_DOWN_MODE, 325 }; 326 struct disp_output { 327 unsigned int type; 328 unsigned int mode; 329 }; 330 331 struct disp_rect64 { 332 long long x; 333 long long y; 334 long long width; 335 long long height; 336 }; 337 338 struct disp_lbc_info { 339 unsigned int is_lossy; 340 unsigned int rc_en; 341 unsigned int pitch; 342 unsigned int seg_bit; 343 }; 344 struct disp_fb_info { 345 /* address of frame buffer, 346 * single addr for interleaved fomart, 347 * double addr for semi-planar fomart 348 * triple addr for planar format 349 */ 350 unsigned long long addr[3]; 351 struct disp_rectsz size[3]; 352 /* align for 3 comonent,unit: bytes */ 353 unsigned int align[3]; 354 enum disp_pixel_format format; 355 enum disp_color_space color_space; /* color space */ 356 unsigned int trd_right_addr[3]; /* right address of 3d fb */ 357 bool pre_multiply; /* true: pre-multiply fb */ 358 struct disp_rect64 crop; /* crop rectangle boundaries */ 359 enum disp_buffer_flags flags; 360 enum disp_scan_flags scan; 361 unsigned int lbc_en; 362 struct disp_lbc_info lbc_info; 363 }; 364 365 struct disp_layer_info { 366 enum disp_layer_mode mode; 367 unsigned char zorder; 368 /* 0: pixel alpha; 1: global alpha; 2: global pixel alpha */ 369 unsigned char alpha_mode; 370 unsigned char alpha_value; /* global alpha value */ 371 struct disp_rect screen_win; /* display window on the screen */ 372 bool b_trd_out; /* 3d display */ 373 enum disp_3d_out_mode out_trd_mode; /* 3d display mode */ 374 union { 375 unsigned int color; /* valid when LAYER_MODE_COLOR */ 376 struct disp_fb_info fb; /* valid when LAYER_MODE_BUFFER */ 377 }; 378 379 unsigned int id; /* frame id, the id of frame display currently */ 380 }; 381 382 struct disp_layer_config { 383 struct disp_layer_info info; 384 bool enable; 385 unsigned int channel; 386 unsigned int layer_id; 387 }; 388 389 /* disp_atw_info - asynchronous time wrap infomation 390 * 391 * @used: indicate if the atw funtion is used 392 * @mode: atw mode 393 * @b_row: the row number of the micro block 394 * @b_col: the column number of the micro block 395 * @cof_fd: dma_buf fd for the buffer contaied coefficient for atw 396 */ 397 struct disp_atw_info { 398 bool used; 399 enum disp_atw_mode mode; 400 unsigned int b_row; 401 unsigned int b_col; 402 int cof_fd; 403 }; 404 /** 405 * disp_vdpo_config 406 */ 407 struct disp_vdpo_config { 408 unsigned int data_seq_sel; 409 unsigned int dclk_invt; 410 unsigned int dclk_dly_num; 411 unsigned int spl_type_u; 412 unsigned int spl_type_v; 413 }; 414 /* disp_fb_info2 - image buffer info v2 415 * 416 * @fd: dma_buf fd for frame buffer 417 * @size: size<width,height> for each buffer, unit:pixels 418 * @align: align for each buffer, unit:bytes 419 * @format: pixel format 420 * @color_space: color space 421 * @trd_right_fd: dma_buf fd for the right-eye frame buffer, 422 * valid when frame-packing 3d buffer input 423 * @pre_multiply: indicate the pixel use premultiplied alpha 424 * @crop: crop rectangle for buffer to be display 425 * @flag: indicate stereo/non-stereo buffer 426 * @scan: indicate interleave/progressive scan type, and the scan order 427 * @depth: depth perception for stereo image, only valid when stereo image input 428 * unit: pixel 429 * @fbd_en: indicate if enable fbd function 430 * @lbc_en: indicate if enable lbc function 431 * @metadata_fd: dma_buf fd for the buffer contained metadata for fbc/hdr 432 * @metadata_size: the size of metadata buffer, unit:bytes 433 * @metadata_flag: the flag to indicate the type of metadata buffer 434 * 0 : no metadata 435 * 1 << 0: hdr static metadata 436 * 1 << 1: hdr dynamic metadata 437 * 1 << 4: frame buffer compress(fbc) metadata 438 * x : all type could be "or" together 439 */ 440 struct disp_fb_info2 { 441 int fd; 442 struct disp_rectsz size[3]; 443 unsigned int align[3]; 444 enum disp_pixel_format format; 445 enum disp_color_space color_space; 446 int trd_right_fd; 447 bool pre_multiply; 448 struct disp_rect64 crop; 449 enum disp_buffer_flags flags; 450 enum disp_scan_flags scan; 451 enum disp_eotf eotf; 452 int depth; 453 unsigned int fbd_en; 454 unsigned int lbc_en; 455 struct disp_lbc_info lbc_info; 456 int metadata_fd; 457 unsigned int metadata_size; 458 unsigned int metadata_flag; 459 }; 460 461 /* disp_layer_info2 - layer info v2 462 * 463 * @mode: buffer/clolor mode, when in color mode, the layer is widthout buffer 464 * @zorder: the zorder of layer, 0~max-layer-number 465 * @alpha_mode: 466 * 0: pixel alpha; 467 * 1: global alpha 468 * 2: mixed alpha, compositing width pixel alpha before global alpha 469 * @alpha_value: global alpha value, valid when alpha_mode is not pixel alpha 470 * @screen_win: the rectangle on the screen for fb to be display 471 * @b_trd_out: indicate if 3d display output 472 * @out_trd_mode: 3d output mode, valid when b_trd_out is true 473 * @color: the color value to be display, valid when layer is in color mode 474 * @fb: the framebuffer info related width the layer, valid when in buffer mode 475 * @id: frame id, the user could get the frame-id display currently by 476 * DISP_LAYER_GET_FRAME_ID ioctl 477 * @atw: asynchronous time wrap information 478 */ 479 struct disp_layer_info2 { 480 enum disp_layer_mode mode; 481 unsigned char zorder; 482 unsigned char alpha_mode; 483 unsigned char alpha_value; 484 struct disp_rect screen_win; 485 bool b_trd_out; 486 enum disp_3d_out_mode out_trd_mode; 487 union { 488 unsigned int color; 489 struct disp_fb_info2 fb; 490 }; 491 492 unsigned int id; 493 struct disp_atw_info atw; 494 }; 495 496 /* disp_layer_config2 - layer config v2 497 * 498 * @info: layer info 499 * @enable: indicate to enable/disable the layer 500 * @channel: the channel index of the layer, 0~max-channel-number 501 * @layer_id: the layer index of the layer widthin it's channel 502 */ 503 struct disp_layer_config2 { 504 struct disp_layer_info2 info; 505 bool enable; 506 unsigned int channel; 507 unsigned int layer_id; 508 }; 509 /* disp_palette_config - palette config 510 * 511 * @num: the num of palette 512 * @data: the palette data, each palette data takes 4 bytes,show as below 513 * bits description 514 * 31:24 alpha value 515 * 23:16 red value 516 * 15:8 green value 517 * 7:0 blue value 518 * @channel: the channel index of the layer, 0~max-channel-number 519 */ 520 struct disp_palette_config { 521 unsigned int num; 522 void *data; 523 unsigned int channel; 524 }; 525 /** 526 * match rule: 0/1:always match; 527 * 2:match if min<=color<=max; 528 * 3:match if color>max or color<min 529 */ 530 struct disp_colorkey { 531 struct disp_color ck_max; 532 struct disp_color ck_min; 533 unsigned int red_match_rule; 534 unsigned int green_match_rule; 535 unsigned int blue_match_rule; 536 }; 537 538 struct disp_s_frame { 539 enum disp_pixel_format format; 540 struct disp_rectsz size[3]; 541 struct disp_rect crop; 542 unsigned long long addr[3]; 543 }; 544 545 struct disp_capture_info { 546 /* capture the whole screen if window eq ZERO */ 547 struct disp_rect window; 548 struct disp_s_frame out_frame; 549 }; 550 551 /* disp_s_frame2 - display simple frame buffer 552 * 553 * @format: pixel format of fb 554 * @size: size for each plane 555 * @crop: crop zone to be fill image data 556 * @fd: dma_buf fd 557 */ 558 struct disp_s_frame2 { 559 enum disp_pixel_format format; 560 struct disp_rectsz size[3]; 561 struct disp_rect crop; 562 int fd; 563 }; 564 565 /* disp_capture_info2 - display capture information 566 * 567 * @window: the rectange on the screen to be capture 568 * @out_frame: the framebuffer to be restore capture image data 569 */ 570 struct disp_capture_info2 { 571 struct disp_rect window; 572 struct disp_s_frame2 out_frame; 573 }; 574 575 struct disp_capture_fmt { 576 enum disp_pixel_format format; /* write-back ouput format, doson't support YUV ouput yet */ 577 struct disp_rect window; /* source crop */ 578 struct disp_rect crop; /* output crop */ 579 }; 580 581 struct disp_capture_buffer { 582 int handle; /* Unique integer id represent this buffer */ 583 enum disp_pixel_format format; /* write-back ouput format */ 584 struct disp_rect window; /* source crop */ 585 struct disp_rect crop; /* output crop */ 586 struct disp_rectsz size[3]; 587 588 int fd; 589 int width; /* buffer width in pixels */ 590 int height; /* buffer height in pixels */ 591 }; 592 593 struct disp_capture_handle { 594 int handle; /* unique integer id represent a capture buffer */ 595 int fencefd; /* fence fd for this buffer */ 596 }; 597 598 enum disp_capture_extend_cmd { 599 DISP_CAPTURE_E_SET_FMT, 600 DISP_CAPTURE_E_BUFFER_LIST_INIT, 601 DISP_CAPTURE_E_BUFFER_LIST_CLEAR, 602 DISP_CAPTURE_E_ACQUIRE_BUFFER, 603 DISP_CAPTURE_E_RELEASE_BUFFER, 604 DISP_CAPTURE_E_CTRL, 605 }; 606 607 /* disp_device_config - display deivce config 608 * 609 * @type: output type 610 * @mode: output mode 611 * @format: data format 612 * @bits: data bits 613 * @eotf: electro-optical transfer function 614 * SDR : DISP_EOTF_GAMMA22 615 * HDR10: DISP_EOTF_SMPTE2084 616 * HLG : DISP_EOTF_ARIB_STD_B67 617 * @cs: color space type 618 * DISP_BT601: SDR for SD resolution(< 720P) 619 * DISP_BT709: SDR for HD resolution(>= 720P) 620 * DISP_BT2020NC: HDR10 or HLG or wide-color-gamut 621 * @dvi_hdmi: output mode 622 * DVI: DISP_DVI 623 * HDMI: DISP_HDMI 624 * @range: RGB/YUV quantization range 625 * DEFUALT: limited range when sending a CE video format 626 * full range when sending an IT video format 627 * LIMITED: color limited range from 16 to 235 628 * FULL: color full range from 0 to 255 629 * @scan info: 630 * DISP_SCANINFO_NO_DATA: overscan if it is a CE format, 631 * underscan if it is an IT format 632 * OVERSCAN: composed for overscan display 633 * UNDERSCAN: composed for underscan display 634 * @aspect_ratio: active format aspect ratio 635 */ 636 struct disp_device_config { 637 enum disp_output_type type; 638 enum disp_tv_mode mode; 639 enum disp_csc_type format; 640 enum disp_data_bits bits; 641 enum disp_eotf eotf; 642 enum disp_color_space cs; 643 enum disp_dvi_hdmi dvi_hdmi; 644 enum disp_color_range range; 645 enum disp_scan_info scan; 646 unsigned int aspect_ratio; 647 unsigned int reserve1; 648 }; 649 650 /* disp_device_dynamic_config - display deivce dynamic config 651 * 652 * @metadata_fd: dma_buf fd for the buffer contained metadata for fbc/hdr 653 * @metadata_size: the size of metadata buffer, unit:bytes 654 * @metadata_flag: the flag to indicate the type of metadata buffer 655 * 0 : no metadata 656 * 1 << 0: hdr static metadata 657 * 1 << 1: hdr dynamic metadata 658 * 1 << 4: frame buffer compress(fbc) metadata 659 * x : all type could be "or" together 660 * @vmap:vmap a block contigous phys memory into virtual space 661 * @vunmap: release virtual mapping obtained by vmap() 662 */ 663 struct disp_device_dynamic_config { 664 int metadata_fd; 665 unsigned int metadata_size; 666 unsigned int metadata_flag; 667 void *(*vmap)(unsigned long phys_addr, unsigned long size); 668 void (*vunmap)(const void *vaddr); 669 }; 670 struct disp_video_timings { 671 unsigned int vic; /* video information code */ 672 unsigned int tv_mode; 673 unsigned int pixel_clk; 674 unsigned int pixel_repeat; /* pixel repeat (pixel_repeat+1) times */ 675 unsigned int x_res; 676 unsigned int y_res; 677 unsigned int hor_total_time; 678 unsigned int hor_back_porch; 679 unsigned int hor_front_porch; 680 unsigned int hor_sync_time; 681 unsigned int ver_total_time; 682 unsigned int ver_back_porch; 683 unsigned int ver_front_porch; 684 unsigned int ver_sync_time; 685 unsigned int hor_sync_polarity; /* 0: negative, 1: positive */ 686 unsigned int ver_sync_polarity; /* 0: negative, 1: positive */ 687 bool b_interlace; 688 unsigned int vactive_space; 689 unsigned int trd_mode; 690 unsigned long dclk_rate_set; /*unit: hz */ 691 unsigned long long frame_period; /* unit: ns */ 692 int start_delay; /* unit: line */ 693 }; 694 695 enum disp_fb_mode { 696 FB_MODE_SCREEN0 = 0, 697 FB_MODE_SCREEN1 = 1, 698 FB_MODE_SCREEN2 = 2, 699 FB_MODE_DUAL_SAME_SCREEN_TB = 3,/* two screen, top buffer for screen0, bottom buffer for screen1 */ 700 FB_MODE_DUAL_DIFF_SCREEN_SAME_CONTENTS = 4,/* two screen, they have same contents; */ 701 }; 702 703 struct disp_fb_create_info { 704 enum disp_fb_mode fb_mode; 705 enum disp_layer_mode mode; 706 unsigned int buffer_num; 707 unsigned int width; 708 unsigned int height; 709 710 unsigned int output_width; /* used when scaler mode */ 711 unsigned int output_height; /* used when scaler mode */ 712 }; 713 714 enum disp_init_mode { 715 DISP_INIT_MODE_SCREEN0 = 0, /* fb0 for screen0 */ 716 DISP_INIT_MODE_SCREEN1 = 1, /* fb0 for screen1 */ 717 DISP_INIT_MODE_SCREEN2 = 2, /* fb0 for screen1 */ 718 DISP_INIT_MODE_TWO_DIFF_SCREEN = 3,/* fb0 for screen0 and fb1 for screen1 */ 719 DISP_INIT_MODE_TWO_SAME_SCREEN = 4,/* fb0(up buffer for screen0, down buffer for screen1) */ 720 DISP_INIT_MODE_TWO_DIFF_SCREEN_SAME_CONTENTS = 5,/* fb0 for two different screen(screen0 layer is normal layer, screen1 layer is scaler layer); */ 721 }; 722 723 struct disp_tv_func { 724 int (*tv_enable)(u32 sel); 725 int (*tv_disable)(u32 sel); 726 int (*tv_suspend)(u32 sel); 727 int (*tv_resume)(u32 sel); 728 int (*tv_get_mode)(u32 sel); 729 int (*tv_set_mode)(u32 sel, enum disp_tv_mode tv_mod); 730 int (*tv_get_input_csc)(u32 sel); 731 int (*tv_get_video_timing_info)(u32 sel, 732 struct disp_video_timings ** 733 video_info); 734 int (*tv_mode_support)(u32 sel, enum disp_tv_mode mode); 735 int (*tv_hot_plugging_detect)(u32 state); 736 int (*tv_set_enhance_mode)(u32 sel, u32 mode); 737 int (*tv_irq_enable)(u32 sel, u32 irq_id, u32 en); 738 int (*tv_irq_query)(u32 sel); 739 unsigned int (*tv_get_cur_line)(u32 sel); 740 int (*vdpo_set_config)(u32 sel, struct disp_vdpo_config *p_cfg); 741 int (*tv_get_startdelay)(u32 sel); 742 void (*tv_show_builtin_patten)(u32 sel, u32 patten); 743 }; 744 745 /* disp_vdevice_interface_para - vdevice interaface parameter 746 * 747 * @intf:interface 748 * 0:hv, 1:cpu, 3:lvds, 4:dsi 749 * @sub_intf: sub interface 750 * rgb interface: 0:parallel hv, 8:serial hv, 10:dummy rgb 751 * 11: rgb dummy, 12: ccir656 752 * cpu interface: 0:18 pin, 10:9pin, 12:6pin, 8:16pin, 14:8pin 753 * lvds interface:0:single link, 1:dual link 754 * dsi inerafce: 0:video mode, 1:command mode, 2: video burst mode 755 * @sequence:output sequence 756 * rgb output: 0:rgb rgb, 1:rgb brg, 2:rgb gbr, 4:brg rgb 757 * 5:brg brg, 6:brg gbr 758 * 8:grb rgb, 9:grb brg, 10:grb gbr 759 * yuv output:0:yuyv, 1: yvyu, 2:uyvy, 3:vyuy 760 * @fdelay:yuv eav/sav F line delay 761 * 0: F toggle right after active video line 762 * 1: delay 2 line(CCIR NTSC) 763 * 2: delay 3 line(CCIR PAL) 764 * @clk_phase:clk phase 765 * 0: 0 degree, 1:90 degree, 2: 180 degree, 3:270 degree 766 * @sync_polarity:sync signals polarity 767 * 0: vsync active low,hsync active low 768 * 1: vsync active high,hsync active low 769 * 2: vsync active low,hsync active high 770 * 3: vsync active high,hsync active high 771 */ 772 struct disp_vdevice_interface_para { 773 unsigned int intf; 774 unsigned int sub_intf; 775 unsigned int sequence; 776 unsigned int fdelay; 777 unsigned int clk_phase; 778 unsigned int sync_polarity; 779 unsigned int ccir_clk_div; 780 unsigned int input_csc;/*not need to config for user*/ 781 }; 782 783 struct disp_vdevice_source_ops { 784 int (*tcon_enable)(struct disp_device *dispdev); 785 int (*tcon_disable)(struct disp_device *dispdev); 786 int (*tcon_simple_enable)(struct disp_device *dispdev); 787 int (*tcon_simple_disable)(struct disp_device *dispdev); 788 }; 789 790 struct disp_device_func { 791 int (*enable)(void); 792 int (*smooth_enable)(void); 793 int (*disable)(void); 794 int (*set_mode)(u32 mode); 795 int (*mode_support)(u32 mode); 796 int (*get_HPD_status)(void); 797 int (*get_input_csc)(void); 798 int (*get_input_color_range)(void); 799 int (*get_video_timing_info)(struct disp_video_timings **video_info); 800 int (*suspend)(void); 801 int (*resume)(void); 802 int (*early_suspend)(void); 803 int (*late_resume)(void); 804 int (*get_interface_para)(void *para); 805 int (*set_static_config)(struct disp_device_config *config); 806 int (*get_static_config)(struct disp_device_config *config); 807 int (*set_dynamic_config)(struct disp_device_dynamic_config *config); 808 int (*get_dynamic_config)(struct disp_device_dynamic_config *config); 809 810 /*for hdmi cec*/ 811 s32 (*cec_standby_request)(void); 812 s32 (*cec_send_one_touch_play)(void); 813 }; 814 815 struct disp_vdevice_init_data { 816 char name[32]; 817 u32 disp; 818 u32 fix_timing; 819 enum disp_output_type type; 820 struct disp_device_func func; 821 }; 822 823 enum disp_tv_dac_source { 824 DISP_TV_DAC_SRC_COMPOSITE = 0, 825 DISP_TV_DAC_SRC_LUMA = 1, 826 DISP_TV_DAC_SRC_CHROMA = 2, 827 DISP_TV_DAC_SRC_Y = 4, 828 DISP_TV_DAC_SRC_PB = 5, 829 DISP_TV_DAC_SRC_PR = 6, 830 DISP_TV_DAC_SRC_NONE = 7, 831 }; 832 833 enum disp_tv_output { 834 DISP_TV_NONE = 0, 835 DISP_TV_CVBS = 1, 836 DISP_TV_YPBPR = 2, 837 DISP_TV_SVIDEO = 4, 838 DISP_VGA = 5, 839 }; 840 841 enum tag_DISP_CMD { 842 /* ----disp global---- */ 843 DISP_SYS_SHOW = 0x00, 844 DISP_RESERVE1 = 0x01, 845 DISP_SET_BKCOLOR = 0x03, 846 DISP_GET_BKCOLOR = 0x04, 847 DISP_SET_COLORKEY = 0x05, 848 DISP_GET_COLORKEY = 0x06, 849 DISP_GET_SCN_WIDTH = 0x07, 850 DISP_GET_SCN_HEIGHT = 0x08, 851 DISP_GET_OUTPUT_TYPE = 0x09, 852 DISP_SET_EXIT_MODE = 0x0A, 853 DISP_VSYNC_EVENT_EN = 0x0B, 854 DISP_BLANK = 0x0C, 855 DISP_SHADOW_PROTECT = 0x0D, 856 DISP_HWC_COMMIT = 0x0E, 857 DISP_DEVICE_SWITCH = 0x0F, 858 DISP_GET_OUTPUT = 0x10, 859 DISP_SET_COLOR_RANGE = 0x11, 860 DISP_GET_COLOR_RANGE = 0x12, 861 DISP_HWC_CUSTOM = 0x13, 862 DISP_DEVICE_SET_CONFIG = 0x14, 863 DISP_DEVICE_GET_CONFIG = 0x15, 864 865 /* ----layer---- */ 866 DISP_LAYER_ENABLE = 0x40, 867 DISP_LAYER_DISABLE = 0x41, 868 DISP_LAYER_SET_INFO = 0x42, 869 DISP_LAYER_GET_INFO = 0x43, 870 DISP_LAYER_TOP = 0x44, 871 DISP_LAYER_BOTTOM = 0x45, 872 DISP_LAYER_GET_FRAME_ID = 0x46, 873 DISP_LAYER_SET_CONFIG = 0x47, 874 DISP_LAYER_GET_CONFIG = 0x48, 875 /* 876 * LAYER_S(G)ET_CONFIG2 takes disp_layer_config2, 877 * it will support more featuras 878 */ 879 DISP_LAYER_SET_CONFIG2 = 0x49, 880 DISP_LAYER_GET_CONFIG2 = 0x4a, 881 DISP_CHN_SET_PALETTE = 0x4b, 882 /* ----hdmi---- */ 883 DISP_HDMI_SUPPORT_MODE = 0xc4, 884 DISP_SET_TV_HPD = 0xc5, 885 DISP_HDMI_GET_EDID = 0xc6, 886 DISP_CEC_ONE_TOUCH_PLAY = 0xc7, 887 888 /* ----lcd---- */ 889 DISP_LCD_ENABLE = 0x100, 890 DISP_LCD_DISABLE = 0x101, 891 DISP_LCD_SET_BRIGHTNESS = 0x102, 892 DISP_LCD_GET_BRIGHTNESS = 0x103, 893 DISP_LCD_BACKLIGHT_ENABLE = 0x104, 894 DISP_LCD_BACKLIGHT_DISABLE = 0x105, 895 DISP_LCD_SET_SRC = 0x106, 896 DISP_LCD_SET_FPS = 0x107, 897 DISP_LCD_GET_FPS = 0x108, 898 DISP_LCD_GET_SIZE = 0x109, 899 DISP_LCD_GET_MODEL_NAME = 0x10a, 900 DISP_LCD_SET_GAMMA_TABLE = 0x10b, 901 DISP_LCD_GAMMA_CORRECTION_ENABLE = 0x10c, 902 DISP_LCD_GAMMA_CORRECTION_DISABLE = 0x10d, 903 DISP_LCD_USER_DEFINED_FUNC = 0x10e, 904 DISP_LCD_CHECK_OPEN_FINISH = 0x10f, 905 DISP_LCD_CHECK_CLOSE_FINISH = 0x110, 906 907 /*tv*/ 908 DISP_TV_SET_GAMMA_TABLE = 0x111, 909 /* ---- capture --- */ 910 DISP_CAPTURE_START = 0x140,/* caputre screen and scaler to dram */ 911 DISP_CAPTURE_STOP = 0x141, 912 DISP_CAPTURE_COMMIT = 0x142, 913 DISP_CAPTURE_COMMIT2 = 0x143, 914 DISP_CAPTURE_QUERY = 0x144, 915 DISP_CAPTURE_EXTEND = 0x145, 916 917 /* ---enhance --- */ 918 DISP_ENHANCE_ENABLE = 0x180, 919 DISP_ENHANCE_DISABLE = 0x181, 920 DISP_ENHANCE_GET_EN = 0x182, 921 DISP_ENHANCE_SET_WINDOW = 0x183, 922 DISP_ENHANCE_GET_WINDOW = 0x184, 923 DISP_ENHANCE_SET_MODE = 0x185, 924 DISP_ENHANCE_GET_MODE = 0x186, 925 DISP_ENHANCE_DEMO_ENABLE = 0x187, 926 DISP_ENHANCE_DEMO_DISABLE = 0x188, 927 DISP_ENHANCE_SET_BRIGHT = 0x190, 928 DISP_ENHANCE_GET_BRIGHT = 0x191, 929 DISP_ENHANCE_SET_CONTRAST = 0x192, 930 DISP_ENHANCE_GET_CONTRAST = 0x193, 931 DISP_ENHANCE_SET_SATURATION = 0x194, 932 DISP_ENHANCE_GET_SATURATION = 0x195, 933 934 /* ---smart backlight --- */ 935 DISP_SMBL_ENABLE = 0x200, 936 DISP_SMBL_DISABLE = 0x201, 937 DISP_SMBL_GET_EN = 0x202, 938 DISP_SMBL_SET_WINDOW = 0x203, 939 DISP_SMBL_GET_WINDOW = 0x204, 940 941 /* ---- for test */ 942 DISP_FB_REQUEST = 0x280, 943 DISP_FB_RELEASE = 0x281, 944 945 DISP_MEM_REQUEST = 0x2c0, 946 DISP_MEM_RELEASE = 0x2c1, 947 DISP_MEM_GETADR = 0x2c2, 948 DISP_VDPO_SET_CONFIG = 0x2c3, 949 950 /* --- rotation sw --- */ 951 DISP_ROTATION_SW_SET_ROT = 0x300, 952 DISP_ROTATION_SW_GET_ROT = 0x301, 953 954 DISP_EINK_UPDATE = 0x402, 955 DISP_EINK_SET_TEMP = 0x403, 956 DISP_EINK_GET_TEMP = 0x404, 957 DISP_EINK_OVERLAP_SKIP = 0x405, 958 DISP_EINK_UPDATE2 = 0x406, 959 }; 960 961 enum { 962 ROTATION_SW_0 = 0, 963 ROTATION_SW_90 = 1, 964 ROTATION_SW_180 = 2, 965 ROTATION_SW_270 = 3, 966 }; 967 968 #define FBIOGET_LAYER_HDL_0 0x4700 969 #define FBIOGET_LAYER_HDL_1 0x4701 970 971 #endif 972