1 /*
2  * Copyright (c) 2006-2024, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef __ZYNQMP_UART_H__
8 #define __ZYNQMP_UART_H__
9 
10 #include <zynqmp_reg.h>
11 
12 /* The following constant defines the amount of error that is allowed for
13  * a specified baud rate. This error is the difference between the actual
14  * baud rate that will be generated using the specified clock and the
15  * desired baud rate.
16  */
17 #define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
18 
19 /*
20  * The following constants indicate the max and min baud rates and these
21  * numbers are based only on the testing that has been done. The hardware
22  * is capable of other baud rates.
23  */
24 #define XUARTPS_MAX_RATE 6240000U
25 #define XUARTPS_MIN_RATE 110U
26 
27 /** @name Register Map
28  *
29  * Register offsets for the UART.
30  * @{
31  */
32 #define XUARTPS_CR_OFFSET 0x0000U      /**< Control Register [8:0] */
33 #define XUARTPS_MR_OFFSET 0x0004U      /**< Mode Register [9:0] */
34 #define XUARTPS_IER_OFFSET 0x0008U     /**< Interrupt Enable [12:0] */
35 #define XUARTPS_IDR_OFFSET 0x000CU     /**< Interrupt Disable [12:0] */
36 #define XUARTPS_IMR_OFFSET 0x0010U     /**< Interrupt Mask [12:0] */
37 #define XUARTPS_ISR_OFFSET 0x0014U     /**< Interrupt Status [12:0]*/
38 #define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
39 #define XUARTPS_RXTOUT_OFFSET 0x001CU  /**< RX Timeout [7:0] */
40 #define XUARTPS_RXWM_OFFSET 0x0020U    /**< RX FIFO Trigger Level [5:0] */
41 #define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
42 #define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
43 #define XUARTPS_SR_OFFSET 0x002CU      /**< Channel Status [14:0] */
44 #define XUARTPS_FIFO_OFFSET 0x0030U    /**< FIFO [7:0] */
45 #define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
46 #define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
47 #define XUARTPS_TXWM_OFFSET 0x0044U    /**< TX FIFO Trigger Level [5:0] */
48 #define XUARTPS_RXBS_OFFSET 0x0048U    /**< RX FIFO Byte Status [11:0] */
49 /* @} */
50 
51 /** @name Control Register
52  *
53  * The Control register (CR) controls the major functions of the device.
54  *
55  * Control Register Bit Definition
56  */
57 #define XUARTPS_CR_STOPBRK 0x00000100U     /**< Stop transmission of break */
58 #define XUARTPS_CR_STARTBRK 0x00000080U    /**< Set break */
59 #define XUARTPS_CR_TORST 0x00000040U       /**< RX timeout counter restart */
60 #define XUARTPS_CR_TX_DIS 0x00000020U      /**< TX disabled. */
61 #define XUARTPS_CR_TX_EN 0x00000010U       /**< TX enabled */
62 #define XUARTPS_CR_RX_DIS 0x00000008U      /**< RX disabled. */
63 #define XUARTPS_CR_RX_EN 0x00000004U       /**< RX enabled */
64 #define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
65 #define XUARTPS_CR_TXRST 0x00000002U       /**< TX logic reset */
66 #define XUARTPS_CR_RXRST 0x00000001U       /**< RX logic reset */
67 /* @}*/
68 
69 /** @name Mode Register
70  *
71  * The mode register (MR) defines the mode of transfer as well as the data
72  * format. If this register is modified during transmission or reception,
73  * data validity cannot be guaranteed.
74  *
75  * Mode Register Bit Definition
76  * @{
77  */
78 #define XUARTPS_MR_CCLK 0x00000400U             /**< Input clock selection */
79 #define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U    /**< Remote loopback mode */
80 #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U    /**< Local loopback mode */
81 #define XUARTPS_MR_CHMODE_ECHO 0x00000100U      /**< Auto echo mode */
82 #define XUARTPS_MR_CHMODE_NORM 0x00000000U      /**< Normal mode */
83 #define XUARTPS_MR_CHMODE_SHIFT 8U              /**< Mode shift */
84 #define XUARTPS_MR_CHMODE_MASK 0x00000300U      /**< Mode mask */
85 #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U   /**< 2 stop bits */
86 #define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
87 #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U   /**< 1 stop bit */
88 #define XUARTPS_MR_STOPMODE_SHIFT 6U            /**< Stop bits shift */
89 #define XUARTPS_MR_STOPMODE_MASK 0x000000A0U    /**< Stop bits mask */
90 #define XUARTPS_MR_PARITY_NONE 0x00000020U      /**< No parity mode */
91 #define XUARTPS_MR_PARITY_MARK 0x00000018U      /**< Mark parity mode */
92 #define XUARTPS_MR_PARITY_SPACE 0x00000010U     /**< Space parity mode */
93 #define XUARTPS_MR_PARITY_ODD 0x00000008U       /**< Odd parity mode */
94 #define XUARTPS_MR_PARITY_EVEN 0x00000000U      /**< Even parity mode */
95 #define XUARTPS_MR_PARITY_SHIFT 3U              /**< Parity setting shift */
96 #define XUARTPS_MR_PARITY_MASK 0x00000038U      /**< Parity mask */
97 #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U    /**< 6 bits data */
98 #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U    /**< 7 bits data */
99 #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U    /**< 8 bits data */
100 #define XUARTPS_MR_CHARLEN_SHIFT 1U             /**< Data Length shift */
101 #define XUARTPS_MR_CHARLEN_MASK 0x00000006U     /**< Data length mask */
102 #define XUARTPS_MR_CLKSEL 0x00000001U           /**< Input clock selection */
103 /* @} */
104 
105 /** @name Interrupt Registers
106  *
107  * Interrupt control logic uses the interrupt enable register (IER) and the
108  * interrupt disable register (IDR) to set the value of the bits in the
109  * interrupt mask register (IMR). The IMR determines whether to pass an
110  * interrupt to the interrupt status register (ISR).
111  * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
112  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
113  * Reading either IER or IDR returns 0x00.
114  *
115  * All four registers have the same bit definitions.
116  *
117  * @{
118  */
119 #define XUARTPS_IXR_RBRK 0x00002000U    /**< Rx FIFO break detect interrupt */
120 #define XUARTPS_IXR_TOVR 0x00001000U    /**< Tx FIFO Overflow interrupt */
121 #define XUARTPS_IXR_TNFUL 0x00000800U   /**< Tx FIFO Nearly Full interrupt */
122 #define XUARTPS_IXR_TTRIG 0x00000400U   /**< Tx Trig interrupt */
123 #define XUARTPS_IXR_DMS 0x00000200U     /**< Modem status change interrupt */
124 #define XUARTPS_IXR_TOUT 0x00000100U    /**< Timeout error interrupt */
125 #define XUARTPS_IXR_PARITY 0x00000080U  /**< Parity error interrupt */
126 #define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
127 #define XUARTPS_IXR_OVER 0x00000020U    /**< Overrun error interrupt */
128 #define XUARTPS_IXR_TXFULL 0x00000010U  /**< TX FIFO full interrupt. */
129 #define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
130 #define XUARTPS_IXR_RXFULL 0x00000004U  /**< RX FIFO full interrupt. */
131 #define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
132 #define XUARTPS_IXR_RXOVR 0x00000001U   /**< RX FIFO trigger interrupt. */
133 #define XUARTPS_IXR_MASK 0x00003FFFU    /**< Valid bit mask */
134 /* @} */
135 
136 /** @name Baud Rate Generator Register
137  *
138  * The baud rate generator control register (BRGR) is a 16 bit register that
139  * controls the receiver bit sample clock and baud rate.
140  * Valid values are 1 - 65535.
141  *
142  * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
143  * in the MR register.
144  * @{
145  */
146 #define XUARTPS_BAUDGEN_DISABLE 0x00000000U   /**< Disable clock */
147 #define XUARTPS_BAUDGEN_MASK 0x0000FFFFU      /**< Valid bits mask */
148 #define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
149 
150 /** @name Baud Divisor Rate register
151  *
152  * The baud rate divider register (BDIV) controls how much the bit sample
153  * rate is divided by. It sets the baud rate.
154  * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
155  *
156  * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
157  * the MR_CCLK bit in the MR register.
158  * @{
159  */
160 #define XUARTPS_BAUDDIV_MASK 0x000000FFU      /**< 8 bit baud divider mask */
161 #define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
162 /* @} */
163 
164 /** @name Receiver Timeout Register
165  *
166  * Use the receiver timeout register (RTR) to detect an idle condition on
167  * the receiver data line.
168  *
169  * @{
170  */
171 #define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
172 #define XUARTPS_RXTOUT_MASK 0x000000FFU    /**< Valid bits mask */
173 
174 /** @name Receiver FIFO Trigger Level Register
175  *
176  * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
177  * which the RX FIFO triggers an interrupt event.
178  * @{
179  */
180 #define XUARTPS_RXWM_DISABLE 0x00000000U   /**< Disable RX trigger interrupt */
181 #define XUARTPS_RXWM_MASK 0x0000003FU      /**< Valid bits mask */
182 #define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
183 /* @} */
184 
185 /** @name Transmit FIFO Trigger Level Register
186  *
187  * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
188  * which the TX FIFO triggers an interrupt event.
189  * @{
190  */
191 #define XUARTPS_TXWM_MASK 0x0000003FU      /**< Valid bits mask */
192 #define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
193 /* @} */
194 
195 /** @name Modem Control Register
196  *
197  * This register (MODEMCR) controls the interface with the modem or data set,
198  * or a peripheral device emulating a modem.
199  *
200  * @{
201  */
202 #define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
203 #define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
204 #define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
205 /* @} */
206 
207 /** @name Modem Status Register
208  *
209  * This register (MODEMSR) indicates the current state of the control lines
210  * from a modem, or another peripheral device, to the CPU. In addition, four
211  * bits of the modem status register provide change information. These bits
212  * are set to a logic 1 whenever a control input from the modem changes state.
213  *
214  * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
215  * status interrupt is generated and this is reflected in the modem status
216  * register.
217  *
218  * @{
219  */
220 #define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
221 #define XUARTPS_MODEMSR_DCD 0x00000080U  /**< Complement of DCD input */
222 #define XUARTPS_MODEMSR_RI 0x00000040U   /**< Complement of RI input */
223 #define XUARTPS_MODEMSR_DSR 0x00000020U  /**< Complement of DSR input */
224 #define XUARTPS_MODEMSR_CTS 0x00000010U  /**< Complement of CTS input */
225 #define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
226 #define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
227 #define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
228 #define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
229 /* @} */
230 
231 /** @name Channel Status Register
232  *
233  * The channel status register (CSR) is provided to enable the control logic
234  * to monitor the status of bits in the channel interrupt status register,
235  * even if these are masked out by the interrupt mask register.
236  *
237  * @{
238  */
239 #define XUARTPS_SR_TNFUL 0x00004000U   /**< TX FIFO Nearly Full Status */
240 #define XUARTPS_SR_TTRIG 0x00002000U   /**< TX FIFO Trigger Status */
241 #define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
242 #define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
243 #define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
244 #define XUARTPS_SR_TXFULL 0x00000010U  /**< TX FIFO full */
245 #define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
246 #define XUARTPS_SR_RXFULL 0x00000004U  /**< RX FIFO full */
247 #define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
248 #define XUARTPS_SR_RXOVR 0x00000001U   /**< RX FIFO fill over trigger */
249 /* @} */
250 
251 /** @name Flow Delay Register
252  *
253  * Operation of the flow delay register (FLOWDEL) is very similar to the
254  * receive FIFO trigger register. An internal trigger signal activates when the
255  * FIFO is filled to the level set by this register. This trigger will not
256  * cause an interrupt, although it can be read through the channel status
257  * register. In hardware flow control mode, RTS is deactivated when the trigger
258  * becomes active. RTS only resets when the FIFO level is four less than the
259  * level of the flow delay trigger and the flow delay trigger is not activated.
260  * A value less than 4 disables the flow delay.
261  * @{
262  */
263 #define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
264 /* @} */
265 
266 /** @name Receiver FIFO Byte Status Register
267  *
268  * The Receiver FIFO Status register is used to have a continuous
269  * monitoring of the raw unmasked byte status information. The register
270  * contains frame, parity and break status information for the top
271  * four bytes in the RX FIFO.
272  *
273  * Receiver FIFO Byte Status Register Bit Definition
274  * @{
275  */
276 #define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
277 #define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
278 #define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
279 #define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
280 #define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
281 #define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
282 #define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
283 #define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
284 #define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
285 #define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
286 #define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
287 #define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
288 #define XUARTPS_RXBS_MASK 0x00000007U       /**< 3 bit RX byte status mask */
289 /* @} */
290 
291 /*
292  * Defines for backwards compatibility, will be removed
293  * in the next version of the driver
294  */
295 #define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
296 #define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
297 #define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
298 #define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
299 
300 #endif /* __ZYNQMP_UART_H__ */
301