1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file hal_adc.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE ADC 5 /// FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 #ifndef __HAL_ADC_H 21 #define __HAL_ADC_H 22 23 // Files includes 24 #include "types.h" 25 #include "reg_adc.h" 26 27 //////////////////////////////////////////////////////////////////////////////// 28 /// @addtogroup MM32_Hardware_Abstract_Layer 29 /// @{ 30 31 //////////////////////////////////////////////////////////////////////////////// 32 /// @defgroup ADC_HAL 33 /// @brief ADC HAL modules 34 /// @{ 35 36 //////////////////////////////////////////////////////////////////////////////// 37 /// @defgroup ADC_Exported_Types 38 /// @{ 39 40 //////////////////////////////////////////////////////////////////////////////// 41 /// @brief ADC_Channels 42 //////////////////////////////////////////////////////////////////////////////// 43 typedef enum { 44 ADC_Channel_0 = 0x00, ///< ADC Channel 0 45 ADC_Channel_1 = 0x01, ///< ADC Channel 1 46 ADC_Channel_2 = 0x02, ///< ADC Channel 2 47 ADC_Channel_3 = 0x03, ///< ADC Channel 3 48 ADC_Channel_4 = 0x04, ///< ADC Channel 4 49 ADC_Channel_5 = 0x05, ///< ADC Channel 5 50 ADC_Channel_6 = 0x06, ///< ADC Channel 6 51 ADC_Channel_7 = 0x07, ///< ADC Channel 7 52 53 ADC_Channel_8 = 0x08, ///< ADC Channel 8 54 ADC_Channel_9 = 0x09, ///< ADC Channel 9 55 ADC_Channel_10 = 0x0A, ///< ADC Channel 10 56 ADC_Channel_11 = 0x0B, ///< ADC Channel 11 57 ADC_Channel_12 = 0x0C, ///< ADC Channel 12 58 ADC_Channel_13 = 0x0D, ///< ADC Channel 13 59 ADC_Channel_14 = 0x0E, ///< ADC Channel 14 60 ADC_Channel_15 = 0x0F, ///< ADC Channel 15 61 ADC_Channel_TempSensor = 0x0E, ///< Temperature sensor channel(ADC1) 62 ADC_Channel_VoltReference = 0x0F, ///< Internal reference voltage channel(ADC1) 63 ADC_Channel_Vrefint = 0x0F, ///< Internal reference voltage channel(ADC1) 64 65 } ADCCHANNEL_TypeDef; 66 67 //////////////////////////////////////////////////////////////////////////////// 68 /// @brief ADC_Sampling_Times 69 //////////////////////////////////////////////////////////////////////////////// 70 typedef enum { 71 ADC_Samctl_1_5 = ADC_SMPR1_SAMCTL0_2_5, ///< ADC sample time select 1.5t 72 ADC_Samctl_2_5 = ADC_SMPR1_SAMCTL0_2_5, ///< ADC sample time select 2.5t 73 ADC_Samctl_3_5 = ADC_SMPR1_SAMCTL0_3_5, ///< ADC sample time select 3.5t 74 ADC_Samctl_4_5 = ADC_SMPR1_SAMCTL0_4_5, ///< ADC sample time select 4.5t 75 ADC_Samctl_5_5 = ADC_SMPR1_SAMCTL0_5_5, ///< ADC sample time select 5.5t 76 ADC_Samctl_6_5 = ADC_SMPR1_SAMCTL0_6_5, ///< ADC sample time select 6.5t 77 ADC_Samctl_7_5 = ADC_SMPR1_SAMCTL0_7_5, ///< ADC sample time select 7.5t 78 ADC_Samctl_8_5 = ADC_SMPR1_SAMCTL0_8_5, ///< ADC sample time select 7.5t 79 ADC_Samctl_13_5 = ADC_SMPR1_SAMCTL0_14_5, ///< ADC sample time select 13.5t 80 ADC_Samctl_14_5 = ADC_SMPR1_SAMCTL0_14_5, ///< ADC sample time select 14.5t 81 ADC_Samctl_28_5 = ADC_SMPR1_SAMCTL0_29_5, ///< ADC sample time select 28.5t 82 ADC_Samctl_29_5 = ADC_SMPR1_SAMCTL0_29_5, ///< ADC sample time select 29.5t 83 ADC_Samctl_41_5 = ADC_SMPR1_SAMCTL0_42_5, ///< ADC sample time select 41.5t 84 ADC_Samctl_42_5 = ADC_SMPR1_SAMCTL0_42_5, ///< ADC sample time select 42.5t 85 ADC_Samctl_55_5 = ADC_SMPR1_SAMCTL0_56_5, ///< ADC sample time select 55.5t 86 ADC_Samctl_56_5 = ADC_SMPR1_SAMCTL0_56_5, ///< ADC sample time select 56.5t 87 ADC_Samctl_71_5 = ADC_SMPR1_SAMCTL0_72_5, ///< ADC sample time select 71.5t 88 ADC_Samctl_72_5 = ADC_SMPR1_SAMCTL0_72_5, ///< ADC sample time select 72.5t 89 ADC_Samctl_239_5 = ADC_SMPR1_SAMCTL0_240_5, ///< ADC sample time select 239.5t 90 ADC_Samctl_240_5 = ADC_SMPR1_SAMCTL0_240_5 ///< ADC sample time select 240.5t 91 } ADCSAM_TypeDef; 92 //////////////////////////////////////////////////////////////////////////////// 93 /// @brief ADC_Resolution 94 //////////////////////////////////////////////////////////////////////////////// 95 typedef enum { 96 ADC_Resolution_12b = ADC_CFGR_RSLTCTL_12, ///< ADC resolution select 12bit 97 ADC_Resolution_11b = ADC_CFGR_RSLTCTL_11, ///< ADC resolution select 11bit 98 ADC_Resolution_10b = ADC_CFGR_RSLTCTL_10, ///< ADC resolution select 10bit 99 ADC_Resolution_9b = ADC_CFGR_RSLTCTL_9, ///< ADC resolution select 9bit 100 ADC_Resolution_8b = ADC_CFGR_RSLTCTL_8 ///< ADC resolution select 8bit 101 } ADCRSL_TypeDef; 102 /// @brief ADC_Prescare 103 //////////////////////////////////////////////////////////////////////////////// 104 typedef enum { 105 ADC_PCLK2_PRESCARE_3 = ADC_CFGR_PRE_3, ///< ADC preclk 3 106 ADC_PCLK2_PRESCARE_5 = ADC_CFGR_PRE_5, ///< ADC preclk 5 107 ADC_PCLK2_PRESCARE_7 = ADC_CFGR_PRE_7, ///< ADC preclk 7 108 ADC_PCLK2_PRESCARE_9 = ADC_CFGR_PRE_9, ///< ADC preclk 9 109 ADC_PCLK2_PRESCARE_11 = ADC_CFGR_PRE_11, ///< ADC preclk 11 110 ADC_PCLK2_PRESCARE_13 = ADC_CFGR_PRE_13, ///< ADC preclk 13 111 ADC_PCLK2_PRESCARE_15 = ADC_CFGR_PRE_15, ///< ADC preclk 15 112 ADC_PCLK2_PRESCARE_17 = ADC_CFGR_PRE_17, ///< ADC preclk 17 113 114 ADC_PCLK2_PRESCARE_2 = ADC_CFGR_PRE_2, ///< ADC preclk 2 115 ADC_PCLK2_PRESCARE_4 = ADC_CFGR_PRE_4, ///< ADC preclk 4 116 ADC_PCLK2_PRESCARE_6 = ADC_CFGR_PRE_6, ///< ADC preclk 6 117 ADC_PCLK2_PRESCARE_8 = ADC_CFGR_PRE_8, ///< ADC preclk 8 118 ADC_PCLK2_PRESCARE_10 = ADC_CFGR_PRE_10, ///< ADC preclk 10 119 ADC_PCLK2_PRESCARE_12 = ADC_CFGR_PRE_12, ///< ADC preclk 12 120 ADC_PCLK2_PRESCARE_14 = ADC_CFGR_PRE_14, ///< ADC preclk 14 121 ADC_PCLK2_PRESCARE_16 = ADC_CFGR_PRE_16 ///< ADC preclk 16 122 } ADCPRE_TypeDef; 123 124 //////////////////////////////////////////////////////////////////////////////// 125 /// @brief ADC_Conversion_Mode 126 //////////////////////////////////////////////////////////////////////////////// 127 typedef enum { 128 ADC_Mode_Imm = ADC_CR_IMM, ///< ADC single convert mode 129 ADC_Mode_Scan = ADC_CR_SCAN, ///< ADC single period convert mode 130 ADC_Mode_Continue = ADC_CR_CONTINUE ///< ADC continue scan convert mode 131 } ADCMODE_TypeDef; 132 133 //////////////////////////////////////////////////////////////////////////////// 134 /// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion 135 //////////////////////////////////////////////////////////////////////////////// 136 typedef enum { 137 ADC1_ExternalTrigConv_T1_CC1 = ADC_CR_T1_CC1, 138 ADC1_ExternalTrigConv_T1_CC2 = ADC_CR_T1_CC2, 139 ADC1_ExternalTrigConv_T1_CC3 = ADC_CR_T1_CC3, 140 ADC1_ExternalTrigConv_T2_CC2 = ADC_CR_T2_CC2, 141 ADC1_ExternalTrigConv_T3_TRIG = ADC_CR_T3_TRIG, 142 ADC1_ExternalTrigConv_T3_CC1 = ADC_CR_T3_CC1, 143 ADC1_ExternalTrigConv_EXTI_11 = ADC_CR_EXTI_11, 144 ADC1_ExternalTrigConv_T1_CC4_CC5 = ADC_CR_T1_CC4_CC5, 145 ADC1_ExternalTrigConv_T1_TRIG = ADC_CR_T1_TRIG, 146 ADC1_ExternalTrigConv_T8_CC4 = ADC_CR_T8_CC4, 147 ADC1_ExternalTrigConv_T8_CC4_CC5 = ADC_CR_T8_CC4_CC5, 148 ADC1_ExternalTrigConv_T2_CC1 = ADC_CR_T2_CC1, 149 ADC1_ExternalTrigConv_T3_CC4 = ADC_CR_T3_CC4, 150 ADC1_ExternalTrigConv_T2_TRIG = ADC_CR_T2_TRIG, 151 ADC1_ExternalTrigConv_T8_CC5 = ADC_CR_T8_CC5, 152 ADC1_ExternalTrigConv_EXTI_15 = ADC_CR_EXTI_15, 153 ADC1_ExternalTrigConv_T1_CC4 = ADC_CR_TIM1_CC4, 154 ADC1_ExternalTrigConv_T1_CC5 = ADC_CR_TIM1_CC5 155 } EXTERTRIG_TypeDef; 156 157 //////////////////////////////////////////////////////////////////////////////// 158 /// @brief ADC_Data_Align 159 //////////////////////////////////////////////////////////////////////////////// 160 typedef enum { 161 ADC_DataAlign_Right = ADC_CR_RIGHT, ///< ADC data left align 162 ADC_DataAlign_Left = ADC_CR_LEFT ///< ADC data right align 163 } ADCDATAALI_TypeDef; 164 165 //////////////////////////////////////////////////////////////////////////////// 166 /// @brief ADC_Flags_Definition 167 //////////////////////////////////////////////////////////////////////////////// 168 typedef enum { 169 ADC_IT_EOC = 1, ///< ADC conversion flag 170 ADC_FLAG_EOC = 1, 171 ADC_IT_AWD = 2, ///< ADC window comparator flag 172 ADC_FLAG_AWD = 2 173 } ADCFLAG_TypeDef; 174 175 //////////////////////////////////////////////////////////////////////////////// 176 /// @brief ADC_Trig_Edge 177 //////////////////////////////////////////////////////////////////////////////// 178 typedef enum { 179 ADC_ADC_Trig_Edge_Dual = ADC_CR_TRG_EDGE_DUAL, ///< ADC trig edge dual mode down and up 180 ADC_ADC_Trig_Edge_Down = ADC_CR_TRG_EDGE_DOWN, ///< ADC trig edge single mode down 181 ADC_ADC_Trig_Edge_Up = ADC_CR_TRG_EDGE_UP, ///< ADC trig edge single mode up 182 ADC_ADC_Trig_Edge_Mask = ADC_CR_TRG_EDGE_MASK ///< ADC trig edge is mask, not allowed 183 } ADCTRIGEDGE_TypeDef; 184 185 186 //////////////////////////////////////////////////////////////////////////////// 187 /// @brief ADC_Scan_Direct 188 //////////////////////////////////////////////////////////////////////////////// 189 typedef enum { 190 ADC_Scan_Direct_Up = ADC_CR_SCANDIR, ///< ADC scan from low channel to high channel 191 ADC_Scan_Direct_Down = 0 ///< ADC scan from High channel to low channel 192 } ADCSCANDIRECT_TypeDef; 193 //////////////////////////////////////////////////////////////////////////////// 194 /// @brief ADC_Trig_Shift 195 //////////////////////////////////////////////////////////////////////////////// 196 typedef enum { 197 ADC_ADC_Trig_Shift_0 = ADC_CR_TRGSHIFT_0, ///< ADC trig shift bit is 0 198 ADC_ADC_Trig_Shift_4 = ADC_CR_TRGSHIFT_4, ///< ADC trig shift bit is 4 199 ADC_ADC_Trig_Shift_16 = ADC_CR_TRGSHIFT_16, ///< ADC trig shift bit is 16 200 ADC_ADC_Trig_Shift_32 = ADC_CR_TRGSHIFT_32, ///< ADC trig shift bit is 32 201 ADC_ADC_Trig_Shift_64 = ADC_CR_TRGSHIFT_64, ///< ADC trig shift bit is 64 202 ADC_ADC_Trig_Shift_128 = ADC_CR_TRGSHIFT_128, ///< ADC trig shift bit is 128 203 ADC_ADC_Trig_Shift_256 = ADC_CR_TRGSHIFT_256, ///< ADC trig shift bit is 256 204 ADC_ADC_Trig_Shift_512 = ADC_CR_TRGSHIFT_512, ///< ADC trig shift bit is 512 205 } ADCTRIGSHIFT_TypeDef; 206 //////////////////////////////////////////////////////////////////////////////// 207 /// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels 208 //////////////////////////////////////////////////////////////////////////////// 209 typedef enum { 210 ADC_Inject_Seqen_Len1 = 0, ///< ADC Injected Seqence length is 1 211 ADC_Inject_Seqen_Len2 = 1, ///< ADC Injected Seqence length is 2 212 ADC_Inject_Seqen_Len3 = 2, ///< ADC Injected Seqence length is 3 213 ADC_Inject_Seqen_Len4 = 3, ///< ADC Injected Seqence length is 4 214 } ADC_INJ_SEQ_LEN_TypeDef; 215 //////////////////////////////////////////////////////////////////////////////// 216 /// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels 217 //////////////////////////////////////////////////////////////////////////////// 218 typedef enum { 219 ADC_InjectedChannel_1 = 0x00, 220 ADC_InjectedChannel_2 = 0x04, 221 ADC_InjectedChannel_3 = 0x08, 222 ADC_InjectedChannel_4 = 0x0c, 223 } ADC_INJ_SEQ_Channel_TypeDef; 224 //////////////////////////////////////////////////////////////////////////////// 225 /// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion 226 //////////////////////////////////////////////////////////////////////////////// 227 typedef enum { 228 ADC1_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO 229 ADC1_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4 230 ADC1_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5 231 ADC1_InjectExtTrigSrc_T2_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM2 CC1 232 ADC1_InjectExtTrigSrc_T3_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM3 CC4 233 ADC1_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4 234 ADC1_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5 235 ADC1_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12 236 237 ADC2_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO 238 ADC2_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4 239 ADC2_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5 240 ADC2_InjectExtTrigSrc_T2_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM2 CC1 241 ADC2_InjectExtTrigSrc_T3_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM3 CC4 242 ADC2_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4 243 ADC2_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5 244 245 ADC2_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12 246 ADC3_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO 247 ADC3_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4 248 ADC3_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5 249 ADC3_InjectExtTrigSrc_T4_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM4 CC1 250 ADC3_InjectExtTrigSrc_T5_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM5 CC4 251 ADC3_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4 252 ADC3_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5 253 ADC3_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12 254 } EXTER_INJ_TRIG_TypeDef; 255 256 257 //////////////////////////////////////////////////////////////////////////////// 258 /// @brief ADC Init Structure definition 259 //////////////////////////////////////////////////////////////////////////////// 260 typedef struct { 261 u32 ADC_Resolution; ///< Convert data resolution 262 u32 ADC_PRESCARE; ///< Clock prescaler 263 u32 ADC_Mode; ///< ADC conversion mode 264 FunctionalState ADC_ContinuousConvMode; ///< Useless just for compatibility 265 u32 ADC_ExternalTrigConv; ///< External trigger source selection 266 u32 ADC_DataAlign; ///< Data alignmentn 267 } ADC_InitTypeDef; 268 269 /// @} 270 271 272 273 274 275 276 //////////////////////////////////////////////////////////////////////////////// 277 /// @defgroup ADC_Exported_Variables 278 /// @{ 279 #ifdef _HAL_ADC_C_ 280 281 #define GLOBAL 282 #else 283 #define GLOBAL extern 284 #endif 285 286 #undef GLOBAL 287 /// @} 288 289 //////////////////////////////////////////////////////////////////////////////// 290 /// @defgroup ADC_Exported_Functions 291 /// @{ 292 void ADC_DeInit(ADC_TypeDef* adc); 293 void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct); 294 void ADC_StructInit(ADC_InitTypeDef* init_struct); 295 void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state); 296 void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state); 297 void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state); 298 void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state); 299 void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time);//ADCSAM_TypeDef 300 void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state); 301 void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source); 302 #define ADC_ExternalTrigInjectedConvConfig ADC_ExternalTrigConvConfig 303 void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state); 304 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold); 305 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel); 306 void ADC_TempSensorVrefintCmd(FunctionalState state); 307 void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt); 308 void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag); 309 310 u16 ADC_GetConversionValue(ADC_TypeDef* adc); 311 312 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc); 313 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag); 314 ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt); 315 void ADC_TempSensorCmd(FunctionalState state); 316 void ADC_VrefintCmd(FunctionalState state); 317 void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state); 318 void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel); 319 void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num); 320 void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state); 321 void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state); 322 void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource); 323 void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state); 324 void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state); 325 void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time); 326 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length); 327 void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel); 328 u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr); 329 u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc); 330 void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value); 331 u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel); 332 /// @} 333 334 /// @} 335 336 /// @} 337 338 //////////////////////////////////////////////////////////////////////////////// 339 #endif 340 //////////////////////////////////////////////////////////////////////////////// 341 342