Searched refs:ADC_CC_CS_SYSPLL (Results 1 – 11 of 11) sorted by relevance
1291 #define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV macro
1301 #define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV macro
6186 #define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV macro
6789 #define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV macro
6954 #define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV macro
1158 #define ADC_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the macro
6349 #define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV macro
6456 #define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV macro
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