1 /*********************************************************************************************************//** 2 * @file ht32f1xxxx_adc.h 3 * @version $Rev:: 2791 $ 4 * @date $Date:: 2022-11-24 #$ 5 * @brief The header file of the ADC library. 6 ************************************************************************************************************* 7 * @attention 8 * 9 * Firmware Disclaimer Information 10 * 11 * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the 12 * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the 13 * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and 14 * other intellectual property laws. 15 * 16 * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the 17 * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties 18 * other than HOLTEK and the customer. 19 * 20 * 3. The program technical documentation, including the code, is provided "as is" and for customer reference 21 * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including 22 * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including 23 * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. 24 * 25 * <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2> 26 ************************************************************************************************************/ 27 28 /* Define to prevent recursive inclusion -------------------------------------------------------------------*/ 29 #ifndef __HT32F1XXXX_ADC_H 30 #define __HT32F1XXXX_ADC_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* Includes ------------------------------------------------------------------------------------------------*/ 37 #include "ht32.h" 38 39 /** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver 40 * @{ 41 */ 42 43 /** @addtogroup ADC 44 * @{ 45 */ 46 47 48 /* Exported constants --------------------------------------------------------------------------------------*/ 49 /** @defgroup ADC_Exported_Constants ADC exported constants 50 * @{ 51 */ 52 #define IS_ADC(x) (x == HT_ADC) 53 54 #define ONE_SHOT_MODE (0x00000000) 55 #define CONTINUOUS_MODE (0x00000002) 56 #define DISCONTINUOUS_MODE (0x00000003) 57 58 #define IS_ADC_CONVERSION_MODE(REGULAR_MODE) (((REGULAR_MODE) == ONE_SHOT_MODE) || \ 59 ((REGULAR_MODE) == CONTINUOUS_MODE) || \ 60 ((REGULAR_MODE) == DISCONTINUOUS_MODE)) 61 62 #define IS_ADC_HP_CONVERSION_MODE(HP_MODE) (((HP_MODE) == ONE_SHOT_MODE) || \ 63 ((HP_MODE) == CONTINUOUS_MODE) || \ 64 ((HP_MODE) == DISCONTINUOUS_MODE)) 65 66 67 #define ADC_CH_0 (0) 68 #define ADC_CH_1 (1) 69 #define ADC_CH_2 (2) 70 #define ADC_CH_3 (3) 71 #define ADC_CH_4 (4) 72 #define ADC_CH_5 (5) 73 #define ADC_CH_6 (6) 74 #define ADC_CH_7 (7) 75 #if !(LIBCFG_NO_ADC_CH8_15) 76 #define ADC_CH_8 (8) 77 #define ADC_CH_9 (9) 78 #define ADC_CH_10 (10) 79 #define ADC_CH_11 (11) 80 #if (LIBCFG_ADC_CH12_15) 81 #define ADC_CH_12 (12) 82 #define ADC_CH_13 (13) 83 #define ADC_CH_14 (14) 84 #define ADC_CH_15 (15) 85 #define IS_ADC_CHANNEL12_15(CHANNEL) (((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || \ 86 ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15)) 87 #else 88 #define IS_ADC_CHANNEL12_15(CHANNEL) (0) 89 #endif 90 #else 91 #define IS_ADC_CHANNEL8_14(CHANNEL) (0) 92 #define ADC_CH_IVREF (15) 93 #endif 94 #define ADC_CH_GND_VREF (16) 95 #define ADC_CH_VDD_VREF (17) 96 97 #define ADC_CH_GNDREF ADC_CH_GND_VREF 98 #define ADC_CH_VREF ADC_CH_VDD_VREF 99 100 101 #if (LIBCFG_NO_ADC_CH8_15) 102 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ 103 ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ 104 ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ 105 ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ 106 (IS_ADC_CHANNEL8_14(CHANNEL)) || \ 107 ((CHANNEL) == ADC_CH_IVREF) || ((CHANNEL) == ADC_CH_GND_VREF) || \ 108 ((CHANNEL) == ADC_CH_VDD_VREF)) 109 #else 110 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ 111 ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ 112 ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ 113 ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ 114 ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ 115 ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) || \ 116 (IS_ADC_CHANNEL12_15(CHANNEL)) || \ 117 ((CHANNEL) == ADC_CH_GND_VREF) || ((CHANNEL) == ADC_CH_VDD_VREF)) 118 #endif 119 120 #if (LIBCFG_NO_ADC_CH8_15) 121 #define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ 122 ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ 123 ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ 124 ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7)) 125 #else 126 #define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ 127 ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ 128 ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ 129 ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ 130 ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ 131 ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) || \ 132 (IS_ADC_CHANNEL12_15(CHANNEL))) 133 #endif 134 135 #define ADC_TRIG_SOFTWARE (1UL << 0) 136 137 /* ((ADCTCR[4] << 4) | (ADCTSR[20] << 20)) */ 138 #if (!LIBCFG_NO_CMP_TRIG_ADC) 139 #define ADC_TRIG_CMP0 ((1UL << 4) | (0UL << 20)) 140 #define ADC_TRIG_CMP1 ((1UL << 4) | (1UL << 20)) 141 #endif 142 143 #if (!LIBCFG_NO_CMP_HPTRIG_ADC) 144 #define ADC_HPTRIG_CMP0 ADC_TRIG_CMP0 145 #define ADC_HPTRIG_CMP1 ADC_TRIG_CMP1 146 #endif 147 148 /* ((ADCTCR[3] << 3) | (ADCTSR[23:22] << 22) | (ADCTSR[19] << 19)) */ 149 #define ADC_TRIG_BFTM0 ((1UL << 3) | (0UL << 22) | (0UL << 19)) 150 #define ADC_TRIG_BFTM1 ((1UL << 3) | (0UL << 22) | (1UL << 19)) 151 152 /* ((ADCTCR[3] << 3) | (ADCTSR[29:27]) << 27) | (ADCTSR[23:22] << 22) | (ADCTSR[19] << 19)) */ 153 #if (LIBCFG_PWM0) 154 #define ADC_TRIG_PWM0_MTO ((1UL << 3) | (0UL << 27) | (1UL << 22) | (0UL << 19)) 155 #define ADC_TRIG_PWM0_CH0O ((1UL << 3) | (1UL << 27) | (1UL << 22) | (0UL << 19)) 156 #define ADC_TRIG_PWM0_CH1O ((1UL << 3) | (2UL << 27) | (1UL << 22) | (0UL << 19)) 157 #define ADC_TRIG_PWM0_CH2O ((1UL << 3) | (3UL << 27) | (1UL << 22) | (0UL << 19)) 158 #define ADC_TRIG_PWM0_CH3O ((1UL << 3) | (4UL << 27) | (1UL << 22) | (0UL << 19)) 159 #endif 160 #if (LIBCFG_PWM1) 161 #define ADC_TRIG_PWM1_MTO ((1UL << 3) | (0UL << 27) | (1UL << 22) | (1UL << 19)) 162 #define ADC_TRIG_PWM1_CH0O ((1UL << 3) | (1UL << 27) | (1UL << 22) | (1UL << 19)) 163 #define ADC_TRIG_PWM1_CH1O ((1UL << 3) | (2UL << 27) | (1UL << 22) | (1UL << 19)) 164 #define ADC_TRIG_PWM1_CH2O ((1UL << 3) | (3UL << 27) | (1UL << 22) | (1UL << 19)) 165 #define ADC_TRIG_PWM1_CH3O ((1UL << 3) | (4UL << 27) | (1UL << 22) | (1UL << 19)) 166 #endif 167 168 /* ((ADCTCR[2] << 2) | (ADCTSR[26:24] << 24) | (ADCTSR[18:16] << 16)) */ 169 #if (!LIBCFG_NO_MCTM0) 170 #define ADC_TRIG_MCTM0_MTO ((1UL << 2) | (0UL << 24) | (0UL << 16)) 171 #define ADC_TRIG_MCTM0_CH0O ((1UL << 2) | (1UL << 24) | (0UL << 16)) 172 #define ADC_TRIG_MCTM0_CH1O ((1UL << 2) | (2UL << 24) | (0UL << 16)) 173 #define ADC_TRIG_MCTM0_CH2O ((1UL << 2) | (3UL << 24) | (0UL << 16)) 174 #define ADC_TRIG_MCTM0_CH3O ((1UL << 2) | (4UL << 24) | (0UL << 16)) 175 #endif 176 177 #if (!LIBCFG_NO_MCTM1) 178 #define ADC_TRIG_MCTM1_MTO ((1UL << 2) | (0UL << 24) | (1UL << 16)) 179 #define ADC_TRIG_MCTM1_CH0O ((1UL << 2) | (1UL << 24) | (1UL << 16)) 180 #define ADC_TRIG_MCTM1_CH1O ((1UL << 2) | (2UL << 24) | (1UL << 16)) 181 #define ADC_TRIG_MCTM1_CH2O ((1UL << 2) | (3UL << 24) | (1UL << 16)) 182 #define ADC_TRIG_MCTM1_CH3O ((1UL << 2) | (4UL << 24) | (1UL << 16)) 183 #endif 184 185 #define ADC_TRIG_GPTM0_MTO ((1UL << 2) | (0UL << 24) | (2UL << 16)) 186 #define ADC_TRIG_GPTM0_CH0O ((1UL << 2) | (1UL << 24) | (2UL << 16)) 187 #define ADC_TRIG_GPTM0_CH1O ((1UL << 2) | (2UL << 24) | (2UL << 16)) 188 #define ADC_TRIG_GPTM0_CH2O ((1UL << 2) | (3UL << 24) | (2UL << 16)) 189 #define ADC_TRIG_GPTM0_CH3O ((1UL << 2) | (4UL << 24) | (2UL << 16)) 190 191 #if (!LIBCFG_NO_GPTM1) 192 #define ADC_TRIG_GPTM1_MTO ((1UL << 2) | (0UL << 24) | (3UL << 16)) 193 #define ADC_TRIG_GPTM1_CH0O ((1UL << 2) | (1UL << 24) | (3UL << 16)) 194 #define ADC_TRIG_GPTM1_CH1O ((1UL << 2) | (2UL << 24) | (3UL << 16)) 195 #define ADC_TRIG_GPTM1_CH2O ((1UL << 2) | (3UL << 24) | (3UL << 16)) 196 #define ADC_TRIG_GPTM1_CH3O ((1UL << 2) | (4UL << 24) | (3UL << 16)) 197 #endif 198 199 /* (ADCTCR[1] << 1) | (ADCTSR[11:8] << 8) */ 200 #define ADC_TRIG_EXTI_0 ((1UL << 1) | ( 0UL << 8)) 201 #define ADC_TRIG_EXTI_1 ((1UL << 1) | ( 1UL << 8)) 202 #define ADC_TRIG_EXTI_2 ((1UL << 1) | ( 2UL << 8)) 203 #define ADC_TRIG_EXTI_3 ((1UL << 1) | ( 3UL << 8)) 204 #define ADC_TRIG_EXTI_4 ((1UL << 1) | ( 4UL << 8)) 205 #define ADC_TRIG_EXTI_5 ((1UL << 1) | ( 5UL << 8)) 206 #define ADC_TRIG_EXTI_6 ((1UL << 1) | ( 6UL << 8)) 207 #define ADC_TRIG_EXTI_7 ((1UL << 1) | ( 7UL << 8)) 208 #define ADC_TRIG_EXTI_8 ((1UL << 1) | ( 8UL << 8)) 209 #define ADC_TRIG_EXTI_9 ((1UL << 1) | ( 9UL << 8)) 210 #define ADC_TRIG_EXTI_10 ((1UL << 1) | (10UL << 8)) 211 #define ADC_TRIG_EXTI_11 ((1UL << 1) | (11UL << 8)) 212 #define ADC_TRIG_EXTI_12 ((1UL << 1) | (12UL << 8)) 213 #define ADC_TRIG_EXTI_13 ((1UL << 1) | (13UL << 8)) 214 #define ADC_TRIG_EXTI_14 ((1UL << 1) | (14UL << 8)) 215 #define ADC_TRIG_EXTI_15 ((1UL << 1) | (15UL << 8)) 216 217 218 #define IS_ADC_TRIG(REGTRIG) (IS_ADC_TRIG1(REGTRIG) || \ 219 IS_ADC_TRIG2(REGTRIG) || \ 220 IS_ADC_TRIG3(REGTRIG) || \ 221 IS_ADC_TRIG4(REGTRIG) || \ 222 IS_ADC_TRIG5(REGTRIG) || \ 223 IS_ADC_TRIG6(REGTRIG) || \ 224 IS_ADC_TRIG7(REGTRIG)) 225 226 #define IS_ADC_HPTRIG(REGTRIG) (IS_ADC_TRIG1(REGTRIG) || \ 227 IS_ADC_TRIG2(REGTRIG) || \ 228 IS_ADC_TRIG3(REGTRIG) || \ 229 IS_ADC_TRIG4(REGTRIG) || \ 230 IS_ADC_TRIG5(REGTRIG) || \ 231 IS_ADC_TRIG6(REGTRIG) || \ 232 IS_ADC_HPTRIG7(REGTRIG)) 233 234 #define IS_ADC_TRIG1(REGTRIG) (((REGTRIG) == ADC_TRIG_GPTM0_MTO) || \ 235 ((REGTRIG) == ADC_TRIG_GPTM0_CH0O) || \ 236 ((REGTRIG) == ADC_TRIG_GPTM0_CH1O) || \ 237 ((REGTRIG) == ADC_TRIG_GPTM0_CH2O) || \ 238 ((REGTRIG) == ADC_TRIG_GPTM0_CH3O) || \ 239 ((REGTRIG) == ADC_TRIG_BFTM0) || \ 240 ((REGTRIG) == ADC_TRIG_EXTI_0) || \ 241 ((REGTRIG) == ADC_TRIG_EXTI_1) || \ 242 ((REGTRIG) == ADC_TRIG_EXTI_2) || \ 243 ((REGTRIG) == ADC_TRIG_EXTI_3) || \ 244 ((REGTRIG) == ADC_TRIG_EXTI_4) || \ 245 ((REGTRIG) == ADC_TRIG_EXTI_5) || \ 246 ((REGTRIG) == ADC_TRIG_EXTI_6) || \ 247 ((REGTRIG) == ADC_TRIG_EXTI_7) || \ 248 ((REGTRIG) == ADC_TRIG_EXTI_8) || \ 249 ((REGTRIG) == ADC_TRIG_EXTI_9) || \ 250 ((REGTRIG) == ADC_TRIG_EXTI_10) || \ 251 ((REGTRIG) == ADC_TRIG_EXTI_11) || \ 252 ((REGTRIG) == ADC_TRIG_EXTI_12) || \ 253 ((REGTRIG) == ADC_TRIG_EXTI_13) || \ 254 ((REGTRIG) == ADC_TRIG_EXTI_14) || \ 255 ((REGTRIG) == ADC_TRIG_EXTI_15) || \ 256 ((REGTRIG) == ADC_TRIG_SOFTWARE)) 257 258 #define IS_ADC_TRIG2(REGTRIG) ((REGTRIG) == ADC_TRIG_BFTM1) 259 260 #if (!LIBCFG_NO_MCTM0) 261 #define IS_ADC_TRIG3(REGTRIG) (((REGTRIG) == ADC_TRIG_MCTM0_MTO) || \ 262 ((REGTRIG) == ADC_TRIG_MCTM0_CH0O) || \ 263 ((REGTRIG) == ADC_TRIG_MCTM0_CH1O) || \ 264 ((REGTRIG) == ADC_TRIG_MCTM0_CH2O) || \ 265 ((REGTRIG) == ADC_TRIG_MCTM0_CH3O) || \ 266 ((REGTRIG) == ADC_TRIG_BFTM1)) 267 #else 268 #define IS_ADC_TRIG3(REGTRIG) (0) 269 #endif 270 271 #if (!LIBCFG_NO_MCTM1) 272 #define IS_ADC_TRIG4(REGTRIG) (((REGTRIG) == ADC_TRIG_GPTM1_MTO) || \ 273 ((REGTRIG) == ADC_TRIG_GPTM1_CH0O) || \ 274 ((REGTRIG) == ADC_TRIG_GPTM1_CH1O) || \ 275 ((REGTRIG) == ADC_TRIG_GPTM1_CH2O) || \ 276 ((REGTRIG) == ADC_TRIG_GPTM1_CH3O)) 277 #else 278 #define IS_ADC_TRIG4(REGTRIG) (0) 279 #endif 280 281 #if (LIBCFG_PWM0) 282 #define IS_ADC_TRIG5(REGTRIG) (((REGTRIG) == ADC_TRIG_PWM0_MTO) || \ 283 ((REGTRIG) == ADC_TRIG_PWM0_CH0O) || \ 284 ((REGTRIG) == ADC_TRIG_PWM0_CH1O) || \ 285 ((REGTRIG) == ADC_TRIG_PWM0_CH2O) || \ 286 ((REGTRIG) == ADC_TRIG_PWM0_CH3O)) 287 #else 288 #define IS_ADC_TRIG5(REGTRIG) (0) 289 #endif 290 291 #if (LIBCFG_PWM1) 292 #define IS_ADC_TRIG6(REGTRIG) (((REGTRIG) == ADC_TRIG_PWM1_MTO) || \ 293 ((REGTRIG) == ADC_TRIG_PWM1_CH0O) || \ 294 ((REGTRIG) == ADC_TRIG_PWM1_CH1O) || \ 295 ((REGTRIG) == ADC_TRIG_PWM1_CH2O) || \ 296 ((REGTRIG) == ADC_TRIG_PWM1_CH3O)) 297 #else 298 #define IS_ADC_TRIG6(REGTRIG) (0) 299 #endif 300 301 #if (!LIBCFG_NO_CMP_TRIG_ADC) 302 #define IS_ADC_TRIG7(REGTRIG) (((REGTRIG) == ADC_TRIG_CMP0) || \ 303 ((REGTRIG) == ADC_TRIG_CMP1)) 304 #else 305 #define IS_ADC_TRIG7(REGTRIG) (0) 306 #endif 307 308 #if (!LIBCFG_NO_CMP_HPTRIG_ADC) 309 #define IS_ADC_HPTRIG7(REGTRIG) (((REGTRIG) == ADC_HPTRIG_CMP0) || \ 310 ((REGTRIG) == ADC_HPTRIG_CMP1)) 311 #else 312 #define IS_ADC_HPTRIG7(REGTRIG) (0) 313 #endif 314 315 316 #define ADC_INT_SINGLE_EOC (0x00000001) 317 #define ADC_INT_SUB_GROUP_EOC (0x00000002) 318 #define ADC_INT_CYCLE_EOC (0x00000004) 319 #define ADC_INT_HP_SINGLE_EOC (0x00000100) 320 #define ADC_INT_HP_SUB_GROUP_EOC (0x00000200) 321 #define ADC_INT_HP_CYCLE_EOC (0x00000400) 322 #define ADC_INT_AWD_LOWER (0x00010000) 323 #define ADC_INT_AWD_UPPER (0x00020000) 324 #define ADC_INT_DATA_OVERWRITE (0x01000000) 325 #define ADC_INT_HP_DATA_OVERWRITE (0x02000000) 326 327 #define IS_ADC_INT(INT) ((((INT) & 0xFCFCF8F8) == 0) && ((INT) != 0)) 328 329 330 #define ADC_FLAG_SINGLE_EOC (0x00000001) 331 #define ADC_FLAG_SUB_GROUP_EOC (0x00000002) 332 #define ADC_FLAG_CYCLE_EOC (0x00000004) 333 #define ADC_FLAG_HP_SINGLE_EOC (0x00000100) 334 #define ADC_FLAG_HP_SUB_GROUP_EOC (0x00000200) 335 #define ADC_FLAG_HP_CYCLE_EOC (0x00000400) 336 #define ADC_FLAG_AWD_LOWER (0x00010000) 337 #define ADC_FLAG_AWD_UPPER (0x00020000) 338 #define ADC_FLAG_DATA_OVERWRITE (0x01000000) 339 #define ADC_FLAG_HP_DATA_OVERWRITE (0x02000000) 340 341 #define IS_ADC_FLAG(FLAG) ((((FLAG) & 0xFCFCF8F8) == 0) && ((FLAG) != 0)) 342 343 344 #define ADC_REGULAR_DATA0 (0) 345 #define ADC_REGULAR_DATA1 (1) 346 #define ADC_REGULAR_DATA2 (2) 347 #define ADC_REGULAR_DATA3 (3) 348 #define ADC_REGULAR_DATA4 (4) 349 #define ADC_REGULAR_DATA5 (5) 350 #define ADC_REGULAR_DATA6 (6) 351 #define ADC_REGULAR_DATA7 (7) 352 #define ADC_REGULAR_DATA8 (8) 353 #define ADC_REGULAR_DATA9 (9) 354 #define ADC_REGULAR_DATA10 (10) 355 #define ADC_REGULAR_DATA11 (11) 356 #define ADC_REGULAR_DATA12 (12) 357 #define ADC_REGULAR_DATA13 (13) 358 #define ADC_REGULAR_DATA14 (14) 359 #define ADC_REGULAR_DATA15 (15) 360 361 #define IS_ADC_REGULAR_DATA(DATA) ((DATA) < 16) 362 363 364 #define ADC_HP_DATA0 (0) 365 #define ADC_HP_DATA1 (1) 366 #define ADC_HP_DATA2 (2) 367 #define ADC_HP_DATA3 (3) 368 369 #define IS_ADC_HP_DATA(DATA) ((DATA) < 4) 370 371 372 #define ADC_AWD_DISABLE (u8)0x00 373 #define ADC_AWD_ALL_LOWER (u8)0x05 374 #define ADC_AWD_ALL_UPPER (u8)0x06 375 #define ADC_AWD_ALL_LOWER_UPPER (u8)0x07 376 #define ADC_AWD_SINGLE_LOWER (u8)0x01 377 #define ADC_AWD_SINGLE_UPPER (u8)0x02 378 #define ADC_AWD_SINGLE_LOWER_UPPER (u8)0x03 379 380 #define IS_ADC_AWD(AWD) (((AWD) == ADC_AWD_DISABLE) || \ 381 ((AWD) == ADC_AWD_ALL_LOWER) || \ 382 ((AWD) == ADC_AWD_ALL_UPPER) || \ 383 ((AWD) == ADC_AWD_ALL_LOWER_UPPER) || \ 384 ((AWD) == ADC_AWD_SINGLE_LOWER) || \ 385 ((AWD) == ADC_AWD_SINGLE_UPPER) || \ 386 ((AWD) == ADC_AWD_SINGLE_LOWER_UPPER)) 387 388 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) < 4096) 389 390 #define ADC_PDMA_REGULAR_SINGLE (0x00000001) 391 #define ADC_PDMA_REGULAR_SUBGROUP (0x00000002) 392 #define ADC_PDMA_REGULAR_CYCLE (0x00000004) 393 394 #define ADC_PDMA_HP_SINGLE (0x00000100) 395 #define ADC_PDMA_HP_SUBGROUP (0x00000200) 396 #define ADC_PDMA_HP_CYCLE (0x00000400) 397 398 #define IS_ADC_PDMA(PDMA) (((PDMA) == ADC_PDMA_REGULAR_SINGLE) || \ 399 ((PDMA) == ADC_PDMA_REGULAR_SUBGROUP) || \ 400 ((PDMA) == ADC_PDMA_REGULAR_CYCLE) || \ 401 ((PDMA) == ADC_PDMA_HP_SINGLE) || \ 402 ((PDMA) == ADC_PDMA_HP_SUBGROUP) || \ 403 ((PDMA) == ADC_PDMA_HP_CYCLE)) 404 405 406 #define IS_ADC_INPUT_SAMPLING_TIME(TIME) ((TIME) <= 255) 407 408 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) < 4096) 409 410 #define IS_ADC_REGULAR_RANK(RANK) ((RANK) < 16) 411 412 #define IS_ADC_HP_RANK(RANK) ((RANK) < 4) 413 414 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 16)) 415 #define IS_ADC_REGULAR_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 16)) 416 417 #define IS_ADC_HP_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 4)) 418 #define IS_ADC_HP_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 4)) 419 420 #define ADC_VREF_1V215 (0ul << 4) 421 #define ADC_VREF_2V0 (1ul << 4) 422 #define ADC_VREF_2V5 (2ul << 4) 423 #define ADC_VREF_2V7 (3ul << 4) 424 425 #define IS_ADC_VREF_SEL(SEL) ((SEL == ADC_VREF_1V215) || \ 426 (SEL == ADC_VREF_2V0) || \ 427 (SEL == ADC_VREF_2V5) || \ 428 (SEL == ADC_VREF_2V7)) 429 430 typedef enum 431 { 432 ADC_ALIGN_RIGHT = (0 << 14), 433 ADC_ALIGN_LEFT = (1 << 14), 434 } ADC_ALIGN_Enum; 435 436 #define IS_ADC_ALIGN(ALIGN) (((ALIGN) == ADC_ALIGN_RIGHT) || ((ALIGN) == ADC_ALIGN_LEFT)) 437 /** 438 * @} 439 */ 440 441 /* Exported functions --------------------------------------------------------------------------------------*/ 442 /** @defgroup ADC_Exported_Functions ADC exported functions 443 * @{ 444 */ 445 void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn); 446 void ADC_Reset(HT_ADC_TypeDef* HT_ADCn); 447 void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); 448 449 void ADC_SamplingTimeConfig(HT_ADC_TypeDef* HT_ADCn, u8 SampleClock); // Apply for the specific model only 450 void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock); 451 void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); 452 void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); 453 454 void ADC_HPChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock); 455 void ADC_HPGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); 456 void ADC_HPTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); 457 458 void ADC_ChannelDataAlign(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ADC_ALIGN_Enum ADC_ALIGN_x); 459 void ADC_ChannelOffsetValue(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u16 OffsetValue); 460 void ADC_ChannelOffsetCmd(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ControlStatus NewState); 461 462 void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); 463 void ADC_HPSoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); 464 465 u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn); 466 u16 ADC_GetHPConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_HP_DATAn); 467 468 void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState); 469 FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); 470 void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); 471 FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x); 472 473 void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x); 474 void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n); 475 void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER); 476 477 void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState); 478 479 void ADC_VREFCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); 480 void ADC_VREFConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_VREF_x); 481 /** 482 * @} 483 */ 484 485 486 /** 487 * @} 488 */ 489 490 /** 491 * @} 492 */ 493 494 #ifdef __cplusplus 495 } 496 #endif 497 498 #endif 499