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Searched refs:AES_BLOCK_SIZE (Results 1 – 5 of 5) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/test/ce/
A Dtest_ce.c86 uint8_t iv_next[AES_BLOCK_SIZE] = {0}; in aes_test()
117 memset(iv_next, 0, AES_BLOCK_SIZE); in aes_test()
127 aes_ctx->dst_length = CE_ROUND_UP(aes_ctx->src_length, AES_BLOCK_SIZE); in aes_test()
152 blk_num = enc_len / AES_BLOCK_SIZE; in aes_test()
155 … memcpy(enc_buffer, aes_enc[m - AES_MODE_ECB][i][j], (blk_num - 2) * AES_BLOCK_SIZE); in aes_test()
156 memcpy(enc_buffer + (blk_num - 2) * AES_BLOCK_SIZE, in aes_test()
157 aes_enc[m - AES_MODE_ECB][i][j] + (blk_num - 1) * AES_BLOCK_SIZE, in aes_test()
158 AES_BLOCK_SIZE); in aes_test()
159 memcpy(enc_buffer + (blk_num - 1) * AES_BLOCK_SIZE, in aes_test()
160 aes_enc[m - AES_MODE_ECB][i][j] + (blk_num - 2) * AES_BLOCK_SIZE, in aes_test()
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/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_sdp_drv.h115 #define AES_BLOCK_SIZE (16U) /**< AES block size in bytes */ macro
119 #define SM4_BLOCK_SIZE (AES_BLOCK_SIZE) /**< SM4 block size in bytes */
164 uint32_t buf0[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf0 */
165 uint32_t buf1[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf1 */
166 uint32_t buf2[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf2 */
167 uint32_t buf3[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf3 */
/bsp/allwinner/libraries/sunxi-hal/hal/source/ce/
A Dce_common.c223 blk_num = ctx->src_length / AES_BLOCK_SIZE; in ce_aes_sw_padding()
224 last_blk_size = ctx->src_length % AES_BLOCK_SIZE; in ce_aes_sw_padding()
227 padding_size = AES_BLOCK_SIZE - last_blk_size; in ce_aes_sw_padding()
230 ctx->padding_len = AES_BLOCK_SIZE; in ce_aes_sw_padding()
235 return blk_num * AES_BLOCK_SIZE; in ce_aes_sw_padding()
259 hal_ce_iv_set(req_ctx->iv, AES_BLOCK_SIZE, task); in ce_aes_start()
260 hal_dcache_clean((unsigned long)req_ctx->iv, AES_BLOCK_SIZE); in ce_aes_start()
371 && (req_ctx->src_length % AES_BLOCK_SIZE != 0)) { in ce_aes_check_ctx_vaild()
373 req_ctx->src_length, AES_BLOCK_SIZE); in ce_aes_check_ctx_vaild()
385 CE_ROUND_UP(req_ctx->src_length, AES_BLOCK_SIZE)); in ce_aes_check_ctx_vaild()
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/bsp/allwinner/libraries/sunxi-hal/include/hal/
A Dsunxi_hal_ce.h21 #define AES_BLOCK_SIZE (16) macro
33 uint8_t padding[AES_BLOCK_SIZE];
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_sdp_drv.c38 #define AES_BLOCK_SIZE (16U) macro

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