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Searched refs:AM_REG (Results 1 – 23 of 23) sorted by relevance

/bsp/apollo2/libraries/drivers/hal/
A Dam_hal_cachectrl.c130 AM_REG(CACHECTRL, CACHECFG) = ui32ConfigValue; in am_hal_cachectrl_enable()
169 AM_REG(CACHECTRL, CACHECFG) = ui32ConfigValue; in am_hal_cachectrl_enable()
189 ui32CacheCfg = AM_REG(CACHECTRL, CACHECFG); in am_hal_cachectrl_disable()
200 AM_REG(CACHECTRL, CACHECFG) = ui32CacheCfg; in am_hal_cachectrl_disable()
205 AM_REG(CACHECTRL, CACHECTRL); in am_hal_cachectrl_disable()
206 AM_REG(CACHECTRL, CACHECTRL); in am_hal_cachectrl_disable()
207 AM_REG(CACHECTRL, CACHECTRL); in am_hal_cachectrl_disable()
353 AM_REG(CACHECTRL, CACHECFG) = u32ConfigValue; in am_hal_cachectrl_config()
411 AM_REG(CACHECTRL, CACHECFG) &= ~u32DisableMask; in am_hal_cachectrl_cache_enables()
416 AM_REG(CACHECTRL, CACHECFG) |= u32EnableMask; in am_hal_cachectrl_cache_enables()
[all …]
A Dam_hal_clkgen.c95 AM_REG(CLKGEN, CLKKEY) = 0; in am_hal_clkgen_sysclk_select()
146 AM_REG(CLKGEN, INTEN) |= ui32Interrupt; in am_hal_clkgen_int_enable()
164 return AM_REG(CLKGEN, INTEN); in am_hal_clkgen_int_enable_get()
211 AM_REG(CLKGEN, INTSET) = ui32Interrupt; in am_hal_clkgen_int_set()
241 u32RetVal &= AM_REG(CLKGEN, INTEN); in am_hal_clkgen_int_status_get()
246 return AM_REG(CLKGEN, INTSTAT); in am_hal_clkgen_int_status_get()
375 AM_REG(CLKGEN, CLKOUT) = 0; in am_hal_clkgen_clkout_disable()
416 AM_REG(CLKGEN, UARTEN) &= ui32Mask; in am_hal_clkgen_uarten_set()
417 AM_REG(CLKGEN, UARTEN) |= ui32UartEn; in am_hal_clkgen_uarten_set()
463 AM_REG(CLKGEN, HFADJ) = in am_hal_clkgen_hfrc_adjust_enable()
[all …]
A Dam_hal_tpiu.c106 AM_REG(TPIU, CSPSR) = 1 << (ui32PortWidth - 1); in am_hal_tpiu_port_width_set()
127 ui32WidthValue = AM_REG(TPIU, SSPSR); in am_hal_tpiu_supported_port_width_get()
169 ui32Temp = AM_REG(TPIU, CSPSR); in am_hal_tpiu_port_width_get()
208 AM_REG(MCUCTRL, TPIUCTRL) |= psConfig->ui32TraceClkIn; in am_hal_tpiu_configure()
213 AM_REG(TPIU, SPPR) = psConfig->ui32PinProtocol; in am_hal_tpiu_configure()
224 AM_REG(TPIU, ACPR) = psConfig->ui32ClockPrescaler; in am_hal_tpiu_configure()
260 AM_REG(TPIU, FFCR) = 0; in am_hal_tpiu_enable()
267 AM_REG(TPIU, CSPSR) = AM_REG_TPIU_CSPSR_CWIDTH_1BIT; in am_hal_tpiu_enable()
304 AM_REG(TPIU, SPPR) = AM_REG_TPIU_SPPR_TXMODE_UART; in am_hal_tpiu_enable()
329 AM_REG(TPIU, ACPR) = psConfig->ui32ClockPrescaler; in am_hal_tpiu_enable()
[all …]
A Dam_hal_pdm.c73 AM_REG(PDM, PCFG) = psConfig->ui32PDMConfigReg; in am_hal_pdm_config()
78 AM_REG(PDM, VCFG) = psConfig->ui32VoiceConfigReg; in am_hal_pdm_config()
83 AM_REG(PDM, FTHR) = psConfig->ui32FIFOThreshold; in am_hal_pdm_config()
104 AM_REG(PDM, PCFG) |= AM_REG_PDM_PCFG_PDMCORE_EN; in am_hal_pdm_enable()
105 AM_REG(PDM, VCFG) |= ( AM_REG_PDM_VCFG_IOCLKEN_EN | in am_hal_pdm_enable()
122 AM_REG(PDM, PCFG) &= ~ AM_REG_PDM_PCFG_PDMCORE_EN; in am_hal_pdm_disable()
123 AM_REG(PDM, VCFG) &= ~ ( AM_REG_PDM_VCFG_IOCLKEN_EN | in am_hal_pdm_disable()
144 uint32_t u32RetVal = AM_REG(PDM, INTSTAT); in am_hal_pdm_int_status_get()
145 return u32RetVal & AM_REG(PDM, INTEN); in am_hal_pdm_int_status_get()
149 return AM_REG(PDM, INTSTAT); in am_hal_pdm_int_status_get()
A Dam_hal_rtc.c188 AM_REG(RTC, INTEN) |= ui32Interrupt; in am_hal_rtc_int_enable()
211 return AM_REG(RTC, INTEN); in am_hal_rtc_int_enable_get()
360 AM_REG(RTC, CTRLOW) = in am_hal_rtc_time_set()
369 AM_REG(RTC, CTRUP) = in am_hal_rtc_time_set()
402 ui32RTCLow = AM_REG(RTC, CTRLOW); in am_hal_rtc_time_get()
403 ui32RTCUp = AM_REG(RTC, CTRUP); in am_hal_rtc_time_get()
577 AM_REG(RTC, RTCCTL) |= in am_hal_rtc_alarm_set()
595 AM_REG(RTC, ALMUP) = in am_hal_rtc_alarm_set()
603 AM_REG(RTC, ALMLOW) = in am_hal_rtc_alarm_set()
629 ui32ALMLow = AM_REG(RTC, ALMLOW); in am_hal_rtc_alarm_get()
[all …]
A Dam_hal_vcomp.c73 AM_REG(VCOMP, CFG) = (psConfig->ui32LevelSelect | in am_hal_vcomp_config()
125 AM_REG(VCOMP, PWDKEY) = 0; in am_hal_vcomp_enable()
140 AM_REG(VCOMP, PWDKEY) = AM_REG_VCOMP_PWDKEY_KEYVAL; in am_hal_vcomp_disable()
166 uint32_t u32RetVal = AM_REG(VCOMP, INTSTAT); in am_hal_vcomp_int_status_get()
167 return u32RetVal & AM_REG(VCOMP, INTEN); in am_hal_vcomp_int_status_get()
171 return AM_REG(VCOMP, INTSTAT); in am_hal_vcomp_int_status_get()
194 AM_REG(VCOMP, INTSET) = ui32Interrupt; in am_hal_vcomp_int_set()
216 AM_REG(VCOMP, INTCLR) = ui32Interrupt; in am_hal_vcomp_int_clear()
238 AM_REG(VCOMP, INTEN) |= ui32Interrupt; in am_hal_vcomp_int_enable()
257 return AM_REG(VCOMP, INTEN); in am_hal_vcomp_int_enable_get()
[all …]
A Dam_hal_mcuctrl.c109 psDevice->ui32ChipPN = AM_REG(MCUCTRL, CHIP_INFO); in am_hal_mcuctrl_device_info_get()
114 psDevice->ui32ChipID0 = AM_REG(MCUCTRL, CHIPID0); in am_hal_mcuctrl_device_info_get()
119 psDevice->ui32ChipID1 = AM_REG(MCUCTRL, CHIPID1); in am_hal_mcuctrl_device_info_get()
124 psDevice->ui32ChipRev = AM_REG(MCUCTRL, CHIPREV); in am_hal_mcuctrl_device_info_get()
129 psDevice->ui32ChipPN = AM_REG(MCUCTRL, CHIP_INFO); in am_hal_mcuctrl_device_info_get()
134 psDevice->ui32ChipID0 = AM_REG(MCUCTRL, CHIPID0); in am_hal_mcuctrl_device_info_get()
139 psDevice->ui32ChipID1 = AM_REG(MCUCTRL, CHIPID1); in am_hal_mcuctrl_device_info_get()
144 psDevice->ui32ChipRev = AM_REG(MCUCTRL, CHIPREV); in am_hal_mcuctrl_device_info_get()
149 psDevice->ui32VendorID = AM_REG(MCUCTRL, VENDORID); in am_hal_mcuctrl_device_info_get()
266 ui32FaultStat = AM_REG(MCUCTRL, FAULTSTATUS); in am_hal_mcuctrl_fault_status()
[all …]
A Dam_hal_systick.c82 AM_REG(SYSTICK, SYSTCSR) |= AM_REG_SYSTICK_SYSTCSR_ENABLE_M; in am_hal_systick_start()
105 AM_REG(SYSTICK, SYSTCSR) &= ~AM_REG_SYSTICK_SYSTCSR_ENABLE_M; in am_hal_systick_stop()
123 AM_REG(SYSTICK, SYSTCSR) |= AM_REG_SYSTICK_SYSTCSR_TICKINT_M; in am_hal_systick_int_enable()
141 AM_REG(SYSTICK, SYSTCSR) &= ~AM_REG_SYSTICK_SYSTCSR_TICKINT_M; in am_hal_systick_int_disable()
178 AM_REG(SYSTICK, SYSTCSR) = 0x0; in am_hal_systick_reset()
199 AM_REG(SYSTICK, SYSTRVR) = ui32LoadVal; in am_hal_systick_load()
217 return AM_REG(SYSTICK, SYSTCVR); in am_hal_systick_count()
249 AM_REG(SYSTICK, SYSTRVR) = u32Ticks; in am_hal_systick_wait_ticks()
254 AM_REG(SYSTICK, SYSTCVR) = 0x0; in am_hal_systick_wait_ticks()
259 AM_REG(SYSTICK, SYSTCSR) = AM_REG_SYSTICK_SYSTCSR_ENABLE_M; in am_hal_systick_wait_ticks()
[all …]
A Dam_hal_adc.c280 ui32FIFOValue = AM_REG(ADC, FIFO); in am_hal_adc_fifo_peek()
308 ui32FIFOValue = AM_REG(ADC, FIFO); in am_hal_adc_fifo_pop()
313 AM_REG(ADC, FIFO) = 0; in am_hal_adc_fifo_pop()
336 AM_REG(ADC, SWT) = 0x37; in am_hal_adc_trigger()
392 AM_REG(ADC, INTEN) |= ui32Interrupt; in am_hal_adc_int_enable()
410 return AM_REG(ADC, INTEN); in am_hal_adc_int_enable_get()
430 AM_REG(ADC, INTEN) &= ~ui32Interrupt; in am_hal_adc_int_disable()
450 AM_REG(ADC, INTCLR) = ui32Interrupt; in am_hal_adc_int_clear()
470 AM_REG(ADC, INTSET) = ui32Interrupt; in am_hal_adc_int_set()
493 u32RetVal &= AM_REG(ADC, INTSTAT); in am_hal_adc_int_status_get()
[all …]
A Dam_hal_pdm.h486 #define am_hal_pdm_fifo_depth_read() (AM_REG(PDM, FR))
493 #define am_hal_pdm_fifo_data_read() (AM_REG(PDM, FRD))
500 #define am_hal_pdm_fifo_flush() (AM_REG(PDM, FLUSH) = 0)
509 #define am_hal_pdm_pcfg_set(Value) (AM_REG(PDM, PCFG) = Value)
516 #define am_hal_pdm_pcfg_get() (AM_REG(PDM, PCFG))
523 #define am_hal_pdm_vcfg_set(Value) (AM_REG(PDM, VCFG) = Value)
530 #define am_hal_pdm_vcfg_get() (AM_REG(PDM, VCFG))
537 #define am_hal_pdm_thresh_set(thresh) (AM_REG(PDM, FTHR) = thresh)
544 #define am_hal_pdm_thresh_get() (AM_REG(PDM, FTHR))
598 #define am_hal_pdm_int_enable(intrpt) (AM_REG(PDM, INTEN) |= intrpt)
[all …]
A Dam_hal_ios.c234 AM_REG(IOSLAVE, FIFOCFG) = ui32LRAMConfig; in am_hal_ios_config()
358 return AM_REG(IOSLAVE, REGACCINTEN); in am_hal_ios_access_int_enable_get()
437 return AM_REG(IOSLAVE, REGACCINTSTAT); in am_hal_ios_access_int_status_get()
458 AM_REG(IOSLAVE, INTEN) |= ui32Interrupt; in am_hal_ios_int_enable()
476 return AM_REG(IOSLAVE, INTEN); in am_hal_ios_int_enable_get()
516 AM_REG(IOSLAVE, INTCLR) = ui32Interrupt; in am_hal_ios_int_clear()
536 AM_REG(IOSLAVE, INTSET) = ui32Interrupt; in am_hal_ios_int_set()
602 return AM_REG(IOSLAVE, INTSTAT); in am_hal_ios_int_status_get()
1204 AM_REG(IOSLAVE, FUPD) = 0x1; in am_hal_ios_fifo_ptr_set()
1209 AM_REG(IOSLAVE, FIFOPTR) = ui32Offset; in am_hal_ios_fifo_ptr_set()
[all …]
A Dam_hal_stimer.c73 ui32CurrVal = AM_REG(CTIMER, STCFG); in am_hal_stimer_config()
78 AM_REG(CTIMER, STCFG) = ui32STimerConfig; in am_hal_stimer_config()
107 return AM_REG(CTIMER, STTMR); in am_hal_stimer_counter_get()
125 AM_REG(CTIMER, STCFG) |= AM_REG_CTIMER_STCFG_CLEAR_M; in am_hal_stimer_counter_clear()
130 AM_REG(CTIMER, STCFG) &= ~AM_REG_CTIMER_STCFG_CLEAR_M; in am_hal_stimer_counter_clear()
161 cfgVal = AM_REG(CTIMER, STCFG); in am_hal_stimer_compare_delta_set()
168 AM_REG(CTIMER, STCFG) &= ~((AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance)); in am_hal_stimer_compare_delta_set()
175 AM_REG(CTIMER, STCFG) |= cfgVal & (AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance); in am_hal_stimer_compare_delta_set()
263 AM_REG(CTIMER, CAPTURE_CONTROL) |= ui32CapCtrl; in am_hal_stimer_capture_start()
282 AM_REG(CTIMER, CAPTURE_CONTROL) &= in am_hal_stimer_capture_stop()
A Dam_hal_pwrctrl.c103 AM_REG(PWRCTRL, DEVICEEN) |= ui32Peripheral; in am_hal_pwrctrl_periph_enable()
151 AM_REG(PWRCTRL, DEVICEEN) &= ~ui32Peripheral; in am_hal_pwrctrl_periph_disable()
367 AM_REG(PWRCTRL, MEMEN) &= ~ui32MemDisMask; in am_hal_pwrctrl_memory_enable()
375 AM_REG(PWRCTRL, MEMEN) |= ui32MemEnMask; in am_hal_pwrctrl_memory_enable()
386 ( AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrStatDisMask ) ); in am_hal_pwrctrl_memory_enable()
398 (( AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrStatEnMask ) in am_hal_pwrctrl_memory_enable()
424 while ( ( AM_REG(PWRCTRL, POWERSTATUS) & in am_hal_pwrctrl_bucks_init()
469 while ( ( AM_REG(PWRCTRL, POWERSTATUS) & in am_hal_pwrctrl_bucks_enable()
506 AM_REG(PWRCTRL, SUPPLYSRC) &= in am_hal_pwrctrl_bucks_disable()
541 AM_REG(PWRCTRL, SRAMCTRL) |= in am_hal_pwrctrl_low_power_init()
[all …]
A Dam_hal_itm.c81 AM_REG(SYSCTRL, DEMCR) |= AM_REG_SYSCTRL_DEMCR_TRCENA(1); in am_hal_itm_enable()
82 while ( !(AM_REG(SYSCTRL, DEMCR) & AM_REG_SYSCTRL_DEMCR_TRCENA(1)) ); in am_hal_itm_enable()
138 while ( AM_REG(ITM, TCR) & AM_REG_ITM_TCR_BUSY(1) ); in am_hal_itm_disable()
145 AM_REG(ITM, TCR) &= ~AM_REG_ITM_TCR_ITM_ENABLE(1); in am_hal_itm_disable()
146 while ( AM_REG(ITM, TCR) & (AM_REG_ITM_TCR_ITM_ENABLE(1) | AM_REG_ITM_TCR_BUSY(1)) ); in am_hal_itm_disable()
153 AM_REG(SYSCTRL, DEMCR) &= ~AM_REG_SYSCTRL_DEMCR_TRCENA(1); in am_hal_itm_disable()
158 AM_REG(MCUCTRL, TPIUCTRL) = AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_0MHz | in am_hal_itm_disable()
178 while (AM_REG(ITM, TCR) & AM_REG_ITM_TCR_BUSY(1)); in am_hal_itm_not_busy()
A Dam_hal_wdt.c139 AM_REG(RSTGEN, CFG) |= AM_REG_RSTGEN_CFG_WDREN_M; in am_hal_wdt_init()
146 AM_REG(RSTGEN, CFG) &= ~AM_REG_RSTGEN_CFG_WDREN_M; in am_hal_wdt_init()
244 uint32_t u32RetVal = AM_REG(WDT, INTSTAT); in am_hal_wdt_int_status_get()
245 return u32RetVal & AM_REG(WDT, INTEN); in am_hal_wdt_int_status_get()
249 return AM_REG(WDT, INTSTAT); in am_hal_wdt_int_status_get()
265 AM_REG(WDT, INTSET) = AM_REG_WDT_INTSET_WDT_M; in am_hal_wdt_int_set()
295 AM_REG(WDT, INTEN) |= AM_REG_WDT_INTSET_WDT_M; in am_hal_wdt_int_enable()
310 return AM_REG(WDT, INTEN); in am_hal_wdt_int_enable_get()
325 AM_REG(WDT, INTEN) &= ~AM_REG_WDT_INTSET_WDT_M; in am_hal_wdt_int_disable()
A Dam_hal_reset.c70 AM_REG(RSTGEN, CFG) = ui32Config; in am_hal_reset_init()
92 AM_REG(RSTGEN, SWPOR) = in am_hal_reset_por()
117 AM_REG(RSTGEN, SWPOI) = in am_hal_reset_poi()
138 return AM_REG(RSTGEN, STAT); in am_hal_reset_status_get()
152 AM_REG(RSTGEN, CLRSTAT) = AM_REG_RSTGEN_CLRSTAT_CLRSTAT(1); in am_hal_reset_status_clear()
A Dam_hal_gpio.c204 AM_REG(GPIO, INT1EN) |= (ui64InterruptMask >> 32); in am_hal_gpio_int_enable()
205 AM_REG(GPIO, INT0EN) |= (ui64InterruptMask & 0xFFFFFFFF); in am_hal_gpio_int_enable()
252 AM_REG(GPIO, INT1EN) &= ~(ui64InterruptMask >> 32); in am_hal_gpio_int_disable()
253 AM_REG(GPIO, INT0EN) &= ~(ui64InterruptMask & 0xFFFFFFFF); in am_hal_gpio_int_disable()
277 AM_REG(GPIO, INT1CLR) = (ui64InterruptMask >> 32); in am_hal_gpio_int_clear()
278 AM_REG(GPIO, INT0CLR) = (ui64InterruptMask & 0xFFFFFFFF); in am_hal_gpio_int_clear()
301 AM_REG(GPIO, INT1SET) = (ui64InterruptMask >> 32); in am_hal_gpio_int_set()
302 AM_REG(GPIO, INT0SET) = (ui64InterruptMask & 0xFFFFFFFF); in am_hal_gpio_int_set()
A Dam_hal_sysctrl.c157 ui32SupplySrc = AM_REG(PWRCTRL, SUPPLYSRC); in buckZX_chk()
168 ui32SupplySrc = AM_REG(PWRCTRL, DEVICEEN); in buckZX_chk()
465 AM_REG(SYSCTRL, CPACR) = (AM_REG_SYSCTRL_CPACR_CP11(0x3) | in am_hal_sysctrl_fpu_enable()
485 AM_REG(SYSCTRL, CPACR) = 0x00000000 & in am_hal_sysctrl_fpu_disable()
521 AM_REG(SYSCTRL, FPCCR) |= (AM_REG_SYSCTRL_FPCCR_ASPEN(0x1) | in am_hal_sysctrl_fpu_stacking_enable()
529 AM_REG(SYSCTRL, FPCCR) |= AM_REG_SYSCTRL_FPCCR_ASPEN(0x1); in am_hal_sysctrl_fpu_stacking_enable()
550 AM_REG(SYSCTRL, FPCCR) &= ~(AM_REG_SYSCTRL_FPCCR_ASPEN(0x1) | in am_hal_sysctrl_fpu_stacking_disable()
569 AM_REG(SYSCTRL, AIRCR) = AM_REG_SYSCTRL_AIRCR_VECTKEY(0x5FA) | in am_hal_sysctrl_aircr_reset()
A Dam_hal_interrupt.c79 AM_REG(NVIC, ISER0) = 0x1 << ((ui32Interrupt - 16) & 0x1F); in am_hal_interrupt_enable()
128 AM_REG(NVIC, ICER0) = 0x1 << ((ui32Interrupt - 16) & 0x1F); in am_hal_interrupt_disable()
227 AM_REG(NVIC, ISPR0) = 0x1 << ((ui32Interrupt - 16) & 0x1F); in am_hal_interrupt_pend_set()
264 AM_REG(NVIC, ICPR0) = 0x1 << ((ui32Interrupt - 16) & 0x1F); in am_hal_interrupt_pend_clear()
A Dam_hal_pwrctrl.h223 while ( !(AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrOnStat) ); \
A Dam_hal_uart.c535 (AM_REG(CLKGEN, UARTEN) & AM_HAL_CLKGEN_UARTEN_UARTENn_M(ui32Module)) >> in am_hal_uart_power_off_save()
A Dam_hal_iom.c370 if ( (AM_REG(MCUCTRL, CHIPREV) & 0xFF) == AM_REG_MCUCTRL_CHIPREV_REVMAJ_B ) in isRevB0()
393 if ( (AM_REG(MCUCTRL, CHIPREV) & 0xFF) == in isRevB2()
/bsp/apollo2/libraries/drivers/regs/
A Dam_reg_macros.h121 #define AM_REG(module, reg) \ macro

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