1 //***************************************************************************** 2 // 3 // am_reg_sysctrl.h 4 //! @file 5 //! 6 //! @brief Register macros for the SYSCTRL module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_SYSCTRL_H 45 #define AM_REG_SYSCTRL_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_SYSCTRL_NUM_MODULES 1 53 #define AM_REG_SYSCTRLn(n) \ 54 (REG_SYSCTRL_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_SYSCTRL_ICTR_O 0xE000E004 62 #define AM_REG_SYSCTRL_ACTLR_O 0xE000E008 63 #define AM_REG_SYSCTRL_ICSR_O 0xE000ED04 64 #define AM_REG_SYSCTRL_VTOR_O 0xE000ED08 65 #define AM_REG_SYSCTRL_AIRCR_O 0xE000ED0C 66 #define AM_REG_SYSCTRL_SCR_O 0xE000ED10 67 #define AM_REG_SYSCTRL_CCR_O 0xE000ED14 68 #define AM_REG_SYSCTRL_SHPR1_O 0xE000ED18 69 #define AM_REG_SYSCTRL_SHPR2_O 0xE000ED1C 70 #define AM_REG_SYSCTRL_SHPR3_O 0xE000ED20 71 #define AM_REG_SYSCTRL_SHCSR_O 0xE000ED24 72 #define AM_REG_SYSCTRL_CFSR_O 0xE000ED28 73 #define AM_REG_SYSCTRL_HFSR_O 0xE000ED2C 74 #define AM_REG_SYSCTRL_MMFAR_O 0xE000ED34 75 #define AM_REG_SYSCTRL_BFAR_O 0xE000ED38 76 #define AM_REG_SYSCTRL_CPACR_O 0xE000ED88 77 #define AM_REG_SYSCTRL_DEMCR_O 0xE000EDFC 78 #define AM_REG_SYSCTRL_STIR_O 0xE000EF00 79 #define AM_REG_SYSCTRL_FPCCR_O 0xE000EF34 80 #define AM_REG_SYSCTRL_FPCAR_O 0xE000EF38 81 #define AM_REG_SYSCTRL_FPDSCR_O 0xE000EF3C 82 83 //***************************************************************************** 84 // 85 // SYSCTRL_ICTR - Interrupt Controller Type Register (NVIC) 86 // 87 //***************************************************************************** 88 // Total number of interrupt lines in groups of 32. 89 #define AM_REG_SYSCTRL_ICTR_INTLINESNUM_S 0 90 #define AM_REG_SYSCTRL_ICTR_INTLINESNUM_M 0x0000000F 91 #define AM_REG_SYSCTRL_ICTR_INTLINESNUM(n) (((uint32_t)(n) << 0) & 0x0000000F) 92 93 //***************************************************************************** 94 // 95 // SYSCTRL_ACTLR - Auxilliary Control Register 96 // 97 //***************************************************************************** 98 // Disables lazy stacking of floating point context. 99 #define AM_REG_SYSCTRL_ACTLR_DISFPCA_S 9 100 #define AM_REG_SYSCTRL_ACTLR_DISFPCA_M 0x00000200 101 #define AM_REG_SYSCTRL_ACTLR_DISFPCA(n) (((uint32_t)(n) << 9) & 0x00000200) 102 103 // Disables floating point instructions completing out of order with respect to 104 // integer instructions. 105 #define AM_REG_SYSCTRL_ACTLR_DISOOFP_S 8 106 #define AM_REG_SYSCTRL_ACTLR_DISOOFP_M 0x00000100 107 #define AM_REG_SYSCTRL_ACTLR_DISOOFP(n) (((uint32_t)(n) << 8) & 0x00000100) 108 109 // Disables folding of IT instructions. 110 #define AM_REG_SYSCTRL_ACTLR_DISFOLD_S 2 111 #define AM_REG_SYSCTRL_ACTLR_DISFOLD_M 0x00000004 112 #define AM_REG_SYSCTRL_ACTLR_DISFOLD(n) (((uint32_t)(n) << 2) & 0x00000004) 113 114 // Disables write buffer use during default memory map accesses. 115 #define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF_S 1 116 #define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF_M 0x00000002 117 #define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF(n) (((uint32_t)(n) << 1) & 0x00000002) 118 119 // Disables interruption of multi-cycle instructions. 120 #define AM_REG_SYSCTRL_ACTLR_DISMCYCINT_S 0 121 #define AM_REG_SYSCTRL_ACTLR_DISMCYCINT_M 0x00000001 122 #define AM_REG_SYSCTRL_ACTLR_DISMCYCINT(n) (((uint32_t)(n) << 0) & 0x00000001) 123 124 //***************************************************************************** 125 // 126 // SYSCTRL_ICSR - Interrupt Control and State Register 127 // 128 //***************************************************************************** 129 // Pend an NMI exception. 130 #define AM_REG_SYSCTRL_ICSR_NMIPENDSET_S 31 131 #define AM_REG_SYSCTRL_ICSR_NMIPENDSET_M 0x80000000 132 #define AM_REG_SYSCTRL_ICSR_NMIPENDSET(n) (((uint32_t)(n) << 31) & 0x80000000) 133 134 // Set the PendSV interrupt as pending. 135 #define AM_REG_SYSCTRL_ICSR_PENDSVSET_S 28 136 #define AM_REG_SYSCTRL_ICSR_PENDSVSET_M 0x10000000 137 #define AM_REG_SYSCTRL_ICSR_PENDSVSET(n) (((uint32_t)(n) << 28) & 0x10000000) 138 139 // Remove the pending status of the PendSV exception. 140 #define AM_REG_SYSCTRL_ICSR_PENDSVCLR_S 27 141 #define AM_REG_SYSCTRL_ICSR_PENDSVCLR_M 0x08000000 142 #define AM_REG_SYSCTRL_ICSR_PENDSVCLR(n) (((uint32_t)(n) << 27) & 0x08000000) 143 144 // Set the SysTick exception as pending. 145 #define AM_REG_SYSCTRL_ICSR_PENDSTSET_S 26 146 #define AM_REG_SYSCTRL_ICSR_PENDSTSET_M 0x04000000 147 #define AM_REG_SYSCTRL_ICSR_PENDSTSET(n) (((uint32_t)(n) << 26) & 0x04000000) 148 149 // Remove the pending status of the SysTick exception. 150 #define AM_REG_SYSCTRL_ICSR_PENDSTCLR_S 25 151 #define AM_REG_SYSCTRL_ICSR_PENDSTCLR_M 0x02000000 152 #define AM_REG_SYSCTRL_ICSR_PENDSTCLR(n) (((uint32_t)(n) << 25) & 0x02000000) 153 154 // Indicates whether a pending exception will be serviced on exit from debug 155 // halt state. 156 #define AM_REG_SYSCTRL_ICSR_ISRPREEMPT_S 23 157 #define AM_REG_SYSCTRL_ICSR_ISRPREEMPT_M 0x00800000 158 #define AM_REG_SYSCTRL_ICSR_ISRPREEMPT(n) (((uint32_t)(n) << 23) & 0x00800000) 159 160 // Indicates whether an external interrupt, generated by the NVIC, is pending. 161 #define AM_REG_SYSCTRL_ICSR_ISRPENDING_S 22 162 #define AM_REG_SYSCTRL_ICSR_ISRPENDING_M 0x00400000 163 #define AM_REG_SYSCTRL_ICSR_ISRPENDING(n) (((uint32_t)(n) << 22) & 0x00400000) 164 165 // The exception number of the highest priority pending exception. 166 #define AM_REG_SYSCTRL_ICSR_VECTPENDING_S 12 167 #define AM_REG_SYSCTRL_ICSR_VECTPENDING_M 0x001FF000 168 #define AM_REG_SYSCTRL_ICSR_VECTPENDING(n) (((uint32_t)(n) << 12) & 0x001FF000) 169 170 // Indicates whether there is an active exception other than the exception shown 171 // by IPSR. 172 #define AM_REG_SYSCTRL_ICSR_RETTOBASE_S 11 173 #define AM_REG_SYSCTRL_ICSR_RETTOBASE_M 0x00000800 174 #define AM_REG_SYSCTRL_ICSR_RETTOBASE(n) (((uint32_t)(n) << 11) & 0x00000800) 175 176 // The exception number of the current executing exception. 177 #define AM_REG_SYSCTRL_ICSR_VECTACTIVE_S 0 178 #define AM_REG_SYSCTRL_ICSR_VECTACTIVE_M 0x000001FF 179 #define AM_REG_SYSCTRL_ICSR_VECTACTIVE(n) (((uint32_t)(n) << 0) & 0x000001FF) 180 181 //***************************************************************************** 182 // 183 // SYSCTRL_VTOR - Vector Table Offset Register. 184 // 185 //***************************************************************************** 186 // Vector table base address. 187 #define AM_REG_SYSCTRL_VTOR_VALUE_S 0 188 #define AM_REG_SYSCTRL_VTOR_VALUE_M 0xFFFFFFFF 189 #define AM_REG_SYSCTRL_VTOR_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 190 191 //***************************************************************************** 192 // 193 // SYSCTRL_AIRCR - Application Interrupt and Reset Control Register. 194 // 195 //***************************************************************************** 196 // Register writes must write 0x5FA to this field, otherwise the write is 197 // ignored. 198 #define AM_REG_SYSCTRL_AIRCR_VECTKEY_S 16 199 #define AM_REG_SYSCTRL_AIRCR_VECTKEY_M 0xFFFF0000 200 #define AM_REG_SYSCTRL_AIRCR_VECTKEY(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 201 202 // Indicates endianness of memory architecture. (Little = 0, Big = 1) 203 #define AM_REG_SYSCTRL_AIRCR_ENDIANNESS_S 15 204 #define AM_REG_SYSCTRL_AIRCR_ENDIANNESS_M 0x00008000 205 #define AM_REG_SYSCTRL_AIRCR_ENDIANNESS(n) (((uint32_t)(n) << 15) & 0x00008000) 206 207 // Priority grouping, indicates the binary point position. 208 #define AM_REG_SYSCTRL_AIRCR_PRIGROUP_S 8 209 #define AM_REG_SYSCTRL_AIRCR_PRIGROUP_M 0x00000700 210 #define AM_REG_SYSCTRL_AIRCR_PRIGROUP(n) (((uint32_t)(n) << 8) & 0x00000700) 211 212 // Writing a 1 to this bit reqests a local reset. 213 #define AM_REG_SYSCTRL_AIRCR_SYSRESETREQ_S 2 214 #define AM_REG_SYSCTRL_AIRCR_SYSRESETREQ_M 0x00000004 215 #define AM_REG_SYSCTRL_AIRCR_SYSRESETREQ(n) (((uint32_t)(n) << 2) & 0x00000004) 216 217 // Writing a 1 to this bit clears all active state information for fixed and 218 // configurable exceptions. 219 #define AM_REG_SYSCTRL_AIRCR_VECTCLRACTIVE_S 1 220 #define AM_REG_SYSCTRL_AIRCR_VECTCLRACTIVE_M 0x00000002 221 #define AM_REG_SYSCTRL_AIRCR_VECTCLRACTIVE(n) (((uint32_t)(n) << 1) & 0x00000002) 222 223 // Writing a 1 to this bit causes a local system reset. 224 #define AM_REG_SYSCTRL_AIRCR_VECTRESET_S 0 225 #define AM_REG_SYSCTRL_AIRCR_VECTRESET_M 0x00000001 226 #define AM_REG_SYSCTRL_AIRCR_VECTRESET(n) (((uint32_t)(n) << 0) & 0x00000001) 227 228 //***************************************************************************** 229 // 230 // SYSCTRL_SCR - System Control Register. 231 // 232 //***************************************************************************** 233 // Determines whether a pending interrupt is a wakeup event. 234 #define AM_REG_SYSCTRL_SCR_SEVONPEND_S 4 235 #define AM_REG_SYSCTRL_SCR_SEVONPEND_M 0x00000010 236 #define AM_REG_SYSCTRL_SCR_SEVONPEND(n) (((uint32_t)(n) << 4) & 0x00000010) 237 238 // Determines whether the sleep mode should be regular or deep sleep 239 #define AM_REG_SYSCTRL_SCR_SLEEPDEEP_S 2 240 #define AM_REG_SYSCTRL_SCR_SLEEPDEEP_M 0x00000004 241 #define AM_REG_SYSCTRL_SCR_SLEEPDEEP(n) (((uint32_t)(n) << 2) & 0x00000004) 242 243 // Determines whether the processor shoudl automatically sleep when an ISR 244 // returns to the base-level. 245 #define AM_REG_SYSCTRL_SCR_SLEEPONEXIT_S 1 246 #define AM_REG_SYSCTRL_SCR_SLEEPONEXIT_M 0x00000002 247 #define AM_REG_SYSCTRL_SCR_SLEEPONEXIT(n) (((uint32_t)(n) << 1) & 0x00000002) 248 249 //***************************************************************************** 250 // 251 // SYSCTRL_CCR - Configuration and Control Register. 252 // 253 //***************************************************************************** 254 // Set to force 8-byte alignment for the stack pointer. 255 #define AM_REG_SYSCTRL_CCR_STKALIGN_S 9 256 #define AM_REG_SYSCTRL_CCR_STKALIGN_M 0x00000200 257 #define AM_REG_SYSCTRL_CCR_STKALIGN(n) (((uint32_t)(n) << 9) & 0x00000200) 258 259 // Set to ignore precise data access faults during hard fault handlers. 260 #define AM_REG_SYSCTRL_CCR_BFHFNMIGN_S 8 261 #define AM_REG_SYSCTRL_CCR_BFHFNMIGN_M 0x00000100 262 #define AM_REG_SYSCTRL_CCR_BFHFNMIGN(n) (((uint32_t)(n) << 8) & 0x00000100) 263 264 // Set to enable trapping on divide-by-zero. 265 #define AM_REG_SYSCTRL_CCR_DIV0TRP_S 4 266 #define AM_REG_SYSCTRL_CCR_DIV0TRP_M 0x00000010 267 #define AM_REG_SYSCTRL_CCR_DIV0TRP(n) (((uint32_t)(n) << 4) & 0x00000010) 268 269 // Set to enable trapping of unaligned word or halfword accesses. 270 #define AM_REG_SYSCTRL_CCR_UNALIGNTRP_S 3 271 #define AM_REG_SYSCTRL_CCR_UNALIGNTRP_M 0x00000008 272 #define AM_REG_SYSCTRL_CCR_UNALIGNTRP(n) (((uint32_t)(n) << 3) & 0x00000008) 273 274 // Set to allow unpriveleged software to access the STIR 275 #define AM_REG_SYSCTRL_CCR_USERSETMPEND_S 1 276 #define AM_REG_SYSCTRL_CCR_USERSETMPEND_M 0x00000002 277 #define AM_REG_SYSCTRL_CCR_USERSETMPEND(n) (((uint32_t)(n) << 1) & 0x00000002) 278 279 // Set to enable the processor to enter Thread mode at an execution priority 280 // other than base level. 281 #define AM_REG_SYSCTRL_CCR_NONBASETHRDENA_S 0 282 #define AM_REG_SYSCTRL_CCR_NONBASETHRDENA_M 0x00000001 283 #define AM_REG_SYSCTRL_CCR_NONBASETHRDENA(n) (((uint32_t)(n) << 0) & 0x00000001) 284 285 //***************************************************************************** 286 // 287 // SYSCTRL_SHPR1 - System Handler Priority Register 1. 288 // 289 //***************************************************************************** 290 // Reserved for priority of system handler 7. 291 #define AM_REG_SYSCTRL_SHPR1_PRI_7_S 24 292 #define AM_REG_SYSCTRL_SHPR1_PRI_7_M 0xFF000000 293 #define AM_REG_SYSCTRL_SHPR1_PRI_7(n) (((uint32_t)(n) << 24) & 0xFF000000) 294 295 // Priority of system handler 6, UsageFault. 296 #define AM_REG_SYSCTRL_SHPR1_PRI_6_S 16 297 #define AM_REG_SYSCTRL_SHPR1_PRI_6_M 0x00FF0000 298 #define AM_REG_SYSCTRL_SHPR1_PRI_6(n) (((uint32_t)(n) << 16) & 0x00FF0000) 299 300 // Priority of system handler 5, BusFault. 301 #define AM_REG_SYSCTRL_SHPR1_PRI_5_S 8 302 #define AM_REG_SYSCTRL_SHPR1_PRI_5_M 0x0000FF00 303 #define AM_REG_SYSCTRL_SHPR1_PRI_5(n) (((uint32_t)(n) << 8) & 0x0000FF00) 304 305 // Priority of system handler 4, MemManage. 306 #define AM_REG_SYSCTRL_SHPR1_PRI_4_S 0 307 #define AM_REG_SYSCTRL_SHPR1_PRI_4_M 0x000000FF 308 #define AM_REG_SYSCTRL_SHPR1_PRI_4(n) (((uint32_t)(n) << 0) & 0x000000FF) 309 310 //***************************************************************************** 311 // 312 // SYSCTRL_SHPR2 - System Handler Priority Register 2. 313 // 314 //***************************************************************************** 315 // Priority of system handler 11, SVCall. 316 #define AM_REG_SYSCTRL_SHPR2_PRI_11_S 24 317 #define AM_REG_SYSCTRL_SHPR2_PRI_11_M 0xFF000000 318 #define AM_REG_SYSCTRL_SHPR2_PRI_11(n) (((uint32_t)(n) << 24) & 0xFF000000) 319 320 // Reserved for priority of system handler 10. 321 #define AM_REG_SYSCTRL_SHPR2_PRI_10_S 16 322 #define AM_REG_SYSCTRL_SHPR2_PRI_10_M 0x00FF0000 323 #define AM_REG_SYSCTRL_SHPR2_PRI_10(n) (((uint32_t)(n) << 16) & 0x00FF0000) 324 325 // Reserved for priority of system handler 9. 326 #define AM_REG_SYSCTRL_SHPR2_PRI_9_S 8 327 #define AM_REG_SYSCTRL_SHPR2_PRI_9_M 0x0000FF00 328 #define AM_REG_SYSCTRL_SHPR2_PRI_9(n) (((uint32_t)(n) << 8) & 0x0000FF00) 329 330 // Reserved for priority of system handler 8. 331 #define AM_REG_SYSCTRL_SHPR2_PRI_8_S 0 332 #define AM_REG_SYSCTRL_SHPR2_PRI_8_M 0x000000FF 333 #define AM_REG_SYSCTRL_SHPR2_PRI_8(n) (((uint32_t)(n) << 0) & 0x000000FF) 334 335 //***************************************************************************** 336 // 337 // SYSCTRL_SHPR3 - System Handler Priority Register 3. 338 // 339 //***************************************************************************** 340 // Priority of system handler 15, SysTick. 341 #define AM_REG_SYSCTRL_SHPR3_PRI_15_S 24 342 #define AM_REG_SYSCTRL_SHPR3_PRI_15_M 0xFF000000 343 #define AM_REG_SYSCTRL_SHPR3_PRI_15(n) (((uint32_t)(n) << 24) & 0xFF000000) 344 345 // Priority of system handler 14, PendSV. 346 #define AM_REG_SYSCTRL_SHPR3_PRI_14_S 16 347 #define AM_REG_SYSCTRL_SHPR3_PRI_14_M 0x00FF0000 348 #define AM_REG_SYSCTRL_SHPR3_PRI_14(n) (((uint32_t)(n) << 16) & 0x00FF0000) 349 350 // Reserved for priority of system handler 13. 351 #define AM_REG_SYSCTRL_SHPR3_PRI_13_S 8 352 #define AM_REG_SYSCTRL_SHPR3_PRI_13_M 0x0000FF00 353 #define AM_REG_SYSCTRL_SHPR3_PRI_13(n) (((uint32_t)(n) << 8) & 0x0000FF00) 354 355 // Priority of system handler 12, DebugMonitor. 356 #define AM_REG_SYSCTRL_SHPR3_PRI_12_S 0 357 #define AM_REG_SYSCTRL_SHPR3_PRI_12_M 0x000000FF 358 #define AM_REG_SYSCTRL_SHPR3_PRI_12(n) (((uint32_t)(n) << 0) & 0x000000FF) 359 360 //***************************************************************************** 361 // 362 // SYSCTRL_SHCSR - System Handler Control and State Register. 363 // 364 //***************************************************************************** 365 // Set to enable UsageFault. 366 #define AM_REG_SYSCTRL_SHCSR_USAGEFAULTENA_S 18 367 #define AM_REG_SYSCTRL_SHCSR_USAGEFAULTENA_M 0x00040000 368 #define AM_REG_SYSCTRL_SHCSR_USAGEFAULTENA(n) (((uint32_t)(n) << 18) & 0x00040000) 369 370 // Set to enable BusFault. 371 #define AM_REG_SYSCTRL_SHCSR_BUSFAULTENA_S 17 372 #define AM_REG_SYSCTRL_SHCSR_BUSFAULTENA_M 0x00020000 373 #define AM_REG_SYSCTRL_SHCSR_BUSFAULTENA(n) (((uint32_t)(n) << 17) & 0x00020000) 374 375 // Set to enable MemManageFault. 376 #define AM_REG_SYSCTRL_SHCSR_MEMFAULTENA_S 16 377 #define AM_REG_SYSCTRL_SHCSR_MEMFAULTENA_M 0x00010000 378 #define AM_REG_SYSCTRL_SHCSR_MEMFAULTENA(n) (((uint32_t)(n) << 16) & 0x00010000) 379 380 // Set to pend the SVCall exception. 381 #define AM_REG_SYSCTRL_SHCSR_SVCALLPENDED_S 15 382 #define AM_REG_SYSCTRL_SHCSR_SVCALLPENDED_M 0x00008000 383 #define AM_REG_SYSCTRL_SHCSR_SVCALLPENDED(n) (((uint32_t)(n) << 15) & 0x00008000) 384 385 // Set to pend the BusFault exception. 386 #define AM_REG_SYSCTRL_SHCSR_BUSFAULTPENDED_S 14 387 #define AM_REG_SYSCTRL_SHCSR_BUSFAULTPENDED_M 0x00004000 388 #define AM_REG_SYSCTRL_SHCSR_BUSFAULTPENDED(n) (((uint32_t)(n) << 14) & 0x00004000) 389 390 // Set to pend the MemManageFault exception. 391 #define AM_REG_SYSCTRL_SHCSR_MEMFAULTPENDED_S 13 392 #define AM_REG_SYSCTRL_SHCSR_MEMFAULTPENDED_M 0x00002000 393 #define AM_REG_SYSCTRL_SHCSR_MEMFAULTPENDED(n) (((uint32_t)(n) << 13) & 0x00002000) 394 395 // Set to pend the UsageFault exception. 396 #define AM_REG_SYSCTRL_SHCSR_USGFAULTPENDED_S 12 397 #define AM_REG_SYSCTRL_SHCSR_USGFAULTPENDED_M 0x00001000 398 #define AM_REG_SYSCTRL_SHCSR_USGFAULTPENDED(n) (((uint32_t)(n) << 12) & 0x00001000) 399 400 // Set when SysTick is active. 401 #define AM_REG_SYSCTRL_SHCSR_SYSTICKACT_S 11 402 #define AM_REG_SYSCTRL_SHCSR_SYSTICKACT_M 0x00000800 403 #define AM_REG_SYSCTRL_SHCSR_SYSTICKACT(n) (((uint32_t)(n) << 11) & 0x00000800) 404 405 // Set when PendSV is active. 406 #define AM_REG_SYSCTRL_SHCSR_PENDSVACT_S 10 407 #define AM_REG_SYSCTRL_SHCSR_PENDSVACT_M 0x00000400 408 #define AM_REG_SYSCTRL_SHCSR_PENDSVACT(n) (((uint32_t)(n) << 10) & 0x00000400) 409 410 // Set when Monitor is active. 411 #define AM_REG_SYSCTRL_SHCSR_MONITORACT_S 8 412 #define AM_REG_SYSCTRL_SHCSR_MONITORACT_M 0x00000100 413 #define AM_REG_SYSCTRL_SHCSR_MONITORACT(n) (((uint32_t)(n) << 8) & 0x00000100) 414 415 // Set when SVCall is active. 416 #define AM_REG_SYSCTRL_SHCSR_SVCALLACT_S 7 417 #define AM_REG_SYSCTRL_SHCSR_SVCALLACT_M 0x00000080 418 #define AM_REG_SYSCTRL_SHCSR_SVCALLACT(n) (((uint32_t)(n) << 7) & 0x00000080) 419 420 // Set when UsageFault is active. 421 #define AM_REG_SYSCTRL_SHCSR_USGFAULTACT_S 3 422 #define AM_REG_SYSCTRL_SHCSR_USGFAULTACT_M 0x00000008 423 #define AM_REG_SYSCTRL_SHCSR_USGFAULTACT(n) (((uint32_t)(n) << 3) & 0x00000008) 424 425 // Set when BusFault is active. 426 #define AM_REG_SYSCTRL_SHCSR_BUSFAULTACT_S 1 427 #define AM_REG_SYSCTRL_SHCSR_BUSFAULTACT_M 0x00000002 428 #define AM_REG_SYSCTRL_SHCSR_BUSFAULTACT(n) (((uint32_t)(n) << 1) & 0x00000002) 429 430 // Set when MemManageFault is active. 431 #define AM_REG_SYSCTRL_SHCSR_MEMFAULTACT_S 0 432 #define AM_REG_SYSCTRL_SHCSR_MEMFAULTACT_M 0x00000001 433 #define AM_REG_SYSCTRL_SHCSR_MEMFAULTACT(n) (((uint32_t)(n) << 0) & 0x00000001) 434 435 //***************************************************************************** 436 // 437 // SYSCTRL_CFSR - Configurable Fault Status Register. 438 // 439 //***************************************************************************** 440 // Divide by zero error has occurred. 441 #define AM_REG_SYSCTRL_CFSR_DIVBYZERO_S 25 442 #define AM_REG_SYSCTRL_CFSR_DIVBYZERO_M 0x02000000 443 #define AM_REG_SYSCTRL_CFSR_DIVBYZERO(n) (((uint32_t)(n) << 25) & 0x02000000) 444 445 // Unaligned access error has occurred. 446 #define AM_REG_SYSCTRL_CFSR_UNALIGNED_S 24 447 #define AM_REG_SYSCTRL_CFSR_UNALIGNED_M 0x01000000 448 #define AM_REG_SYSCTRL_CFSR_UNALIGNED(n) (((uint32_t)(n) << 24) & 0x01000000) 449 450 // A coprocessor access error has occurred. 451 #define AM_REG_SYSCTRL_CFSR_NOCP_S 19 452 #define AM_REG_SYSCTRL_CFSR_NOCP_M 0x00080000 453 #define AM_REG_SYSCTRL_CFSR_NOCP(n) (((uint32_t)(n) << 19) & 0x00080000) 454 455 // An integrity check error has occurred on EXC_RETURN. 456 #define AM_REG_SYSCTRL_CFSR_INVPC_S 18 457 #define AM_REG_SYSCTRL_CFSR_INVPC_M 0x00040000 458 #define AM_REG_SYSCTRL_CFSR_INVPC(n) (((uint32_t)(n) << 18) & 0x00040000) 459 460 // Instruction executed with invalid EPSR.T or EPSR.IT field. 461 #define AM_REG_SYSCTRL_CFSR_INVSTATE_S 17 462 #define AM_REG_SYSCTRL_CFSR_INVSTATE_M 0x00020000 463 #define AM_REG_SYSCTRL_CFSR_INVSTATE(n) (((uint32_t)(n) << 17) & 0x00020000) 464 465 // Processor attempted to execute an undefined instruction. 466 #define AM_REG_SYSCTRL_CFSR_UNDEFINSTR_S 16 467 #define AM_REG_SYSCTRL_CFSR_UNDEFINSTR_M 0x00010000 468 #define AM_REG_SYSCTRL_CFSR_UNDEFINSTR(n) (((uint32_t)(n) << 16) & 0x00010000) 469 470 // BFAR has valid contents. 471 #define AM_REG_SYSCTRL_CFSR_BFARVALID_S 15 472 #define AM_REG_SYSCTRL_CFSR_BFARVALID_M 0x00008000 473 #define AM_REG_SYSCTRL_CFSR_BFARVALID(n) (((uint32_t)(n) << 15) & 0x00008000) 474 475 // A bus fault occurred during FP lazy state preservation. 476 #define AM_REG_SYSCTRL_CFSR_LSPERR_S 13 477 #define AM_REG_SYSCTRL_CFSR_LSPERR_M 0x00002000 478 #define AM_REG_SYSCTRL_CFSR_LSPERR(n) (((uint32_t)(n) << 13) & 0x00002000) 479 480 // A derived bus fault has occurred on exception entry. 481 #define AM_REG_SYSCTRL_CFSR_STKERR_S 12 482 #define AM_REG_SYSCTRL_CFSR_STKERR_M 0x00001000 483 #define AM_REG_SYSCTRL_CFSR_STKERR(n) (((uint32_t)(n) << 12) & 0x00001000) 484 485 // A derived bus fault has occurred on exception return. 486 #define AM_REG_SYSCTRL_CFSR_UNSTKERR_S 11 487 #define AM_REG_SYSCTRL_CFSR_UNSTKERR_M 0x00000800 488 #define AM_REG_SYSCTRL_CFSR_UNSTKERR(n) (((uint32_t)(n) << 11) & 0x00000800) 489 490 // Imprecise data access error has occurred. 491 #define AM_REG_SYSCTRL_CFSR_IMPRECISERR_S 10 492 #define AM_REG_SYSCTRL_CFSR_IMPRECISERR_M 0x00000400 493 #define AM_REG_SYSCTRL_CFSR_IMPRECISERR(n) (((uint32_t)(n) << 10) & 0x00000400) 494 495 // A precise data access has occurrred. The faulting address is in BFAR. 496 #define AM_REG_SYSCTRL_CFSR_PRECISERR_S 9 497 #define AM_REG_SYSCTRL_CFSR_PRECISERR_M 0x00000200 498 #define AM_REG_SYSCTRL_CFSR_PRECISERR(n) (((uint32_t)(n) << 9) & 0x00000200) 499 500 // A bus fault on an instruction prefetch has occurred. 501 #define AM_REG_SYSCTRL_CFSR_IBUSERR_S 8 502 #define AM_REG_SYSCTRL_CFSR_IBUSERR_M 0x00000100 503 #define AM_REG_SYSCTRL_CFSR_IBUSERR(n) (((uint32_t)(n) << 8) & 0x00000100) 504 505 // MMAR has valid contents. 506 #define AM_REG_SYSCTRL_CFSR_MMARVALID_S 7 507 #define AM_REG_SYSCTRL_CFSR_MMARVALID_M 0x00000080 508 #define AM_REG_SYSCTRL_CFSR_MMARVALID(n) (((uint32_t)(n) << 7) & 0x00000080) 509 510 // MemManage fault occurred during FP lazy state preservation. 511 #define AM_REG_SYSCTRL_CFSR_MLSPERR_S 5 512 #define AM_REG_SYSCTRL_CFSR_MLSPERR_M 0x00000020 513 #define AM_REG_SYSCTRL_CFSR_MLSPERR(n) (((uint32_t)(n) << 5) & 0x00000020) 514 515 // Derived MemManage fault occurred on exception entry. 516 #define AM_REG_SYSCTRL_CFSR_MSTKERR_S 4 517 #define AM_REG_SYSCTRL_CFSR_MSTKERR_M 0x00000010 518 #define AM_REG_SYSCTRL_CFSR_MSTKERR(n) (((uint32_t)(n) << 4) & 0x00000010) 519 520 // Derived MemManage fault occurred on exception return. 521 #define AM_REG_SYSCTRL_CFSR_MUNSTKER_S 3 522 #define AM_REG_SYSCTRL_CFSR_MUNSTKER_M 0x00000008 523 #define AM_REG_SYSCTRL_CFSR_MUNSTKER(n) (((uint32_t)(n) << 3) & 0x00000008) 524 525 // Data access violation. Address is in MMAR. 526 #define AM_REG_SYSCTRL_CFSR_DACCVIOL_S 1 527 #define AM_REG_SYSCTRL_CFSR_DACCVIOL_M 0x00000002 528 #define AM_REG_SYSCTRL_CFSR_DACCVIOL(n) (((uint32_t)(n) << 1) & 0x00000002) 529 530 // MPU or Execute Never default memory map access violation. 531 #define AM_REG_SYSCTRL_CFSR_IACCVIOL_S 0 532 #define AM_REG_SYSCTRL_CFSR_IACCVIOL_M 0x00000001 533 #define AM_REG_SYSCTRL_CFSR_IACCVIOL(n) (((uint32_t)(n) << 0) & 0x00000001) 534 535 //***************************************************************************** 536 // 537 // SYSCTRL_HFSR - Hard Fault Status Register. 538 // 539 //***************************************************************************** 540 // Debug event has occurred. 541 #define AM_REG_SYSCTRL_HFSR_DEBUGEVT_S 31 542 #define AM_REG_SYSCTRL_HFSR_DEBUGEVT_M 0x80000000 543 #define AM_REG_SYSCTRL_HFSR_DEBUGEVT(n) (((uint32_t)(n) << 31) & 0x80000000) 544 545 // Processor has elevated a configurable-priority fault to a HardFault. 546 #define AM_REG_SYSCTRL_HFSR_FORCED_S 30 547 #define AM_REG_SYSCTRL_HFSR_FORCED_M 0x40000000 548 #define AM_REG_SYSCTRL_HFSR_FORCED(n) (((uint32_t)(n) << 30) & 0x40000000) 549 550 // Vector table read fault has occurred. 551 #define AM_REG_SYSCTRL_HFSR_VECTTBL_S 1 552 #define AM_REG_SYSCTRL_HFSR_VECTTBL_M 0x00000002 553 #define AM_REG_SYSCTRL_HFSR_VECTTBL(n) (((uint32_t)(n) << 1) & 0x00000002) 554 555 //***************************************************************************** 556 // 557 // SYSCTRL_MMFAR - MemManage Fault Address Register. 558 // 559 //***************************************************************************** 560 // Address of the memory location that caused an MMU fault. 561 #define AM_REG_SYSCTRL_MMFAR_ADDRESS_S 0 562 #define AM_REG_SYSCTRL_MMFAR_ADDRESS_M 0xFFFFFFFF 563 #define AM_REG_SYSCTRL_MMFAR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 564 565 //***************************************************************************** 566 // 567 // SYSCTRL_BFAR - Bus Fault Address Register. 568 // 569 //***************************************************************************** 570 // Address of the memory location that caused an Bus fault. 571 #define AM_REG_SYSCTRL_BFAR_ADDRESS_S 0 572 #define AM_REG_SYSCTRL_BFAR_ADDRESS_M 0xFFFFFFFF 573 #define AM_REG_SYSCTRL_BFAR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 574 575 //***************************************************************************** 576 // 577 // SYSCTRL_CPACR - Coprocessor Access Control Register. 578 // 579 //***************************************************************************** 580 // Access priveleges for the Floating point unit. Must always match CP10. 581 #define AM_REG_SYSCTRL_CPACR_CP11_S 22 582 #define AM_REG_SYSCTRL_CPACR_CP11_M 0x00C00000 583 #define AM_REG_SYSCTRL_CPACR_CP11(n) (((uint32_t)(n) << 22) & 0x00C00000) 584 585 // Access priveleges for the Floating point unit. Must always match CP11. 586 #define AM_REG_SYSCTRL_CPACR_CP10_S 20 587 #define AM_REG_SYSCTRL_CPACR_CP10_M 0x00300000 588 #define AM_REG_SYSCTRL_CPACR_CP10(n) (((uint32_t)(n) << 20) & 0x00300000) 589 590 //***************************************************************************** 591 // 592 // SYSCTRL_DEMCR - Debug Exception and Monitor Control Register 593 // 594 //***************************************************************************** 595 // Global enable for all DWT and ITM features. 596 #define AM_REG_SYSCTRL_DEMCR_TRCENA_S 24 597 #define AM_REG_SYSCTRL_DEMCR_TRCENA_M 0x01000000 598 #define AM_REG_SYSCTRL_DEMCR_TRCENA(n) (((uint32_t)(n) << 24) & 0x01000000) 599 600 //***************************************************************************** 601 // 602 // SYSCTRL_STIR - Software Triggered Interrupt Register 603 // 604 //***************************************************************************** 605 // Vector number of the interrupt that should be triggered. 606 #define AM_REG_SYSCTRL_STIR_INTID_S 0 607 #define AM_REG_SYSCTRL_STIR_INTID_M 0xFFFFFFFF 608 #define AM_REG_SYSCTRL_STIR_INTID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 609 610 //***************************************************************************** 611 // 612 // SYSCTRL_FPCCR - Floating-Point Context Control Register. 613 // 614 //***************************************************************************** 615 // Set to enable automatic saving of FP registers on exception entry. 616 #define AM_REG_SYSCTRL_FPCCR_ASPEN_S 31 617 #define AM_REG_SYSCTRL_FPCCR_ASPEN_M 0x80000000 618 #define AM_REG_SYSCTRL_FPCCR_ASPEN(n) (((uint32_t)(n) << 31) & 0x80000000) 619 620 // Set to enable lazy context saving of FP registers on exception entry. 621 #define AM_REG_SYSCTRL_FPCCR_LSPEN_S 30 622 #define AM_REG_SYSCTRL_FPCCR_LSPEN_M 0x40000000 623 #define AM_REG_SYSCTRL_FPCCR_LSPEN(n) (((uint32_t)(n) << 30) & 0x40000000) 624 625 // Able to set DebugMonitor exception to pending on last FP stack allocation. 626 #define AM_REG_SYSCTRL_FPCCR_MONRDY_S 8 627 #define AM_REG_SYSCTRL_FPCCR_MONRDY_M 0x00000100 628 #define AM_REG_SYSCTRL_FPCCR_MONRDY(n) (((uint32_t)(n) << 8) & 0x00000100) 629 630 // Able to set BusFault exception to pending on last FP stack allocation. 631 #define AM_REG_SYSCTRL_FPCCR_BFRDY_S 6 632 #define AM_REG_SYSCTRL_FPCCR_BFRDY_M 0x00000040 633 #define AM_REG_SYSCTRL_FPCCR_BFRDY(n) (((uint32_t)(n) << 6) & 0x00000040) 634 635 // Able to set MemManage exception to pending on last FP stack allocation. 636 #define AM_REG_SYSCTRL_FPCCR_MMRDY_S 5 637 #define AM_REG_SYSCTRL_FPCCR_MMRDY_M 0x00000020 638 #define AM_REG_SYSCTRL_FPCCR_MMRDY(n) (((uint32_t)(n) << 5) & 0x00000020) 639 640 // Able to set HardFault exception to pending on last FP stack allocation. 641 #define AM_REG_SYSCTRL_FPCCR_HFRDY_S 4 642 #define AM_REG_SYSCTRL_FPCCR_HFRDY_M 0x00000010 643 #define AM_REG_SYSCTRL_FPCCR_HFRDY(n) (((uint32_t)(n) << 4) & 0x00000010) 644 645 // Running from Thread mode on last FP stack allocation. 646 #define AM_REG_SYSCTRL_FPCCR_THREAD_S 3 647 #define AM_REG_SYSCTRL_FPCCR_THREAD_M 0x00000008 648 #define AM_REG_SYSCTRL_FPCCR_THREAD(n) (((uint32_t)(n) << 3) & 0x00000008) 649 650 // Running from unprivileged mode on last FP stack allocation. 651 #define AM_REG_SYSCTRL_FPCCR_USER_S 1 652 #define AM_REG_SYSCTRL_FPCCR_USER_M 0x00000002 653 #define AM_REG_SYSCTRL_FPCCR_USER(n) (((uint32_t)(n) << 1) & 0x00000002) 654 655 // Lazy state preservation is active. 656 #define AM_REG_SYSCTRL_FPCCR_LSPACT_S 0 657 #define AM_REG_SYSCTRL_FPCCR_LSPACT_M 0x00000001 658 #define AM_REG_SYSCTRL_FPCCR_LSPACT(n) (((uint32_t)(n) << 0) & 0x00000001) 659 660 //***************************************************************************** 661 // 662 // SYSCTRL_FPCAR - Floating-Point Context Address Register. 663 // 664 //***************************************************************************** 665 // Address of the unpopulated floating-point register space allocated on the 666 // exception stack frame. 667 #define AM_REG_SYSCTRL_FPCAR_ADDRESS_S 0 668 #define AM_REG_SYSCTRL_FPCAR_ADDRESS_M 0xFFFFFFFF 669 #define AM_REG_SYSCTRL_FPCAR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 670 671 //***************************************************************************** 672 // 673 // SYSCTRL_FPDSCR - Floating-Point Default Status Control Register. 674 // 675 //***************************************************************************** 676 // Default value for FPSCR.AHP. 677 #define AM_REG_SYSCTRL_FPDSCR_AHP_S 26 678 #define AM_REG_SYSCTRL_FPDSCR_AHP_M 0x04000000 679 #define AM_REG_SYSCTRL_FPDSCR_AHP(n) (((uint32_t)(n) << 26) & 0x04000000) 680 681 // Default value for FPSCR.DN. 682 #define AM_REG_SYSCTRL_FPDSCR_DN_S 25 683 #define AM_REG_SYSCTRL_FPDSCR_DN_M 0x02000000 684 #define AM_REG_SYSCTRL_FPDSCR_DN(n) (((uint32_t)(n) << 25) & 0x02000000) 685 686 // Default value for FPSCR.FZ. 687 #define AM_REG_SYSCTRL_FPDSCR_FZ_S 24 688 #define AM_REG_SYSCTRL_FPDSCR_FZ_M 0x01000000 689 #define AM_REG_SYSCTRL_FPDSCR_FZ(n) (((uint32_t)(n) << 24) & 0x01000000) 690 691 // Default value for FPSCR.RMode. 692 #define AM_REG_SYSCTRL_FPDSCR_RMODE_S 22 693 #define AM_REG_SYSCTRL_FPDSCR_RMODE_M 0x00C00000 694 #define AM_REG_SYSCTRL_FPDSCR_RMODE(n) (((uint32_t)(n) << 22) & 0x00C00000) 695 696 #endif // AM_REG_SYSCTRL_H 697