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Searched refs:ANA_REG9_PLLHSEL_X5_5 (Results 1 – 5 of 5) sorted by relevance

/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/
A Dlib_clk.h106 #define ANA_REG9_PLLHSEL_X5_5 (0x3U << ANA_REG9_PLLHSEL_Pos) macro
169 #define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5
/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Include/
A Dlib_clk.h140 #define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5
/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/
A Dlib_clk.c428 case ANA_REG9_PLLHSEL_X5_5: in CLK_GetHCLKFreq()
/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Source/
A Dlib_clk.c443 case ANA_REG9_PLLHSEL_X5_5: in CLK_GetHCLKFreq()
/bsp/Vango/v85xx/Libraries/CMSIS/Vango/V85xx/Include/
A Dtarget.h1065 #define ANA_REG9_PLLHSEL_X5_5 (0x3U << ANA_REG9_PLLHSEL_Pos) macro

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