Searched refs:ANA_REG9_PLLHSEL_X5_5 (Results 1 – 5 of 5) sorted by relevance
106 #define ANA_REG9_PLLHSEL_X5_5 (0x3U << ANA_REG9_PLLHSEL_Pos) macro169 #define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5
140 #define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5
428 case ANA_REG9_PLLHSEL_X5_5: in CLK_GetHCLKFreq()
443 case ANA_REG9_PLLHSEL_X5_5: in CLK_GetHCLKFreq()
1065 #define ANA_REG9_PLLHSEL_X5_5 (0x3U << ANA_REG9_PLLHSEL_Pos) macro
Completed in 59 milliseconds